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STW9NA80STN/a14avaiOLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-IN


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STW9NA80
N
74LVX04
LOW VOLTAGE CMOS HEX INVERTER
November 1998 HIGH SPEED: tPD = 4.1 ns (TYP.) at VCC = 3.3V INPUT VOLTAGE LEVEL:
VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION:
ICC = 2 μA (MAX.) at TA = 25 oC LOW NOISE:
VOLP = 0.3 V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 04 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION

The 74LVX04 is a low voltage CMOS HEX
INVERTER fabricated with sub-micron silicon
gate and double-layer metal wiring C2 MOS
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enable high noise
immunity and stable output.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8
INPUT EQUIVALENT CIRCUIT
TRUTH TABLE
PIN DESCRIPTION
RECOMMENDED OPERATING CONDITIONS

1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2V
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
74LVX04

2/8
DC SPECIFICATIONS
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS

1) Worst case package
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND
3) max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz
74LVX04

3/8
AC ELECTRICAL CHARACTERISTICS (Input tr = tf =3 ns)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the
same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/4 (per Gate)
74LVX04

4/8
TEST CIRCUIT
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
74LVX04

5/8
74LVX04
6/8
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