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STVM100DC6FSTN/a2573avaiI睠 LCD/e-paper VCOM calibrator
STVM100DC6FSTMICRON/a18000avaiI睠 LCD/e-paper VCOM calibrator


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STVM100DC6F
I睠 LCD/e-paper VCOM calibrator
June 2013 DocID13236 Rev 9 1/28
STVM100
2 C LCD/e-paper VCOM calibrator
Datasheet - production data
Features
I2 C interface, slave address: 1001111 7-bit adjustable sink current output 2.25 V to 3.6 V logic supply voltage VDD AVDD operating voltages 4.5 V to 20 V for VDD from 2.6 V to 3.6 V 4.5 V to 13 V for VDD from 2.25 V to 3.6 V EEPROM for storing the optimum V COM setting Guaranteed monotonic output over operating
range 400 kHz maximum interface bus speed Operating temperature: –40 °C to 85 °C Available in an 8-pin 3 mm x 3 mm TDFN8 or mm x 3 mm TSSOP8 package
Applications
TFT-LCD panels e-paper and e-book displays
Description

The STVM100 is a programmable VCOM
adjustment solution for thin-film transistor (TFT)
liquid-crystal displays (LCDs) to remove “flickers”.
It is also used in e-paper and e-book applications
to avoid the “ghosting” effect (residual pixels after
display refresh). It can replace a mechanical
potentiometer, so that the factory operator can
physically view the front screen when performing
the VCOM adjustment. This significantly reduces
labor costs, increases reliability, and enables
automation.
The STVM100 provides a digital I2 C interface to
control the sink current output (IOUT). This output
drives an external resistive voltage divider, which
can then be applied to an external VCOM buffer.
Three external resistors R1, R2, and RSET
determine the highest and lowest value of the
VCOM. An increase in the output sink current will
lower the voltage on the external divider so that
the VCOM can be adjusted by 128 steps within this
range. Once the desired VCOM setting is
achieved, it can be stored in the internal
EEPROM that will be automatically recalled
during each power-up.
The STVM100 is available in an 8-pin, 3 mm x mm TDFN8 or 3 mm x 3 mm TSSOP8 package.

Table 1. Device summary
DocID13236 Rev 9 3/28
STVM100 Contents
Contents Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 2-wire bus characteristics and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.1 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.2 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4 VDD power supply ramp-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of tables STVM100
4/28 DocID13236 Rev 9
List of tables

Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Bit P read and write mode values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. TDFN8 3 x 3 x 0.75 mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . . . 24
Table 10. TSSOP8 – 8-lead, thin shrink small outline, 3 mm x 3 mm, mech. data. . . . . . . . . . . . . . . 25
Table 11. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DocID13236 Rev 9 5/28
STVM100 List of figures
List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Connections diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Acknowledgment sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Read/write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. R1, R2, and RSET connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. VDD supply current vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. AVDD supply current vs. AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. VDD supply current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. AVDD supply current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. IOUT error vs. temperature (STVM100 at middle scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. Total unadjusted error vs. DAC setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Differential non-linearity vs. DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. Integral non-linearity vs. DAC setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. AVDD power-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19. Full scale-up response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 20. Full scale-down response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 21. TDFN8 3 x 3 x 0.75 mm, pitch 0.65, package mechanical data . . . . . . . . . . . . . . . . . . . . . 24
Figure 22. TSSOP8 – 8-lead, thin shrink small outline, 3 mm x 3 mm, mech. data. . . . . . . . . . . . . . . 25
Device overview STVM100
6/28 DocID13236 Rev 9
1 Device overview
Figure 1. Logic diagram

Table 2. Pin names and functions See SET pin function in this table for the maximum adjustable sink current setting.
DocID13236 Rev 9 7/28
STVM100 Device overview
Figure 2. Connections diagram
Figure 3. Block diagram
Figure 4. Hardware hookup
Device operation STVM100
8/28 DocID13236 Rev 9
2 Device operation

The STVM100 operates as a slave device on the serial bus. Access is obtained by
implementing a start condition, followed by the 7-bit slave address (1001111), and the eighth
bit for READ/WRITE identification. The volatile DAC register and non-volatile EEPROM
values can be read out or written in.
2.1 2-wire bus characteristics and conditions

This bus is intended for communication between different ICs. It consists of two lines: a bi-directional data signal (SDA). a clock signal (SCL).
The SDA and SCL lines must be connected to a positive supply voltage via a pull-up
resistor. The following protocols have been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control
signals.
2.1.1 Bus not busy

Both data and clock lines remain high.
2.1.2 Start data transfer

A change in the data line state from high-to-low while the clock is high indicate the start
condition.
2.1.3 Stop data transfer

A change in the data line state from low-to-high while the clock is high indicates the stop
condition.
DocID13236 Rev 9 9/28
STVM100 Device operation
2.1.4 Data valid

The data on the SDA line must be stable during the high period of the clock. The high or low
state of the data line can only change when the clock signal on the SCL line is low (see
Figure 5). The data on the line may be changed during the clock signal low period. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The
number of data bytes transferred between the start and stop conditions is not limited. The
information is transmitted byte-wide and each receiver acknowledges transmission with a
ninth bit.
By definition, the device that gives out a message is called “transmitter”, the device that gets
the message is called “receiver”. The device that controls the message is called the
“master”. The devices controlled by the master are called “slave” devices.
Figure 5. Serial bus data transfer sequence
Device operation STVM100
10/28 DocID13236 Rev 9
2.1.5 Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level signal put on the bus by the receiver, whereas the master generates an extra
acknowledge-related clock pulse (see Figure 6). A slave receiver which is addressed is
obliged to generate an acknowledge signal after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges transmissions has to pull down the SDA line during the
acknowledge clock pulse in such a way, that the SDA line is a stable low during the high
period of the acknowledge-related clock pulse. The setup and hold times must be taken into
account. A master receiver must signal an end of transmitted data to the slave transmitter
by not generating an acknowledge on the last byte that has been clocked out of the slave. In
this case, the transmitter must leave the data line high to enable the master to generate the
stop condition.
Figure 6. Acknowledgment sequence
DocID13236 Rev 9 11/28
STVM100 Device operation
2.2 Read mode

In READ mode, after the start condition, the master sets the slave address (see Figure 7).
Followed by the READ/WRITE mode control bit (R/W=1) and the acknowledge bit, the value
in DAC register will be transmitted and the master receiver will send an acknowledge bit to
the slave transmitter. Finally the stop condition will terminate the READ operation. In READ
mode, the valid data is the first 7 bits and the P bit (the eight bit) is don’t care.
2.3 Write mode

In WRITE mode the master transmits to the STVM100 slave receiver. The bus protocol is
shown in Figure 7. Following the start condition and slave address, a logic '0' (R/W = 0) is
placed on the bus to identify a WRITE operation. After the acknowledgement by the slave,
the data will be transmitted to the slave with the 7-bit which indicates the data is valid as well
as the eighth bit “P” for the register’s identification. When P = 1, the DAC register is written
to, and when P = 0, the EEPROM is written to (Programming). After receiving the data, the
slave will generate an acknowledge signal, then a stop condition will terminate the WRITE
operation. STVM100 is pre-programmed with 80H in the EEPROM after manufacturing.
A period of tW (see Table 8) is needed for EEPROM programming. During this period, the
slave will not acknowledge any WRITE operation.
The bit P values in both READ and WRITE modes are shown in Table3.
Figure 7. Read/write mode sequence


2.4 V DD power supply ramp-up

The ramp-up from 10% VDD to 90% VDD level should be achieved in less than or equal to
10ms to ensure that the EEPROM and power-on reset circuits are synchronized, and the
correct value is read from the EEPROM.
Table 3. Bit P read and write mode values
Application information STVM100
12/28 DocID13236 Rev 9
3 Application information

The STVM100 is a programmable VCOM calibrator to remove flickers in TFT-LCDs or to
avoid the “ghosting effect” (residual pixels during refresh) in e-paper and e-books. It
provides a digital I2 C interface to control the sink current output. This output drives an
external resistive voltage divider, which can then be applied to an external VCOM buffer.
The highest and lowest VCOM value is determined by three resistors, R1, R2, and RSET. The
connection is shown in Figure8.
The sink current from the STVM100 OUT pin is given in Equation 1. This current then flows
through RSET. This current must be less than 120 µA (see ISET value in Table 7 on page 16).
Figure 8. R1, R2, and RSET connection

Note: In order to choose an appropriate device to buffer the output of STVM100, please see our
operational amplifier product portfolio available at:
http:///stonline/products/families/amplifiers_comparators/amplifiers_comparators.htm
Note: “D” is a user-selected value, an integer ranging from 0 to 127.
DocID13236 Rev 9 13/28
STVM100 Application information
Maximum ratings STVM100
14/28 DocID13236 Rev 9
4 Maximum ratings

Stressing the device above the ratings listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4. Absolute maximum ratings Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
DocID13236 Rev 9 15/28
STVM100 DC and AC parameters DC and AC parameters

This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5. Designers should check that the operating conditions in their circuit match the
operating conditions when relying on the quoted parameters.


Table 5. Operating and AC measurement conditions
Table 6. Capacitances
Effective capacitance measured with power supply at 3 V. Sampled only, not 100% tested. At 25 °C, f = 1 MHz.
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