STV9556 ,7.5 NS TRIPLE CHANNEL HIGH VOLTAGE VIDEO AMPLIFIERELECTRICAL CHARACTERISTICS . . . . 56 THEORY OF OPERATION . . . . 76.1 General ..
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STV9556
7.5 NS TRIPLE CHANNEL HIGH VOLTAGE VIDEO AMPLIFIER
September 2003 1/24
Version 4.1
STV95567.5 NS TRIPLE-CHANNEL HIGH VOLT AGE VIDEO AMPLIFIER
BLOCK DIAGRAM PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS4 THERMAL DATA
5 ELECTRICAL CHARACTERISTICS
Note 1: The STV9556 goes into stand-by mode when Vcc is switched off (<1.5V).
In stand-by mode, Vout is set to low level.
Note 2: Matching measured between each channel.
Note 3: Pulsed current width < 50μs
ELECTRICAL CHARACTERISTICS (continued)
Note 4: Matching measured between each channel.
Note 5: PICTURE BOOST condition (video amplitude at 50V or above) is used in some applications when displaying
still picture or moving video. In this condition the high level of contrast improves the pictures quality at the
expense of the video performances (tR, tF and Overshoot) which are slightly deteriorated.
Figure 1. AC test circuit
THEORY OF OPERATION6.1 General
The STV9556 is a three-channel video amplifier supplied by a low supply voltage: VCC (typ.12V) and a
high supply voltage: VDD (up to 115V).
The high values of VDD supplying the amplifier output stage allow direct control of the CRT cathodes (DC
coupling mode).
In DC coupling mode, the application schematic is very simple and only a few external components are
needed to drive the cathodes. In particular, there is no need of the DC-restore circuitry which is used in
classical AC coupling applications.
The output voltage range is wide enough (Figure 2) to provide simultaneously :
– Cut-off adjustment (typ. 25V)
– Video contrast (typ. up to 40V),
– Brightness (with the remaining voltage range).
In normal operation, the output video signal must remain inside the linear region whatever the cut-off,
brightness and contrast adjustments are.
Figure 2. Output signal, level adjustments
6.2 Output voltage
A very simplified schematic of each STV9556 channel is shown in Figure3.
The feedback network of each channel is integrated with a typical built-in voltage gain of G=20 (40k/2k).
The output voltage VOUT is given by the following formula:
VOUT =(G+1)xV REF - (G xVIN)
for G= 20 and VREF= 5.6V, we have
VOUT =117.6 -20x VIN
Figure 3. Simplified schematic of one channel
POWER DISSIPATIONThe total power dissipation is the sum of the static DC and the dynamic dissipation: TOT = P STAT + P DYN.
The static DC power dissipation is approximately: STAT = VDD x IDD + VCC x ICC
The dynamic dissipation is, in the worst case (1 pixel On/ 1 pixel Off pattern): DYN = 3 VDD x CL x V OUT(PP) x f x K (see Note 6)
where f is the video frequency and K the ratio between the active line and the total horizontal line duration.
Example:
for VDD = 110V, VCC = 12V,
IDD = 25mA, ICC = 60mA, OUT =40VPP, f= 40MHz,
CL = 8pF and K = 0.72.
We have: STAT = 3.47W and P DYN = 3.04W
Therefore:
PTOT = 6.51W.
Note 6: This worst thermal case must only be considered for TJmax calculation. Nevertheless, during the average life
of the circuit, the conditions are closer to the white picture conditions.
TYPICAL PERFORMANCE CHARACTERISTICSVDD=110V, VCC=12V, CL=8pF, RP=200Ω, ΔV=40VPP , unless otherwise specified - see Figure1
Figure 4. STV9556 pulse response Figure 5. V OUT versus VIN
Figure 8. Speed versus offset Figure 9. Speed versus load capacitance
INTERNAL SCHEMATICSFigure 10. RGB inputs Figure 11. RGB outputs
Figure 12. VDD Figure 13. VCC
Figure 14. GNDP Figure 15. GNDA
APPLICATION HINTS10.1 How to choose the high supply voltage value (VDD) in DC coupling mode
The VDD high supply voltage must be chosen carefully. It must be high enough to provide the necessary
video adjustment but set to minimum value to avoid unecessary power dissipation.
Example (see Figure 2):
The following example shows how the optimum VDD voltage value is determined:
– Cut-off adjustment range (B) : 25V
– Max contrast (D) : 40V
Case 1:
10V Brightness (C) adjusted by the preamplifier :
VDD =A+B +C+D+EDD= 15V+ 25V+ 10V+ 40V+ 17V= 107V
Case 2:
10V Brightness (C) adjusted by the G1 anode:
VDD =A+B +D+E
VDD =15V +25V +40V +17V= 97V
10.2 Arcing Protection: schematics
As the amplifier outputs are connected to the CRT cathodes, special attention must be given to protect
them against possible arcing inside the CRT.
Protection must be considered when starting the design of the video CRT board. It should always be
implemented before starting to adjust the dynamic video response of the system.
The arcing network that we recommend (see Figure 16) provides efficient protection without deteriorating
the amplifier video performances.
The total resistance between the amplifier and the CRT cathode (R10+R11) protects the device against
overvoltages. We recommend to use R10+R11 > 200 Ω.
Spark gaps are strongly recommended for arcing protection.
