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STV7710-STV7710/GY-A -STV7710TCP
VACUUM FLUORESCENT DISPLAY (VFD)DRIVER
STV7710/WAFVacuum Fluorescent Display (VFD) Driver
FEA TURES 96 Outputs VFD Driver 90V Absolute Maximum Supply 3.3V/5V compatible logic -40/30mA source/sink output MOS -50/50mA source/sink output diode 1 bit data bus (40MHz) BCD process Packaging: Die Form
DESCRIPTIONSTV7710/WAF is a driver for vacuum fluorescent
display (VFD) designed in the ST proprietary BCD
high voltage technology. Using a 1 bit wide data
bus, it can control 96 high current & high voltage
outputs. The STV7710/WAF is supplied with a
separated 70V power output supply. All command
inputs are CMOS and 3.3V logic levels compatible.
ORDERING INFORMATION
STV7710/WAF able of content
Chapter 1 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Chapter 2 DIE PIN OUT / DIE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Chapter 3 MECHANICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53.1 Alignment marks specification ..............................................................................................5
3.2 Pads specification ................................................................................................................5
Chapter 4 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94.1 Pin description ......................................................................................................................9
4.2 Data bus configuration .........................................................................................................9
4.3 Description .........................................................................................................................10
Chapter 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Chapter 6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Chapter 7 AC TIMING REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chapter 8 AC TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Chapter 9 INPUT/OUPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Chapter 10 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
STV7710/WAF BLOCK DIAGRAM BLOCK DIAGRAM
Figure 1: STV7710/WAF block diagram
DIE PIN OUT / DIE DESCRIPTION STV7710/WAF DIE PIN OUT / DIE DESCRIPTION
Figure 2: STV7710/WAF die pinout
STV7710/WAF MECHANICAL SPECIFICATION MECHANICAL SPECIFICATION
3.1 Alignment marks specification
3.2 Pads specificationThe reference is the centre of the die (x=0, y=0)
Figure 3: Alignment marks
Table 1: Top side from left to right
MECHANICAL SPECIFICATION STV7710/WAF
Table 2: Bottom side from right to left
Table 3: RIGHT SIDE from top to bottom
STV7710/WAF MECHANICAL SPECIFICATION
Table 4: LEFT SIDE from bottom to top
Table 3: RIGHT SIDE from top to bottom
MECHANICAL SPECIFICATION STV7710/WAF
Table 4: LEFT SIDE from bottom to top
STV7710/WAF CIRCUIT DESCRIPTION CIRCUIT DESCRIPTION
4.1 Pin description
4.2 Data bus configurationThis table describes the position of the first data sampled by the first rising edge of the CLK signal.
Table 5: STV7710/WAF pin description
Table 6: STV7710/WAF data bus configuration
CIRCUIT DESCRIPTION STV7710/WAF
4.3 DescriptionSTV7710/WAF includes all the logic and power circuits necessary to drive electrodes of a vacuum
fluorescent display (VFD). Binary values of each pixel of the displayed line are loaded into the shift
register DATA_A/B data bus. Data is shifted at each low to high transition of the CLK clock. After 96
shifts, the data is available at the output of the shift register. This output can be used to cascade
several Ics to drive higher resolution displays.
The forward /reverse (F/R) input is used to select the direction of the shift register. Data input/output
status is set according to the selected direction (refer to Table6).
The maximum frequency of the shift clock is 40MHz.
When the STB signal is high, data are transferred from the shift register to the latch and power
output stages.
All the output data are kept memorized and held in the latch stage when the latch input STB is set
at low level.
Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the
application. Also, make sure that TEST input pin is connected to ground (Figure8).
STV7710/WAF is supplied with a 5 volt power supply. All the logic inputs can be driven either by 5V
CMOS logic, or by 3.3V CMOS logic.
Table 7: Shift register truth table
Table 8: Power output truth table
