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STV7699
PLASMA DISPLAY PANEL DATA DRIVER
STV7699PLASMA DISPLA Y PANEL DA TA DRIVER
January 1999
PRODUCT PREVIEW 64 OUTPUTS PLASMA DISPLAY DRIVER. 170V ABSOLUTE MAXIMUM SUPPLY. 5V SUPPLY FOR LOGIC. 50/40mA SOURCE / SINK OUTPUT. 60/60mA SOURCE / SINK OUTPUT DIODE. 64-BIT SHIFT REGISTER (20MHz). BLK, POLARITY AND HIZ CONTROL. BCD TECHNOLOGY. DIE or 100-PIN PQFP PACKAGE
DESCRIPTIONThe STV7699 is a Plasma Display Panel (PDP)
data driver implemented in ST’s proprietary BCD
technology. Using a 4-bit wide cascadable shift
register, it drives 64 high current & high voltage out-
puts. By serialy connecting several STV7699, any hori-
zontal pixel definition can be performed. The 20MHz
shift clock gives an equivalent 80MHz shift register.
The STV7699 is supplied with a separated 170V
power output supply and a 5V logic supply.
PIN CONNECTIONSAll command inputs are CMOS compatible.
The STV7699 package is a 100-pin PQFP . It is also
available as die.
1/9
PIN ASSIGNMENT (PQFP100)
PIN ASSIGNMENT (Power Outputs)
STV76992/9
PAD DIMENSIONS (in μm)The reference is the center of the die (x = 0, y = 0).
LEFT SIDE from top to bottom
BOTTOM SIDE from left to right
Right SIDE from bottom to top
TOP SIDE from right to left
STV76993/9
CIRCUIT DESCRIPTIONThe STV7699 contains all the logic and the power
circuits necessary to drive the colums of a Plasma
Display Panel (P.D.P.). Data are shifted at each low
to high transition of the (CLK) shift clock. Data are
input in a 4-bit wide data bus to A1 - A4 input (case
of forward shift mode ; F/R = low). After 16 shifts,
the first nibble is available at the serial outputs
B1 - B4. These outputs can be used to cascade
several drivers to performed any horizontal resolu-
tion. CLK, Ai and Bi inputs are Smith trigger inputs
to improve the noise margin.
The Forward /Reverse (F/R) input is used to select
the direction of the shift register.
The maximum frequency of the shift clock is
20MHz.
All the output data are held and memorized into the
latch stage when the Latch input (STB) is high.
When it is at low level, data are transferred from
the shift register to the latch and to the output power
stage.
Output state can be forced to high impedance by
pulling low HIZ input.
When BLK is Low, all the outputs are forced to low
level or high level according to POL signal value.
Output state copy data that was input, with the
same polarity, when BLK, HIZ and POL are High.
VSSLOG, VSSSUB and VSSP are not internally con-
nected.
VSSLOG and VSSSUB must be connected as close as
possible to the logical reference ground of the
application.
Table 1 : Power Output Truth Table
Note 1 : Qn is the value memorised in the latch stage ; it is the value
of the parallel shift register output stage after n Clock
pulses.
A data loaded in the shift register is read on the
output power stage without inversion of its polarity.
Table 2 : Control Table
BLOCK DIAGRAM
STV76994/9
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
Notes :1. For PQFP100 packaging. Through all power outputs : with power dissipation lower or equal than Ptot and junction temperature lower or equal than Tjmax.
ELECTRICAL CHARACTERISTICS(VCC = 5V, VPP = 160V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25°C, fCLK = 20MHz,
unless otherwise specified)
SUPPLY
OUTPUT
INPUT (CLK, STB, BLK, HIZ, Ai, Bi)
Notes :3. Compatible with power dissipation and Tjoper ≤ 125°C. See test diagram.
STV76995/9
AC TIMINGS REQUIREMENTS(VCC = 4.5V to 5.5V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10ns)
AC TIMING CHARACTERISTICS(VCC = 5V, VPP = 65V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25°C, VILMax. = 0.2VCC, VIHMin. = 0.8VCC,
VOH = 4.0V, VOL = 0.4V, CL = 10pF, unless otherwise specified)
Notes :5. See test diagram. One output among 64, loading capacitor COUT = 50pF, other outputs at low level.
STV76996/9
