STV0974 ,Mobile Imaging DSPelectrical characteristics . . . . . . . 55Chapter 6 Package mechanical data . .616.1 P ..
STV0974/TR ,Mobile Imaging DSPApplications■ M-JPEG operation at up to 30 frame/s at VGA resolution■ Mobile phone embedded camera ..
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STV1601A ,SERIAL INTERFACE TRANSMISSION ENCODERAPPLICATIONS EXAMPLES.Serial data transmission of digital televisionsignal 525-625 lines.4:2:2 comp ..
STV160NF02L ,NELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STV160NF02LAT4 ,N-CHANNEL 20V 0.0018 OHM 160A POWERSO-10 STRIPFET POWER MOSFETELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
T7024 ,The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth and WDCT.Features Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (P Typically 23 dBm ..
T7024 ,The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth and WDCT.Features Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (P Typically 23 dBm ..
T7024 ,The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth and WDCT.Features Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (P Typically 23 dBm ..
T7024 ,The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth and WDCT.Features Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (P Typically 23 dBm ..
T7024-PGP ,Bluetooth⑩/ISM 2.4-GHz Front- End ICFeatures Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (P Typically 23 dBm ..
T7024-PGPM ,Bluetooth/ISM 2.4 GHz front-end IC.Features Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (P Typically 23 dBm ..
STV0974-STV0974/TR
Mobile Imaging DSP
Rev. 3
STV0974
Features Supports VS6552 - 640 x 480 (VGA) color
CMOS image sensor Supports VisionLink low EMI link to image
sensor Specialized video processor for noise/defect
filtering, color reconstruction, sharpness
enhancement and radial corrections Programmable gamma correction for LCD
support Programmable cropping, down-sizing by 1.5,
2, 2.5, 3, 4, 5 and 6, MMS (Multi Media
Messaging Service) digital zoom JPEG compression, with programmable
target file size M-JPEG operation at up to 30 frame/s at VGA
resolution Programmable pixel output format including
ITU-R 656 modes, RGB viewfinder modes and
JPEG baseline Flashgun control Flexible host interface: 8-bit data /Hsync /Vsync video output interface
and I²C camera control interface 8-bit microprocessor interface with 2 Kbyte
video FIFO for JPEG data, 10 Kbyte for non-
JPEG data, interrupt and DMA requests
Multi-mode exposure control and color
balance 30 µW ultra low-power standby 6 x 6 mm TFBGA low-footprint & lead-free
package
DescriptionThe STV0974 is a low power digital image
processor designed for the VS6552 color VGA
image sensor. The STV0974 uses advanced image
processing techniques to deliver high quality VGA
images at up to 30 frames per second
(frame/s). The sensor data received via the low EMI
sensor interface is processed in real time: this
includes pixel defect correction, color interpolation,
image sharpness enhancement, selective noise
filtering, cropping and scaling, allowing digital zoom
for ViewFinder or MMS applications. Finally the
image can be JPEG-compressed in real-time. The
STV0974 also performs sensor housekeeping
functions such as automatic exposure and white
balance controls.
Applications Mobile phone embedded camera system PDA embedded camera or accessory camera Wireless security camera
Technical Specifications
Ordering InformationMobile Imaging DSP
STV0974
Contents
Chapter 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.1 Viewfinder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Still features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Live features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Chapter 2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chapter 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chapter 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Video processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 Video compression (VC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 Video output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.7 Power management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.9 Camera control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.10 Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Chapter 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.5 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .616.1 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.2 Package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 7 PCB layout guide lines for the STV0974 and VS6552 . . . . . . . . . . . . . . . . . . . .64
STV0974Chapter 8 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Chapter 9 Evaluation kit and demonstration boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
STV0974 Overview
1 OverviewThe STV0974 is a mobile imaging digital signal processor which, when used with VS6552 CMOS
color VGA image sensor from STMicroelectronics, performs all the required data processing to
deliver good quality Viewfinder, still and live color images. The STV0974 performs high quality color
processing on images, achieving JPEG compression if requested and transfers them to a
baseband through one of the available interfaces.
Data is transferred from sensor to STV0974 through Low Electromagnetic Interference (EMI)
interface, using the sensor data transfer protocol over LVDS.
Data is transferred from STV0974 to Baseband through the video output interface. In video mode, the processor streams video data in a format
which closely follows the data format specified in the ITU-R656 standard. through the microprocessor Interface. In microprocessor mode, the video data is stored in a
small FIFO before is it pulled out of the asynchronous microprocessor interface by the host
system (with DMA support).
1.1 Viewfinder modeWhen connected to microprocessor interface or video output interface, the STV0974 can process
Viewfinder image up to 30 frame/s.
1.2 Still featuresWhen requested by the baseband, the STV0974 captures bayer data from the sensor. Data is then
color processed, down-scaled and/or compressed and sent through video output or microprocessor
interface. In still mode, the first image produced has a guaranteed good exposure and color
balance for single shot capture.
1.3 Live features When connected to microprocessor interface or video output interface, the STV0974 can process
live video up to 30 frame/s and eventually proceed to down-scaling and compression with on-chip
Motion JPEG. Live mode is intended for capture of video sequences.
Functional block diagram STV0974 Functional block diagram
Figure 1: Functional block diagram
STV0974 Signal description
3 Signal description
Table 1: STV0974 signal description
Table 2: Host interface pins - output modes Flash Strobe Output
Functional description STV0974
4 Functional description
4.1 OverviewThe processor includes a chain of dedicated video data processing blocks controlled by a
microprocessor. The processing blocks perform the main video pipe processing while the
microprocessor manages the interactions between the sensor, the functional blocks and the host.
The host controls and monitors the STV0974 via a set of read/write registers accessible via the I2C
interface for the streaming video mode and via the asychronous microprocessor interface for the
microprocessor mode.
In video mode, the processor streams video data in a format which closely follows the data format
specified in the ITU-R656 standard.
In microprocessor mode, the video data is stored in a small FIFO before is it pulled out of the
asynchronous microprocessor interface by the host system (with DMA support).
4.1.1 Video pipe block descriptionPlease refer to the block diagram (Figure1).
Sensor interface This block decodes the incoming serial data stream from the sensor (raw bayer data) and converts it into a parallel form for the processing chain.
Video processor The video processor converts the raw bayer data from the sensor to RGB or YUV processed data by applying a number of filters to the data then scaling and converting the
data into either one of the RGB modes or into YUV mode.
Video JPEG compressor The video compressor converts the processed data from the video processor and converts the data into JPEG format. The compression ratio applied to the image can
be controlled by the microprocessor.
Streaming video output port In streaming video mode the data from either the video processor or the video compressor is enclosed in a format which closely follows the data format specified in
the ITU-R656 standard.
Microprocessor interface In microprocessor interface mode, the data from the video processor or video compressor is stored in a FIFO. The interface informs the system via an IRQ or a DRQ that
the FIFO is filling up. The system then has to pull some of the data from the STV0974 via the
microprocessor interface.
STV0974 Functional description
4.1.2 Control
Register map The STV0974 is controlled via a register map that is maintained by the STV0974 microprocessor. Each register in the map has an address and contains either read or read/write
data. The read only registers detail the current state of the STV0974. Read/write registers can be
written to in order to modify the default behavior of the STV0974. The map is accessed via I2 C or
via the microprocessor interface.
Micro processor interface In microprocessor interface mode the STV0974 register map can be accessed by writing the address of the register to the port and then reading or writing the register
value.
Video output interface In streaming video mode, the STV0974 register map can be accessed via the I2 C port on the STV0974. The STV0974 is addressed by supplying the device address, register
address and value to be written or read.
Microprocessor The microprocessor maintains the system interface via the register map. Any changes in system state are reflected in this map by the microprocessor and any changes
commanded by the host system via this interface are then applied by the microprocessor.
When the system is commanded to change state, the microprocessor configures the functional
blocks from the STV0974 and the sensor into the requested mode. The register map is updated
accordingly to reflect the new state of the hardware.
The microprocessor monitors statistics gathered from the incoming image data and responds to
changes in images. It adapts the functional block settings to correct for shifts in environmental
conditions such as light level and illumination color temperature. The microcontroller will optimize
these settings to provide the best quality image on all occasions.
4.1.3 Other functional blocks
Power management The hardware state of the STV0974 can be controlled by the power down pin (PDN). Upon the application of power to the STV0974 and PDN release, the STV0974 power-on-
reset cell issues a timed reset pulse and then releases the STV0974 into its boot state.
The power-on-reset cell which output is the POR signal, is externally connected to the RST pin.
Clocks In sleep mode, the STV0974 clock is derived from the clock signal applied to the CLK pin. In all other modes, the STV0974 clock is derived from the high speed clock received from the
sensor.
Functional description STV0974
4.2 Sensor interface
4.2.1 Features Low electromagnetic interference (EMI) interface with CMOS image sensors High speed serial receiver, with data and clock inputs Up to 120 Mbit/s operation using very low voltage differential signaling (vLVDS) VisionLink transfer protocol I²C compliant master controller, 1.8 V interface, up to 400 kHz operation
4.2.2 DescriptionThe STV0974 sensor interface is dedicated to the VS6552 image sensor that uses the VisionLink
data transfer protocol over vLVDS. This includes: An I²C master controller supporting 1.8 V interface and 400 kHz operation. The I²C master port
signals are MSDA and MSCL that require external pull-up resistors. Internally, the I²C master is
a peripheral of the microprocessor control unit. Two vLVDS receivers for sensor data and clock signals, PDATA and PCLK differential pairs
respectively. Each receiver accepts 1.8 V LVDS signals A VisionLink data synchronization and extraction unit, which extracts image timing references,
active video and sensor status information. The extracted video stream in raw Bayer format
along with active video strobes are connected to the video processing unit. The sensor status
information is presented to the microprocessor control unit.
STV0974 Functional description
4.3 Video processing unit
4.3.1 Features Low-power dedicated hardware video processing unit, pipeline operation up to VGA resolution
30 Hz Image sensor correction stage including pixel defect correction and fixed pattern noise (FPN)
cancellation Color interpolation stage with anti-aliasing and color matrix compensation Optical system compensation stage including anti vignetting and sharpness enhancement Noise reduction filter Programmable gamma and s-curve gamma for LCD support Full frame statistics gathering for exposure and color balance controls Programmable output image size (downscale by 1.5, 2, 2.5, 3, 4, 5 and 6)
4.3.2 Overview
Fixed Pattern Noise (FPN) cancellation The FPN cancellation algorithm removes any column variability over the video area.
Statistics gathering Image statistics are gathered on the full resolution input image and forwarded to the camera control unit for exposure and color balance control loops.
Anti vignetting A radial gain is applied to the image luminance to compensate for possible luminance loss in the corners of the image due to an imperfect lens system.
Defect correction The defect correction algorithm can detect and correct any defective pixels in a sensor array.
Noise reduction filter The noise reduction filter is based on an adaptive algorithm. This algorithm performs filtering but does not affect image areas including significant information.
Color interpolation Each pixel RGB components are calculated by interpolation of the incoming Bayer pattern.
Figure 2: Video processing unit
Functional description STV0974
Color matrix Each pixel (RGB vector) is multiplied by a color matrix to adjust color balance. Viewfinder and live settings are independent to allow for optimization of both LCD display and
capture for later viewing (i.e. on a PC).
Sharpness enhancement A sharpening two-dimensional mask is applied to Green only and from interpolation. The resulting data is added (with a gain factor) to the matrix RGB data.
Downscaler The downscaler unit extracts a rectangular region of interest and resizes the image by resampling video data. Standard image size such as CIF , QVGA and QCIF are available as well as
a fully programmable custom size:
When custom size is selected, the crop and scale parameters are subject to the following
constraints to ensure proper operation: Output image size must be in 8 x 8 pixels increments Scaling factor can be any value giving an input image size within input limits
Gamma correction A non-linear gain is applied to each pixel’s RGB components to compensate for the display’s non-linearity. A standard curve is available for image capture for later viewing on a
PC and an S-curve is available for LCD display.
Coder The coder unit converts the internal RGB video stream to a user selectable output video format. It is based on a YUV digital video encoder with embedded synchronization codes,
compliant with [1], extended with the support of RGB formats for viewfinder usage, as shown in
Table4.
Table 3: Standard image size, VGA input
STV0974 Functional descriptionByte ordering assumes a little endian memory system, i.e. in 16-bit formats, the least significant
byte is sent first. For example, the UYVY format produces the sequence U Y0 V Y1 ... as per [1].
Note: Nevertheless various options are available to suit memory system requirements: Byte ordering can be changed to big endian In YUV formats, the U and V components can be swapped In RGB formats, the R and B components can be swapped
YUV format processing The RGB pixel is converted to YUV coordinates according to ITU-R BT601 specification. The YUV coordinates are then rounded and clipped for an 8-bit
representation. T o produce a 4:2:2 digital component video, U and V components are filtered and
down sampled by a factor of 2, coincident with Y sampling time.
RGB format processing Dithering: In order to avoid contouring effects on low color depth displays, the RGB components are dithered prior to truncation to the required number of bits.
Framing: The output frame is produced by performing the following steps: Blanking code insertion: During video blanking intervals, blanking codes are inserted in the output stream. The default blanking code is the 16-bit pattern 0x1080, corresponding to Y =
0x10 and U/V = 0x80 as per [1].
Synchronization pattern detection and correction: The coder performs detection of various synchronization patterns and applies a correction according to the current output format.
Video Timing Reference Code Insertion: A 4-byte sequence is inserted at the beginning and the end of each digital video line to delineate lines and frames in the video stream. The
sequence is defined in [1] as FF 00 00 XY, where the XY byte is defined by:
SAV (Start of Active Video) is defined as the 4-byte sequence where H = 0.
EAV (End of Active Video) is defined as the 4-byte sequence where H = 1.
Table 4: Output video formats
Table 5: XY bits definition
Functional description STV0974
4.4 Video compression (VC)Real time video compression permits a frame rate of 30 frame/s in any mode at VGA.
The JPEG compression engine is a standard baseline sequential JPEG encoder [2].
The compression ratio can be modified by applying a multiplication factor on the quantization table.
The quantization table can be scaled from a factor of 1/8 to a factor of 8.
The STV0974 video compression block includes a baseline DCT JPEG encoder compliant with
ISO DIS 10918-1.
The JPEG encoder has the following characteristics: baseline sequential DCT based encoder YUV 422 encoding only up to VGA image size scalable quantization table standard quantization table standard Huffman coder
The encoder top level block diagram is presented in Figure3.
The input data is a YUV 422 8-bit data stream in raster order. The output data is a baseline JPEG
data stream.
Figure 3: Encoder top level block diagram
STV0974 Functional description
4.4.1 Raster to block converterThis block transforms the raster scan ordered data into block based ordered data. This data
ordering is compliant with ISO DIS 10918-1 Annex A - Section A.2.
The sequence of the input data stream is the following: line 1 from left to right up to pixel n, then line
2 from left to right......up to line m, pixel n.
The output data stream sequence is block based. The image is segmented into MCU (minimum
coded units) as illustrated in Figure5.
Figure 4: Data sequence at Raster to block input
Figure 5: MCU data order
Functional description STV0974The MCU sequence order is top left to top right and top to bottom.
Figure 6 shows the MCU structure made of 4 blocks: 2 blocks of 8x8 Y component, 1 block of 8x8 U
component and one block of 8x8 V component. The series of blocks must be processed according
to this order.
Each block is composed of 8x8 components. Figure 7 presents the structure of BlockY1, as an
example.
The data sequence inside each block is left to right and top to bottom.
To summarize, at the output of Raster to Block converter, the data order is the following:
Y data of blockY1 of first MCU (64 data from left to right, then top to bottom)
Y data of blockY2 of first MCU (64 data from left to right, then top to bottom)
U data of blockU of first MCU (64 data from left to right, then top to bottom)
V data of blockV of first MCU (64 data from left to right, then top to bottom)
Y data of blockY1 of second MCU (64 data from left to right, then top to bottom)
Y data of blockY2 of second MCU (64 data from left to right, then top to bottom)
U data of blockU of second MCU (64 data from left to right, then top to bottom)
V data of blockV of second MCU (64 data from left to right, then top to bottom)
... up to last image MCU.
Figure 6: Structure of each MCU
Figure 7: Structure of block Y1
STV0974 Functional description
4.4.2 Discrete Cosine TransformThis block performs a Discrete Cosine Transform on the incoming data stream. It is compliant with
ISO DIS 10918-1 Annex A - Section A.3.
The block processes each 8x8 input block to transform them into 8x8 DCT coefficients. The
calculation of the DCT coefficients is done by the formula:
4.4.3 Zigzag transformThis block is in charge of setting the DCT coefficients in a sequence that corresponds to an
increasing spacial frequency of the cosine function. It is compliant with ISO DIS 10918-1 Annex A -
Section A.3.6.
with
Figure 8: ZigZag block sequence re-orderingv,() 2---- Cu ()Cv()0=0=× fxy,() 2x1+ ()uπ---------------------------- 2y1+ ()vπ----------------------------coscos=() Cv(), 1-----= uv,()∀ 0=() Cv() ,1= uv,()∀ 0¼
Functional description STV0974
4.4.4 Quantization blockThis block applies a uniform quantizer on all DCT coefficients, in ZigZag sequence. It is compliant
with ISO DIS 10918-1 Annex A - Section A.3.4.
The quantizer step size for each DCT coefficient Suv is the value of the corresponding element Q’uv from the quantization table Q’.
Where uv is the index of the zigzag coefficient.
Table Q’ is a scaled quantization table calculated for table Q as follows:
where Squeeze is a parameter value.
Table Q is represented in Figure 9, as described in ISO DIS 10918-1 Annex K.
Table 6 shows an example of VGA image when different squeeze values are applied by the user.
Figure 9: Luminance and chrominance quantization tables
Table 6: VGA image size - YUV 4: 2: 2 - Example of image size after JPEG compression No compression
Squv round Suv
Q'uv------------⎝⎠⎛⎞= Squeeze-------------------------Q×=
STV0974 Functional description
4.4.5 Entropy coderThis block performs the following functions: insertion of JPEG Markers runlength encoding Huffman encoding
4.4.5.1 JPEG markersThese markers are compliant with ISO DIS 10918-1 Annex B.
The output JPEG file includes markers defined in Table 7, in order of appearance.
4.4.5.2 Runlength and Huffman encoding
Encoding of DC coefficientThe so-called DC coefficient is the first coefficient of each DCT data block. This DC coefficient is
coded through its DPCM difference with its previous value, which is huffman encoded. This is
described in ISO DIS 10918-1 Annex A - Section F .1.2.1. The DC Huffman tables are described in
ISO DIS 10918-1 Annex A - Section K.3.
In the example from Figure 10, the DC coefficient in Block Y2 is equal to 4, the previous Luminance
DC coefficient is 12 (DC coefficient of Block Y1). The DPCM value is 4-12 = -8 and the encoded
value will be Huffman (-8). The code that is generated is Code = DC Huffman (-8).
Encoding of AC coefficientsThe 63 left coefficients of each DCT block are called AC coefficients. They are encoded using run-
length and Huffman encoder. The run-length encoding consists in counting the number of zero
values between each non-zero coefficient. When a non zero coefficient is found, the Huffman code
of the pair (number of preceding zero, Number value) is Huffman encoded. If a run contains more
than 15 zeros, a specific number called ZRL is Huffman encoded.
If all the values up to the end of the block are equal to zero, a specific code called EOB is Huffman
encoded.
Table 7: JPEG markers included in STV0974 output data stream
Figure 10: Encoding of DC coefficient
Functional description STV0974The Huffman table used are described in ISO DIS 10918-1 Annex A - Section K.3.
In the above example, the first AC coefficient of Block Y1 is 0, as good as the second one. The
zeros are not Huffman encoded, but the runlength counts them. When the first non-zero value is
reached (Coefficient 4 with value 77), the Huffman code for the pair (number of preceding zeros,
value) = (2,77) if Huffman encoded.
The code that is generated is Code = Huffman (2,77).
Figure 11: Encoding of AC coefficient
STV0974 Functional description
4.5 Microprocessor interface
4.5.1 Features 8-bit microprocessor interface, asynchronous read/write, one address bit Indirect access to image sensor and coprocessor control registers Direct access to image data (JPEG compressed or uncompressed) On-chip 2048 byte image FIFO Interrupt request output 8/16/32-byte burst DMA support 2 Kbyte video FIFO for JPEG data and 10 Kbyte FIFO for non-JPEG data
4.5.2 DescriptionThe STV0974 can be connected to any general purpose 8-bit microprocessor via the
microprocessor interface. This interface substitutes functionally to the YUV and I²C interfaces, i.e.
both data and control flows are handled through the interface which provides: access to the image data FIFO for fast transfers of scaled-down viewfinder images or full-
resolution captured and compressed image data. For host systems with DMA support, a DMA
request line is provided, as well as programmable FIFO threshold for burst operation. For other
systems, an interrupt request output line is provided.The 2048-byte FIFO allows for greater
host system latencies; to suit system requirements, the FIFO threshold is programmable. access to the camera subsystem configuration and control registers, through an address/data
register pair and a status register for data polling. Access requests are posted to the internal
controller core that handles the request (as in I²C mode) and finally acknowledges through the
microprocessor interface status register.
Functional description STV0974
4.5.3 Direct registersAccess to the microprocessor interface direct registers is controlled by the state of CSN, RDN,
WRN and RS (Table8).
The direct registers are used to access all STV0974 indirect registers and external image sensor
registers through I²C. To read from a camera register: Write AR with the indirect register address. Poll the status register RDY bit until high. Read the register data from DR.
To write to a camera register: Write AR with the indirect register address. Write DW with the register data. Poll the status register RDY bit until high.
Note:1 16-bit values are in little-endian representation, i.e. LSB at lower address. No data polling is required to access the microprocessor interface indirect registers.
Address Register (AR)The Address Register holds the 16-bit address of the camera register to access. AR is written by
two consecutive byte writes, least significant byte first.
Note: To avoid LSB/MSB sequence mismatch, any read access (to DR or SR) guarantees that the
following write to AR updates the LSB (ADDR bits 7:0).
Table 8: Microprocessor Interface Direct Registers
Table 9: Address Register
STV0974 Functional description
Status Register (SR)The status register is an 8-bit read-only direct register holding all pending requests from the camera
subsystem.
Table 10: Status Register
Functional description STV0974
Data Write Register (DW)The data write register contains the byte to transfer to a camera register. DW can be written only
when SR bit RDY is set.
Data Read Register (DR)The Data Read Register contains the byte transferred from a camera register. DR is valid only
when SR bit RDY is set.
4.5.4 Indirect registersThe microprocessor interface indirect registers are accessed by the host using an indirect address
base of 0x8FF0 / 0xCFF0 (write / read). Register offsets are listed in Table13:
Table 11: Data write register
Table 12: Data Read register
Table 13: Microprocessor interface indirect register map a b 16-bit values are in little-endian representation, i.e. LSB at lower address. No data polling is required to access the microprocessor interface indirect registers.
STV0974 Functional description
FIFO Register (FIFO)FIFO is a read-only register. When read, FIFO returns the least recent byte from the image data
FIFO, decrements the byte count and releases the FIFO interrupt if the count is lower than the
threshold. Reading from an empty FIFO returns the last valid byte read.
The image data FIFO is cleared at the beginning of VENV, the image vertical envelope. If the FIFO
is not empty, its contents are discarded and the FERR flag is raised in the status register SR. New
image data start to fill in the FIFO. If an overflow occurs during VENV, the FERR flag is also raised
in SR; FERR can be cleared through ICLR.
Microprocessor Interface Control Register (MICR)MICR controls and configures the image data transfer.
Table 14: FIFO register
Table 15: Microprocessor Interface Control Register
Functional description STV0974
Interrupt Mask Register (IMASK)
Interrupt Clear Register (ICLR)
FIFO Threshold Register (FTHR)This register is used to program values such as 1 (flush), 16 or 32 (DMA burst) or any greater value
up to 2032 for interrupt driven data transfer. Note that for proper DMA operation, ‘threshold’ must be
greater than or equal to the DMA burst size (MICR[BSIZE]).
Table 16: Interrupt Mask Register
Table 17: Interrupt Clear Register
Table 18: FIFO threshold register
Table 19: FIFO Threshold Register
STV0974 Functional description
FIFO Count Register (FCNT)FCNT is a read-only 16-bit register, returning the current number of bytes available in the FIFO.
4.5.5 Image transfer operation
Interrupt controlled transferThe STV0974 generates interrupts by asserting the IRQ signal. The host interrupt handler performs
the following operations: Read the status register SR to determine if the STV0974 is the interrupting device (IRQ bit) and
detect the active interrupt sources. Acknowledge pending interrupts by writing ICLR. Service the interrupt source(s), i.e. for example:
MCI: read micro-core status and error registers (camera control channel).
SOF: trigger frame synchronous task.
FF: empty the FIFO by reading 16-byte blocks (camera image data channel).
RDY: read DR for a pending read, write next AR (low-level byte transfer). Interrupts can be disabled through IMASK.
DMA controlled transferThe STV0974 supports DMA operation for image data transfer: the DRQ output signal is used to
trigger a DMA burst read transfer from peripheral to memory. A full image transfer under DMA
executes as follows: The STV0974 is initialized: DMA burst size, FIFO is cleared. DRQ is asserted when the image FIFO threshold is reached or exceeded. The DMA controller starts performing the burst read transfer consisting of 8, 16 or 32 byte reads.
Table 20: FIFO Count Register
Figure 12: Full image transfer under DMA
Functional description STV0974 DRQ is released after the first byte is read. After the last byte of the burst is read, the transfer terminates on step 6 if the FIFO is empty and
the frame end is reached. Otherwise, transfer continues on step 2. IRQ is asserted to signal the end of image transfer; the DMA channel is closed and re-initialized
for the next transfer.
This behavior ensures that no request can be missed by the controller, assuming DRQ is an edge-
sensitive signal. DRQ polarity can be reversed through MICR[POL] bit.
Note:1 During DMA transfer, it is assumed that reading DR returns a byte from the FIFO, which means that
AR shall be pointing to the FIFO when the DMA channel is active. To access other registers while
performing DMA, the DMA controller must be halted and pending transfers properly flushed; then
indirect accesses to the camera subsystem can occur. Finally, AR must be restored and the DMA
controller released. At the end of the transfer, FIFO underrun can occur if the image size is not an integer multiple of the
burst size: dummy bytes are appended at the end of the image buffer. Nevertheless, the JPEG end-
of-frame marker (0xffd9) delineates the buffer.
STV0974 Functional description
4.6 Video output interface
4.6.1 Video synchronizationThe STV0974 supports two modes of data stream synchronization. Either the data stream can be
synchronized by separate HSYNC and VSYNC signal (see Section 4.6.3) or by Synchronization
codes in the data stream (see Section 4.6.2).
4.6.2 Synchronization codes
Horizontal synchronization The horizontal synchronization signal can be embedded within the data. Figure 13 represents the synchronization codes generated in a line.
Vertical synchronizationNote: The horizontal synchronization is not sent during vertical blanking.
Figure 13: Embedded code horizontal timing
Figure 14: Embedded codes in vertical timing
Functional description STV0974
4.6.3 HSYNC and VSYNC video synchronizationHSYNC and VSYNC synchronization timing is shown in the Figure15.
4.6.4 Data timingThe YUV timing and the 3 RGB timings are also represented on Figure 16, with the associated
qualifying HCLK clock.
Figure 15: Horizontal and vertical synchronization
Figure 16: Timings with associated qualifying clocks
STV0974 Functional description
4.6.5 JPEG data on 8-bit parallel with qualification clockThis interface outputs JPEG on parallel 8-bit IOs. Different synchronization can be provided, as
described in Figure17.
There are no defined lines in a JPEG data stream. The whole stream is output as a single frame
line with VSYNC and HSYNC asserted together.
Polarities of HSYNC, VSYNC and HCLK are programmable.
Extra bytes can be added at the end of the image to ease the host DMA task.
Figure 17: JPEG data output
Functional description STV0974
4.7 Power management unitThe STV0974 is reset via the internal PowerOnReset cell (POR) or via an external control reset
line. The device reset is controlled by the RST pin.
The POR cell generates an output signal on the POR pin every time that the device external supply
is switched off or the PDN pin is activated.
The STV0974 enters into power-up phase in two circumstances: when the supplies are turned on with PDN pin high. when the STV0974 exits from power-down (PDN pin rises with supplies already on).
At power-up, the STV0974 performs its initialization phase and goes into sleep mode.
Figure 18: Reset of STV0974
Figure 19: State machine at power-up
STV0974 Functional descriptionTiming constraints:
Note: To be compatible with external power-on/internal power-down modes (ex: external VDD on and
PDN low), all input pads from baseband side as well as SCL and SDA pads on both sensor and
baseband sides are “fail-safe”.
The “timing constraints” mentioned above correspond to the minimum delay needed between
signals, in order to follow a correct power up sequence and insure an adequate initialization phase.
Referring to the application schematics (Section 8), STMicroelectronics recommends to connect
POR pin (internal supply) to RST pin (Reset).
Figure 20: Boot-up phase machine
Table 21: Timing constraints
Functional description STV0974
4.8 Clock inputThis block generates all the necessary internal clocks from an input range defined in Table 22. The
input clock pad accepts up to 26 MHz signals.
Table 22: System input clock frequency range Standard supported input frequencies (in MHz):
6.5, 8.4, 9, 9.6, 9.72, 12,13, 16.8, 18, 19.2, 19.44, 26
STV0974 Functional description
4.9 Camera control unit
4.9.1 Features User mode transitionI2 C register map including high-level registers and low-level registers dedicated to scaler
control
4.9.2 Descriptioni. the “1” transition is automatic
ii. Flash mode requires a firmware patch. Contact ST support.
iii. Flash mode is not available with the microprocessor interface
Modes
Power down ●Supply is internally cut.
Reset. Transitional state
Boot ●
Sleep mode This mode ensures that the coprocessor consumes the lowest possible power and I2C
control is possible. Patching should occur in sleep mode followed by setting the system clock
parameters.
Idle Mode The clock coming from the sensor is active and I2 C control is possible.
Viewfinder Mode The viewfinder mode can be used to display dithered images on low color depth local LCD displays. The programmable gamma allows for a wide range of displays. Different image
sizes and data formats can be chosen.
Figure 21: State machine user mode transitions
Functional description STV0974
Still Mode This mode is used to take still pictures. Still picture parameters can be set for both image size and data format. the first image output has a guaranteed exposure and color balance.
the number of frames output can also be set.
Live Mode Live clips can be generated in all the data and image formats.
Flash Mode Flash mode is used to take a single still picture and synchronously activate a flash gun signal and illuminate the scene during the exposure period of the pixels.
Torch Mode For systems without a flash gun, a torch mode can replace the flash mode. Torch mode is a setting (rather than a mode) which supports illumination of devices by producing a longer
illumination pulse with a lower intensity. In torch mode, illumination is switched on before the
camera is operated in one of the standard operating modes: ViewFinder, still capture or live.
Mode transitions
Boot to sleep The microcore starts following PDN de-activation. The right configuration is obtained according to the following procedure: Determine the sensor I2 C chip address. Read all sensor registers, either through I2 C reads or status line interpretation. Initialize internal registers.
The device then automatically goes into sleep mode
Sleep to idle When exiting sleep mode, the external clock register of the sensor is set, and the sensor goes into Idle mode.
Figure 22: Sleep to idle timing
