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STV0502STN/a800avaiCCD SENSORS ANALOG PROCESSOR IC


STV0502 ,CCD SENSORS ANALOG PROCESSOR ICSTV0502CCD SENSORS ANALOG PROCESSOR IC.SERIAL BUS CONTROLVIDEO.CORRELATED DOUBLE SAMPLING OF THECCD ..
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STV0502
CCD SENSORS ANALOG PROCESSOR IC
STV0502
CCD SENSORS ANALOG PROCESSOR IC
October 1998 SERIAL BUS CONTROL
VIDEO
. CORRELATED DOUBLE SAMPLING OF THE
CCD SIGNAL. DIGITALLY CONTROLLED VARIABLE AMPLI-
FIER AND BLACK CLAMP LEVEL. 8 BITS PIXEL RATE ADC
AUDIO
. MICROPHONE PREAMP WITH SWITCHABLE
AGC (RANGE 34dB - 60dB) OR FIXED GAIN
DESCRIPTION

The chip integrates the analog functions needed in
a CCD Video Camera, more particularly for video-
conferencing purpose.
The CCD signal is sampled, amplified to a useful
level and digitized by an 8 bits ADC. The gain of the
amplifier and the black level clamp can be adjusted
by a serial bus.
The audio microphone preamplifier allows a micro-
phone to be connected to the chip, which outputs
a differential audio line level signal ready for digital
conversion or straight amplification. The preampli-
fier incorporates an AGC to adapt to the income
signal level. The AGC is switchable ON/OFF by the
serial interface.
PIN CONNECTIONS

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PINOUT DESCRIPTION
STV0502

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BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
1 - Video Section
CCD signal is provided to the STV0502, via a
coupling capacitor, as well as the pulses FS/FCDS.
The CDS (Correlated Double Sampling) is perform-
ing a clamp of the CCD signal during the FCDS
pulse. The signal obtained is then sampled during
the FS pulse, and held the rest of the period. The
resulting signal is then the difference between the
useful pixel level, and the pixel level corresponding
to no charge which can vary from one pixel to
another. Therefore, the parasitic level offset from
one pixel to another is removed.
This signal is DC coupled to the ACG, amplified by
a variable gain amplifier, bus controlled
(0.07dB step), which gain is in the range +6dB to
+23.7dB (17.7dB range). Typically, the amplifier is
controlled in order to keep the signal at an optimum
level (AGC) to be digitized. An extra 12dB can be
added up via a bit of the serial interface. In this case
the gain range becomes +18dB up to + 36dB.
At this point, the signal is clamped to a Black level
during the OB pulse. The black level is 5 bits bus
controlled, and its range corresponds to
[0 LSB ; 31 LSB] of the ADC. The black level is
made with a 5 bits DC frequency DAC, using the
same VBOTTOM and VTOP voltage references than
the ADC for matching purposes. The clamp is made
out of a OB pulse sampled comparator between the
DAC output voltage (Black) and the ADC input
signal. The comparator has a symetrical current
output charging a capacitor. The obtained voltage
is buffered and used as a feedback to the AGC
input stage. This clamp makes sure that ADCin is
matched to the DAC black setting during the OB
pulse, disregarding any offset in the AGC path.
Then the signal is digitized by a fast ADC, clocked
at the pixel rate. The output of the chip is then an
8-bit pixel DATA, ready for digital post-processing.
2 - Audio Section

The chip integrates a high gain audio amplifier, in
order to process low signals coming from a speech
microphone, and provide on its output a line level,
differential audio signal, for digital conversion, or
power amplification. Two modes can be selected :
fixed gain mode or AGC mode. In case of AGC
mode, a peak detection of the signal is performed
in order to regulate the output signal on a defined
level of 1.5VPP or 1VPP (non-diff). This regulated
level can be chosen at 1.5VPP or 1VPP thanks to a
pin at respectively ground or supply voltage (a pull-
up resistor to supply is already included on chip),
for compatibility purposes between the 502 and
various back-end chips.
The system includes a Low-Noise fixed amplifier
(26dB), and a bias circuitry at the front.
STV0502

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Figure 1
FUNCTIONAL DESCRIPTION (continued)

It is followed by a Voltage Controlled Amplifier
(range 8dB - 34dB), that can be switched into a
fixed 26dB gain amplifier.
The VCA output is differential and 2 buffers are
driving the two output pins, with a load impedance
down to 5kΩ.
A bias circuitry and an external capacitor (ACC)
form a DC feedback loop on the VCA DC bias, in
order to correct any DC offset on the VCA output.
Finally, a peak detector (double alternance) is used
to compare the output signal with the reference
threshold, to be regulated at. An external capacitor
(CAGC) is used for the AGC time constants. If the
signal goes above the threshold, a 500μA current
is charging the capacitor with a fast reponse
time(attack). In case of very big signals, a second
charge cureent of about 5mA is given, in order to
reduce the period during which the output signal is
saturated. Otherwise, a constant 1μA current dis-
charges the capacitor with a slow response time
(decay). The capacitor voltage controls the VCA
gain. This constitues the AGC loop.
Figure 2
STV0502

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FUNCTIONAL DESCRIPTION (continued)
3 - Serial Bus Specification

It is a 2-wires (data and clock) serial bus, used as
a slave.
Clock line is monodirectional (input) and allways
sent by the master to the chip, whereas Data line
is bidirectional (I/O).
There are 3 registers (8 bits), both writable/readable.
Each register can be addressed by a 4 bits address
word, followed by a R/W bit, and an 8 bits word Data
(read/write).
2 main patterns can be sent : Reset Pattern and
Read/Write pattern.
3.1 -Timings and Protocol

The data bit is taken into account when the clock
is rising. Reset Pattern : resets all the registers to their
default (Power On) values :
format = 16 * (data=1) | 2 * (data=0)
(total = 18 clocks) Read/Write Pattern :
format = 4 addr bits | R/W bit | 8 data bits
(total = 13 clocks)
Please note that : On power On conditions, SDATA line is in Write
(Input) Mode. In case of a read pattern, the SDATA line is
automatically set to Read (Output mode) during
8 clock cycles (Data D7 - D0) after R/W bit has
been sent, and comes back in Write (Input
mode) after the 13th clock cycle. There is no timing restriction between two
consecutive patterns (a pattern being defined
as one of the two above).
3.2 - Register Summary
: unused bits: means useful bits
Please note that 3 different functions are merged
in register address 01.
Figure 3
Figure 4
STV0502

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FUNCTIONAL DESCRIPTION (continued)
3.3 - Control Data
Video Amplifier Gain Control (8 bits used)

Address : 0000
POR value: 0000.0000 ---> 6dB
Gain is expressed from CDSoutput to ADC input
(ADC range 1.55VPP) 0.07dB / LSB step Overall range (256 steps) : 17.7dB
Black Level Adjustment Control (5 bits used)

Address : 0001
POR Value: 0001.0000 ---> 16LSB
The adjustment is controlling the black reference
voltage. However, it is preferred to express the
Black level adjustment in terms of the ADC output
code variation (in ADC LSBs, compared to the
nominal default setting) depending on the Black
setting.
Typically, 16 LSBs black level is recommended. 1 ADC LSBs / LSB step Overall range : 31 ADC LSBs
Video High Gain Select (1 bit used)

Address : 0001
POR Value: 0 ---> Nominal gain
This bit controls an extra 12dB gain in the video
path (adding to gain described in previous page).
Video AGCOUT Test Signal ON/OFF (2 bits used)

Address : 0001
POR Value: 00 ---> High Z pad
A pin is reserved to output the ADC input signal, or
input the ADC input signal for test and evaluation
purpose.
Those bits control the state of the output buffer. To
limit Xtalk and pollutions, the buffer is in High
impedance mode during normal operation.
Microphone AGC Switch (1 bit used)

Address : 0010
POR value: 0000.0000 ---> AGC OFF
The switch is controlling the state of the AGC : ON
or OFF.
In OFF mode, the Micro Preamp. is set at a fixed
nominal gain of 52dB.
In ON mode, the AGC is operating in a gain range
[34dB ; 60dB] (see further in this document for
details).
STV0502

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THERMAL DATA
ELECTRICAL CHARACTERISTICS

Tamb = 25o C, VDD = VCC = 5V, unless otherwise specified
SUPPLY
CMOS DIGITAL INPUTS
SERIAL INTERFACE
Figure 5
ABSOLUTE MAXIMUM RATINGS
ESD : The STV0502 withstands 2kV in Human Body Model and 100V in Machine Model for all Pins versus

VDD and VSS.
STV0502

7/15
ELECTRICAL CHARACTERISTICS
Tamb = 25o C, VDD = VCC = 5V, unless otherwise specified (continued)
VIDEO CDS
VIDEO AMPLIFIER
Notes :
1. Normal operation means FS & FCDS run at specified timings and 12MHz frequency. On a 20Hz to 10MHz frequency range, with 10μF filtering capacitors on all supplies, and well splitted supplies and grounds.
STV0502

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