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STS3DPF60LSTN/a95avaiDUAL P-CHANNEL 60V


STS3DPF60L ,DUAL P-CHANNEL 60VAbsolute Maximum ratingsSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 60 VDS GSV Drain- ..
STS3DPFS30L ,P-CHANNEL 30VELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STS3DPFS45 ,P-CHANNEL 45VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
STS4DNF30L ,DUAL N-CHANNEL 30V ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STS4DNF-30L ,DUAL N-CHANNEL 30V ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 30 VDS GSV Drain-g ..
STS4DNF60L ,N-CHANNEL 60VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
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STS3DPF60L
DUAL P-CHANNEL 60V
1/9September 2004
STS3DPF60L

DUAL P-CHANNEL 60V - 0.10 Ω - 3A SO-8
STripFET™ MOSFET
Rev. 1
STS3DPF60L
2/9
Table 3: Absolute Maximum ratings

(•) Pulse width limited by safe operating area.
Table 4: Thermal Data

(*) When Mounted on 1 inch2 FR-4 board, 2 oz of Cu t ≤ 10 s
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 5: On/Off
3/9
STS3DPF60L
ELECTRICAL CHARACTERISTICS (CONTINUED)
Table 6: Dynamic
Table 7: Source Drain Diode

(*) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(•)Pulse width limited by safe operating area.
STS3DPF60L
4/9
Figure 3: Safe Operating Area
Figure 4: Output Characteristics
Figure 5: Transconductance
Figure 6: Thermal Impedance
Figure 7: Transfer Characteristics
Figure 8: Static Drain-source On Resistance
5/9
STS3DPF60L
Figure 9: Gate Charge vs Gate-source Voltage
age vs Temperature
Figure 11: Dource-Drain Diode Forward Char-
acteristics
Figure 12: Capacitance Variations
Figure 13: Normalized On Resistance vs Tem-
perature
Figure 14: Normalized Breakdown Voltage vs
Temperature
STS3DPF60L
6/9
Figure 15: Unclamped Inductive Load Test Cir-
cuit
Figure 17: Test Circuit For Inductive Load
Switching and Diode Recovery Times
Figure 18: Unclamped Inductive Wafeform

Figure 19: Gate Charge Test Circuit

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