STPCC0166BTC3 ,PC Compatible Embeded MicroprocessorFeatures include smooth scaling andVideoColorpipeline KeyMonitorcolor space conversion of the video ..
STPCC0180BTC3 ,STPC CONSUMER DATASHEET / PC COMPATIBLE EMBEDED MICROPROCESSORFeatures include smooth scaling andVideoColorcolor space conversion of the video input streampipeli ..
STPCC0390BTC3 ,PC Compatible Embeded Microprocessor
STPCC4HEBC ,X86 Core PC Compatible Information Appliance System-on-ChipLogic Diagram- NTSC / PAL COMPOSITE, RGB, S-VIDEO■ PCI MASTER / SLAVE / ARBITERHost x86■ ISA MASTER ..
STPCD0166BTC3 ,PC Compatible Embedded Microprocessor
STPCD0166BTC3 ,PC Compatible Embedded Microprocessor
T1001NL , TELECOMMUNICATIONS PRODUCTS
T1005 , TELECOMMUNICATIONS PRODUCTS
T1006NL , TELECOMMUNICATIONS PRODUCTS
T1007 , TELECOMMUNICATIONS PRODUCTS
T1007NL , TELECOMMUNICATIONS PRODUCTS
T1008NL , TELECOMMUNICATIONS PRODUCTS
STPCC0166BTC3
PC Compatible Embeded Microprocessor
STPC CONSUMER Compatible Embeded Microprocessor1/518/2/00
Figure1. Logic Diagram POWERFUL X86 PROCESSOR 64-BIT BUS ARCHITECTURE 64-BIT DRAM CONTROLLER SVGA GRAPHICS CONTROLLER UMA ARCHITECTURE VIDEO SCALER DIGITAL PAL/NTSC ENCODER VIDEO INPUT PORT CRTCONTROLLER 135MHz RAMDAC 3 LINE FLICKER FILTER SCAN CONVERTER PCI MASTER/ SLAVE/ ARBITER CTRL ISA MASTER/SLAVE INTERFACE IDE CONTROLLER DMA CONTROLLER INTERRUPT CONTROLLER TIMER/ COUNTERS POWER MANAGEMENT
STPC CONSUMER OVERVIEWThe STPC Consumer integratesa standard 5th
generation x86 core,a DRAM controller,a graph-
ics subsystem,a video pipeline and support logic
including PCI, ISA and IDE controllersto providea
single Consumer orientated PC compatible sub-
system ona single device.
The deviceis based ona tightly coupled Unified
Memory Architecture (UMA), sharing the same
memory array between the CPU main memory
and the graphics and video frame buffers.
Extra facilities are implementedto handle video
streams. Features include smooth scaling and
color space conversionof the video input stream
and mixing with graphics data. The chip also in-
cludesa built-in digital TV encoder and anti-flicker
filters that allow stable, high-quality display on
standard PALor NTSC television sets without ad-
ditional components.
The STPC Consumeris packagedina 388 Plastic
Ball Grid Array (PBGA).
PBGA388
x86
Core
HostI/F
DRAM
CTRL
VIP
PCI
m/s
PCIBUSISA
m/s
EIDEPCI
m/s
ISABUSCRTC HWCursor
Monitor
TVOutput
SYNCOutputColorSpace
Converter
Color
Key
Chroma
Key
Video
pipeline
CCIRInput
EIDESVGA
AntiFlicker
IPC
Digital
PAL/
NTSC
STPC CONSUMER2/51
X86 Processor core Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible. Can accessupto 4GBytesof external
memory. 8KByte unified instruction and data cache
with write back and write through capability. Parallel processing integral floating point unit,
with automatic power down. Clock core speedsuptoof 100 MHz. Fully static designfor dynamic clock control. Low power and system management modes. Optimized designfor 3.3V operation.
DRAM Controller Integrated system memory andgraphic frame
memory. Supports upto 128 MBytes system memory4 banks and downtoas littleas 2Mbytes. Supports 4MB, 8MB, 16MB, 32MB single-
sided and double-sided DRAM SIMMs. Four quad-word write buffersfor CPUto
DRAM and PCIto DRAM cycles. Four 4-word read buffersfor PCI masters. Supports Fast Page Mode& EDO DRAM. Programmable timingfor DRAM parameters
including CAS pulse width, CAS pre-charge
time and RASto CAS delay. 60, 70,80& 100ns DRAM speeds. Memory hole between1 MByte&8 MByte
supported for PCI/ISA busses. Hidden refresh. checkif your memory deviceis supported by
the STPC, please refer to Table 9-3 in the
Programming Manual.
Graphics Engine 64-bit windows accelerator. Backward compatibilityto SVGA standards. Hardware acceleration for text, bitblts,
transparent blts and fills. Upto64x64bit graphics hardware cursor. Upto 4MB long linear frame buffer. 8-, 16-, and 24-bit pixels. Driversfor Windows and other operating
systems.
VGA Controller Integrated 135MHz triple RAMDAC allowing
for 1280x 1024x 75Hz display. Requires external frequency synthesizer and
reference sources. 8-, 16-, 24-bit pixels. Interlacedor non-interlaced output.
Video Input port Accepts video inputsin CCIR 601/656or
ITU-R 601/656, and stream decoding. Optional 2:1 decimator Stores captured videoinoff setting areaof
the onboard frame buffer. Video pass throughto the onboard PAL/
NTSC encoder for full screen video images. HSYNC and B/T generationor lock onto
external video timing source.
Video Pipeline Two-tap interpolative horizontal filter. Two-tap interpolative vertical filter. Color space conversion (RGBto YUV and
YUVto RGB). Programmable window size. Chroma and color keyingfor integrated video
overlay. Programmable two tap filter with gamma
correctionor three tap flicker filter. Progressiveto interlaced scan converter.
Digital NTSC/PAL encoder NTSC-M, PAL-M,P AL-B,D,G,H,I,PAL-N easy
programmable video outputs. CCIR601 encoding with programmable color
subcarrier frequencies. Line skip/insert capability Interlacedor non-interlaced operation mode. 625 lines/50Hzor 525 lines/60Hz8bit
multiplexed CB-Y -CR digital input. CVBS and R,G,B simultaneous analog
outputs through 10-bit DACs. Cross color reductionby specific trap filtering luma within CVBS flow. Power down mode available on each DAC.
STPC CONSUMER3/51
PCI Controller Fully compliant with PCI 2.1 specification. Integrated PCI arbitration interface. Upto3
masters can connect directly. External PAL
allows for greater than3 masters. Translationof PCI cyclesto ISA bus. Translationof ISA master initiated cycleto
PCI. Support for burst read/write from PCI master. 0.33X and 0.5X CPU clock PCI clock.
ISA master/slave Interface Generates the ISA clock from either
14.318MHz oscillator clockor PCI clock Supports programmable extra wait statefor
ISA cycles Supports I/O recovery timefor backto back
I/O cycles. Fast Gate A20 and Fast reset. Supports the single ROM thatC,D,orE.
blocks shares withF block BIOS ROM. Supports flash ROM. Supports ISA hidden refresh. Buffered DMA& ISA master cyclesto reduce
bandwidth utilizationof the PCI and Host bus.
NSP compliant.
IDE Interface Supports PIO Supportsupto Mode5 Timings Transfer Ratesto22 MBytes/sec Supports upto4 IDE devices Concurrent channel operation (PIO modes)-x 32-Bit Buffer FIFOs per channel Support for PIO mode3&4. Support for 11.1/16.6 MB/s, I/O Channel
Ready PIO data transfers. Individual drive timingforall four IDE devices Supports both legacy& native IDE modes Supports hard drives larger than 528MB Support for CD-ROM and tape peripherals Backward compatibility with IDE (ATA-1). Driversfor Windows and other Operating
Systems
Integrated peripheral controller 2X8237/AT compatible 7-channel DMA
controller. 2X8259/AT compatible interrupt Controller. interrupt inputs- ISA and PCI. Three 8254 compatible Timer/Counters. Co-processor error support logic.
Power Management Four power saving modes: On, Doze,
Standby, Suspend. Programmable system activity detector Supports SMM and APM. Supports STOPCLK. SupportsIO trap& restart. Independent peripheral time-out timerto
monitor hard disk, serial& parallel ports. Supports RTC, interrupts and DMAs wake-up
STPC CONSUMER4/51
UPDATE HISTORY FOR OVERVIEW.5/51
0.1 UPDATE HISTORY FOR OVERVIEW.The following changes have been madeto the Electrical Specification Chapteron the 02/02/2000.
Section Change Text
Added To checkif your memory deviceis supported by the STPC, please referto
Table 9-3 Host Addressto MA Bus Mappingin the Programming Manual.
GENERAL DESCRIPTION6/51
GENERAL DESCRIPTION the heartof the STPC Consumeris an ad-
vanced processor block, dubbed the 5ST86. The
5ST86 includesa powerful x86 processor core
along witha 64-bit DRAM controller, advanced
64bit accelerated graphics and video controller,a
high speed PCI local-bus controller and Industry
standard PC chip set functions (Interrupt control-
ler, DMA Controller, Interval timer and ISA bus)
and EIDE controller.
The STPC Consumer has in addition to the
5ST86,a Video subsystem and high quality digital
Television output.
The STMicroelectronics x86 processor coreis em-
bedded with standard and application specific pe-
ripheral moduleson the same silicon die. The core
hasall the functionalityof the STMicroelectronics
standard x86 processor products, including the
low power System Management Mode (SMM).
System Management Mode (SMM) provides an
additional interrupt and address space that canbe
used for system power managementor software
transparent emulationof peripherals. While run-
ningin isolated SMM address space, the SMMin-
terrupt routine can execute without interfering with
the operating systemor application programs.
Further power management facilities includea
suspend mode that can be initiated from either
hardwareor software. Becauseof the static nature the core,no internal datais lost.
The STPC Consumer makes useofa tightly cou-
pled Unified Memory Architecture (UMA), where
the same memory arrayis used for CPU main
memory and graphics frame-buffer. This signifi-
cantly reduces total system memory with system
performances equalto thatofa comparable solu-
tion with separate frame buffer and system mem-
ory.In addition, memory bandwidthis improvedby
attaching the graphics engine directlyto the 64-bit
processor host interface runningat the speedof
the processor bus rather than the traditional PCI
bus.
The 64-bit wide memory array provides the sys-
tem with 320MB/s peak bandwidth, double thatof equivalent system using32 bits. This allows for
higher screen resolutions and greater color depth.
The processor bus runsat the speedof the proc-
essor (DX devices)or half the speed (DX2 devic-
es).
The ‘standard’ PC chipset functions (DMA, inter-
rupt controller, timers, power management logic)
are integrated with the x86 processor core.
The PCI busis the main data communication link the STPC Consumer chip. The STPC Consum- translates appropriate host bus I/O and Memory
cycles onto the PCI bus.It also supports the gen-
erationof Configuration cycles on the PCI bus.
The STPC Consumer,asa PCI bus agent (host
bridge class), fully complies with PCI specification
2.1. The chip-set also implements the PCI manda-
tory header registersin Type0 PCI configuration
space for easy portingof PCI aware system BI-
OS. The device containsa PCI arbitration function
for three external PCI devices.
The STPC Consumer integrates an ISA bus con-
troller. Peripheral modules such as parallel and
serial communications ports, keyboard controllers
and additional ISA devices can be accessed by
the STPC Consumer chip set through this bus. industry standard EIDE (ATA2) controlleris
builtinto the STPC Consumer and connectedin-
ternally via the PCI bus.
Graphics functions are controlledby the on-chip
SVGA controller and the monitor displayis man-
agedby the 2D graphics display engine.
This Graphics Engineis tunedto work with the
host CPUto providea balanced graphics system
witha low silicon area cost.It performs limited
graphics drawing operations, which include hard-
ware accelerationof text, bitblts, transparent blts
and fills. These operations can act on off-screen on-screen areas. The frame buffer size rangesto4 Mbytes anywherein the physical main
memory.
The graphics resolution supportedisa maximum 1280x1024in 65536 coloursat 75Hz refresh
rate andis VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extendedby onebitto accommodate the
above display resolution.
STPC Consumer provides several additional func-
tionsto handle MPEGor similar video streams.
The Video Input Port accepts an encoded digital
video streamin oneofa numberof industry stand-
ard formats, decodesit, optionally decimatesitby factorof 2:1, and depositsit into an off screen
areaof the frame buffer. An interrupt request can generated whenan entire fieldor frame has
been captured.
GENERAL DESCRIPTION7/51
The video output pipeline incorporatesa video-
scaler and color space converter function and pro-
visionsin the CRT controllerto displaya video
window. While repainting the screen the CRT con-
troller fetches both the videoas wellas the normal
non-video frame bufferin two separate internal
FIFOs (256-Bytes each). The video stream canbe
color-space converted (optionally) and smooth
scaled. Smooth interpolative scalingin both hori-
zontal and vertical directions are implemented.
Color and Chroma key functions are also imple-
mentedto allow mixing video stream with non-vid- frame buffer.
The video output passes directlyto the RAMDAC
for monitor output or through another optional
color space converter (RGBto 4:2:2 YCrCb)to the
programmable anti-flicker filter. The flicker filteris
configured as eithera two line filter with gamma
correction (primarily designed for DOS type text)a3 line flicker filter (primarily designedfor Win-
dows type displays). The flicker filteris optional
and canbe software disabled for use with videoon
large screen areas.
The Video output pipelineof the STPC Consumer
interfaces directlyto the internal digital TV encod-
er.It takesa 24 bit RGB non-interlaced pixel
stream and convertstoa multiplexed 4:2:2 YCrCbbit output stream, the logic includesa progres-
siveto interlaced scan converter and logicto in-
sert appropriate CCIR656 timing reference codes
into the output stream.It facilitates the high quality
displayof VGAor full screen video streams re-
ceived via the Video input portto standard NTSC PAL televisions.
The STPC Consumer coreis compliant with the
Advanced Power Management (APM) specifica-
tionto providea standard methodby which the
BIOS can control the power used by personal
computers. The Power Management Unit module
(PMU) controls the power consumptionby provid-
inga comprehensive setof features that control
the power usage and supports compliance with
the United States Environmental Protection Agen-
cy’s Energy Star Computer Program. The PMU
provides following hardware structuresto assist
the softwarein managing the power consumption the system. System Activity Detection.3 power-down timers detecting system inactivity: Doze timer (short durations). Stand-by timer (medium durations). Suspend timer (long durations). House-keeping activity detection. House-keeping timerto cope with short burstsof
house-keeping activity while dozingorin stand-by
state. Peripheral activity detection. Peripheral timer detecting peripheral inactivity SUSP# modulationto adjust the system perform-
ancein various power down statesof the system
including full power on state. Power control outputsto disable power from dif-
ferent planesof the board.
Lackof system activity for progressively longer
periodof timesis detected by the three power
down timers. These timers can generate SMI in-
terruptsto CPUso that the SMM software can put
the systemin decreasing statesof power con-
sumption. Alternatively, system activityina power
down state can generate SMI interruptto allow the
softwareto bring the system backupto full power state. The chip-set supportsupto three power
down states: Doze state, Stand-by state and Sus-
pend mode. These correspondto decreasing lev-
elsof power savings.
Power down puts the STPC Consumer into sus-
pend mode. The processor completes execution the current instruction, any pending decodedin-
structions and associated bus cycles. During the
suspend mode, internal clocks are stopped. Re-
moving power down, the processor resumes in-
struction fetching and begins executionin thein-
struction streamat the pointit had stopped. reference design for the STPC Consumeris
available including the schematics and layout
files, the designisa PC ATX motherboard design.
The designis availableasa demonstration board
for application and system development.
The STPC Consumeris supported by several
BIOS vendors, including the super I/O device
usedin the reference design. Driversfor 2D accel-
erator, video features and EIDE are availaible on
various operating systems.
The STPC Consumer has been designed using
modern reusable modular design techniques,itis
possibleto addor remove the standard featuresof
the STPC Consumer or other variants of the
5ST86 family. Contact your local STMicroelecton-
ics sales office for further information.
GENERAL DESCRIPTION8/51
Figure 1-1 Functionnal descriptionx86
Core
Host I/F
DRAM
SVGA
VIP
PCI m/s
PCI BUSISA
EIDEPCI m/s
ISA BUSCRTC HW Cursor
Monitor Output
SYNC OutputIPC
Anti-Flicker
Color SpaceColor
Key
Chroma
Video
pipeline
CCIR Input
EIDEDigital
PAL/
GENERAL DESCRIPTION9/51
Figure 1-2 Typical Application
STPC Consumer
ISA
PCI 16-bit EDO DRAMs
Super I/O EIDE
Flash
Keyboard/ Mouse
Serial Ports
Parallel Port
Floppy
Monitor
VideoSVGA
CCIR601
CCIR656
S-VHS
RGB
PAL
NTSC
IRQ
DMA.REQ
DMA.ACK
DMUX
DMUX
MUX
MUX
RTC
PIN DESCRIPTION10/51
PIN DESCRIPTION
2.1 INTRODUCTIONThe STPC Consumer integrates mostof the func-
tionalitiesof the PC architecture.Asa result, many the traditional interconnections between the
host PC microprocessor and the peripheral devic- aretotally internalto the STPC Consumer. This
offers improved performance dueto the tight cou-
plingof the processor core and these peripherals.a result manyof the external pin connections
are made directlyto the on-chip peripheral func-
tions.
Figure 2-1 shows the STPC Consumer’s external
interfaces.It defines the main busses and their
function. Table 2-1 describes the physical imple-
mentation listing signal types and their functional-
ities. Table 2-2 providesa full pin listing and de-
scription. Table 2-3 providesa full listingof the
STPC Consumer pin locationsof package by
physical connection. Please referto the pin alloca-
tion drawingfor reference.
Note: Several interface pins are multiplexed with
other functions, referto the Pin Description sec-
tionfor further details
Table 2-1. Signal Description
Group name QtyBasic Clocks reset& Xtal(SYS) 12
DRAM Controller 89
PCI interface (PCI) 58
ISA/ IDE/ IPC combined interface 88
Video Input (VIP) 9 Output 10
VGA Monitor interface 10
Grounds 69
VDD 26
Analog specificVCC/VDD 12
Reserved 5
Total Pin Count 388
Figure 2-1. STPC Consumer External Interfaces
SOUTHNORTH PCI
x86
DRAM VGA VIP TV SYS ISA/IDE IPC 10 9 10 58 13 77 11
STPC Consumer
PIN DESCRIPTION11/51
Table 2-2. Definitionof Signal Pins
Signal Name Dir Description Qty
BASIC CLOCKS AND RESETSSYSRSTI# I System Reset/ Power good 1
XTALI I 14.3MHz Crystal Input 1
XTALO I/O 14.3MHz Crystal Output- External Oscillator Input 1
HCLK O Host Clock (Test) 1
DEV_CLK O 24MHz Peripheral Clock (floppy drive) 1
GCLK2X I/O 80MHz Graphics Clock 1
DCLK I/O 135MHz Dot Clock 1
PCI_CLKI I 33MHz PCI Input Clock 1
PCI_CLKO O 33MHz PCI Output Clock (from internal PLL) 1
SYSRSTO# O Reset Outputto System 1
ISA_CLK O ISA Clock Output- Multiplexer Select Line For IPC 1
ISA_CLK2X O ISA Clockx2 Output- Multiplexer Select Line For IPC 1
MEMORY INTERFACEMA[11:0] I/O Memory Address 12
RAS#[3:0] O Row Address Strobe 4
CAS#[7:0] O Column Address Strobe 8
MWE# O Write Enable 1
MD[63:0] I/O Memory Data 64
PCI INTERFACEAD[31:0] I/O PCI Address/ Data 32
CBE[3:0] I/O Bus Commands/ Byte Enables 4
FRAME# I/O Cycle Frame 1
TRDY# I/O Target Ready 1
IRDY# I/O Initiator Ready 1
STOP# I/O Stop Transaction 1
DEVSEL# I/O Device Select 1
PAR I/O Parity Signal Transactions 1
SERR# O System Error 1
LOCK# I PCI Lock 1
PCIREQ#[2:0] I PCI Request 3
PCIGNT#[2:0] O PCI Grant 3
PCI_INT[3:0] I PCI Interrupt Request 4
VDD5 I 5V Power Supplyfor PCI ESD protection 4
ISA AND IDE COMBINED ADDRESS/DATALA[23:22]/ SCS3#,SCS1# I/O Unlatched Address (ISA)/ Secondary Chip Select (IDE) 2
LA[21:20]/ PCS3#,PCS1# I/O Unlatched Address (ISA)/ Primary Chip Select (IDE) 2
LA[19:17]/ DA[2:0] O Unlatched Address (ISA)/ Address (IDE) 3
RMRTCCS#/ DD[15] I/O ROM/RTC Chip Select/ Data Busbit15 (IDE) 1
KBCS#/ DD[14] I/O Keyboard Chip Select/ Data Busbit14 (IDE) 1
RTCRW#/ DD[13] I/O RTC Read/Write/ Data Busbit13 (IDE) 1
RTCDS#/ DD[12] I/O RTC Data Strobe/ Data Busbit12 (IDE) 1
SA[19:8]/ DD[11:0] I/O Latched Address (ISA)/ Data Bus (IDE) 16
SA[7:0] I/O Latched Address (IDE) 4
SD[15:0] I/O Data Bus (ISA) 16
PIN DESCRIPTION12/51
ISA/IDE COMBINED CONTROLIOCHRDY/ DIORDY I/O I/O Channel Ready (ISA)- Busy/Ready (IDE) 1
ISA CONTROLOSC14M O ISA bus synchronisation clock 1
ALE O Address Latch Enable 1
BHE# I/O System Bus High Enable 1
MEMR#, MEMW# I/O Memory Read and Memory Write 2
SMEMR#, SMEMW# O System Memory Read and Memory Write 2
IOR#, IOW# I/O I/O Read and Write 2
MASTER# I AddOn Card Owns Bus 1
MCS16#, IOCS16# I Memory/IO Chip Select16 2
REF# O Refresh Cycle. 1
AEN O Address Enable 1
ZWS# I Zero Wait State 1
IOCHCK# I I/O Channel Check. 1
ISAOE# O Bidirectional OE Control 1
RTCAS# O Real Time Clock Address Strobe 1
GPIOCS# I/O General Purpose Chip Select 1
IDE CONTROLPIRQ I Primary Interrupt Request 1
SIRQ I Secondary Interrupt Request 1
PDRQ I Primary DMA Request 1
SDRQ I Secondary DMA Request 1
PDACK# O Primary DMA Acknowledge 1
SDACK# O Secondary DMA Acknowledge 1
PIOR# I/O Primary I/O Read 1
PIOW# O Primary I/O Write 1
SIOR# I/O Secondary I/O Read 1
SIOW# O Secondary I/O Write 1
IPCIRQ_MUX[3:0] I Multiplexed Interrupt Request 4
DREQ_MUX[1:0] I Multiplexed DMA Request 2
DACK_ENC[2:0] O DMA Acknowledge 3 O ISA Terminal Count 1
MONITOR INTERFACERED, GREEN, BLUE O Red, Green, Blue 3
VSYNC O Vertical Sync 1
HSYNC O Horizontal Sync 1
VREF_DAC I DAC Voltage reference 1
RSET I Resistor Set 1
COMP I Compensation 1
DDC[1:0] I/O Display Data Channel Serial Link 2
SCL/ DDC[1] I/O I C Interface- Clock/ Canbe usedfor VGA DDC[1] signal 1
Table 2-2. Definitionof Signal Pins
Signal Name Dir Description Qty
PIN DESCRIPTION13/51
SDA/ DDC[0] I/O I C Interface- Data/ Canbe usedfor VGA DDC[0] signal 1
COL_CMP O Color Compare Output.
VIDEO INPUTVCLK I Pixel Clock 1
VIN I YUV Video Data Input CCIR 601or 656 8
DIGITALTV OUTPUTRED_TV, GREEN_TV, BLUE_TV O Analog video outputs synchronized with CVBS 3
VCS O Composite Synchor Horizontal line SYNC output 1
ODD_EVEN O Frame Synchronisation 1
CVBS O Analog video composite output (luminance/ chrominance) 1
IREF1_TV I Reference currentof 9bit DACfor CVBS 1
VREF1_TV I Reference voltageof 9bit DACfor CVBS 1
IREF2_TV I Reference currentof 8bit DACfor R,G,B 1
VREF2_TV I Reference voltageof 8bit DACfor R,G,B 1
VSSA_TV I Analog Vssfor DAC 1
VDDA_TV I Analog Vddfor DAC 1
MISCELLANEOUSSPKRD O Speaker Device Output 1
SCAN_ENABLE I Reserved (Test pin) 1
Table 2-2. Definitionof Signal Pins
Signal Name Dir Description Qty
PIN DESCRIPTION14/51
2.2 SIGNAL DESCRIPTIONS
2.2.1 BASIC CLOCKS AND RESETS
SYSRSTI System Reset/Power good. This inputis
low when the reset switchis depressed. Other-
wise,it reflects the power supply’s power good
signal. SYSRSTIis asynchronousto all clocks,
and actsasa negative active reset. The reset cir-
cuit initiatesa hard reset on the rising edgeof
SYSRSTI.
SYSRSTO# Reset Outputto System. Thisis the
system resetsignal andis usedto reset the restof
the components (noton Host bus)in the system.
The ISA bus resetis an externally inverted buff-
ered versionof this output and the PCI bus resetis externally buffered versionof this output.
XTALI 14.3MHz Crystal Input
XTALO 14.3MHz Crystal Output. These pins are
the 14.318MHz crystal input; This clockis usedas
the reference clock for the internal frequency syn-
thesizer to generate the HCLK, CLK24M,
GCLK2X and DCLK clocks. 14.318 MHz Series Cut Quartz Crystal should connected between these two pins. Balance
capacitorsof15 pF should also be added.In the
eventofan external oscillator providing the master
clock signalto the STPC Consumer device, the
TTL signal shouldbe providedon XTALO.
HCLK Host Clock. Thisis the host 1X clock. Its
frequency can vary from 25to 75 MHz. All host
transactions and PCI transactions are synchro-
nizedto this clock. The DRAM controllerto exe-
cute the host transactionsis also driven by this
clock.In normal mode, this output clockis gener-
atedby the internal pll.
GCLK2X 80MHz Graphics Clock. Thisis the
Graphics 2X clock, which drives the graphics en-
gine and the DRAM controllerto execute the
graphics and display cycles.
Normally GCLK2Xis generatedby the internal fre-
quency synthesizer, and this pinis an output. By
settingabitin Strap Register2, this pin can be
made an input so that an external clock can re-
place the internal frequency synthesizer.
PCI_CLKI 33MHz PCI Input Clock
This signalis the PCI bus clock input and should driven from the PCI_CLKO pin.
PCI_CLKO 33MHz PCI Output Clock. Thisis the
master PCI bus clock output.
DCLK 135MHz Dot Clock. Thisis the dot clock,
which drives graphics display cycles.Its frequency
cango from 8MHz (using internal PLL) upto 135
MHz, anditis requiredto havea worst case duty
cycleof 60-40.
This signal iseither drivenby the internalpll (VGA) an external 27MHz oscillator (when the com-
posite video outputis enabled). The direction can controlledbya strap optionoran internal regis-
ter bit.
ISA_CLK ISA Clock Output (also Multiplexer Se-
lect Line For IPC). This pin produces the Clock
signal for the ISA bus.Itis also used with
ISA_CLK2Xas the multiplexorcontrol linesfor the
Interrupt Controller Interrupt input lines. Thisisa
divided down versionof either the PCICLKor
OSC14M.
ISA_CLKX2 ISA Clock Output (also Multiplexer
Select Line For IPC). This pin producesa signal
thatis twice the frequencyof the ISA bus Clock
signal.Itis also used with ISA_CLKas the multi-
plexor control lines for the Interrupt Controllerin-
put lines.
DEV_CLK 24MHz Peripheral Clock Output. This
24MHZ signalis providedasa convenience for
the system integrationofa Floppy Disk driver
functioninan external chip.
OSC14M ISA bus synchronisation clock Output.
Thisis the buffered 14.318 Mhz clockto the ISA
bus.
2.2.2 MEMORY INTERFACE
MA[11:0] Memory Address Output. These12 mul-
tiplexed memory address pins support external
DRAM with upto 4K refresh. These include all
16MxN and some 4MxN DRAM modules. The
address signals must be externally bufferedto
support more than16 DRAM chips. The timingof
these signals can be adjusted by softwareto
match the timingsof most DRAM modules.
PIN DESCRIPTION15/51
MD[63:0] Memory Data I/O. Thisis the 64-bit
memory data bus.If only halfofa bankis populat-
ed, MD63-32is pulled high, dataison MD31-0.
MD[40-0] are readby the device strap option reg-
isters during rising edgeof SYSRSTI.
RAS#[3:0] Row Address Strobe Output. There
are4 active low row address strobe outputs, one
for each bankof the memory. Each bank containsor 8-Bytesof data. The memory controllerallows
halfofa bank (4-bytes)tobe populatedto enable
memory upgradeat finer granularity.
The RAS# signals drive the SIMMs directly with-
out any external buffering. These pins are always
outputs, but they can also simultaneously be in-
puts, toallow the memory controllerto monitor the
valueof the RAS# signalsat the pins.
CAS#[7:0] Column Address Strobe Output. There
are8 active low column address strobe outputs,
one eachfor each byteof the memory.
The CAS# signals drive the SIMMs either directly through external buffers.
These pins are always outputs, but they can also
simultaneously be inputs,to allow the memory
controllerto monitor the valueof the CAS# signals the pins.
MWE# Write Enable Output. Write enable speci-
fies whether the memory accessisa read (MWE#H)ora write (MWE#=L). This single write ena-
ble controls all the DRAM.It can be externally
bufferedto boost the maximum numberof loads
(DRAM chips) supported.
The MWE# signals drive the SIMMs directly with-
out any external buffering.
2.2.3 VIDEO INTERFACE
VCLK Pixel Clock Input.
VIN[7:0] YUV Video Data Input CCIR 601or 656.
Time multiplexed 4:2:2 luminance and chromi-
nance data as definedin ITU-R Rec601-2 and
Rec656 (except for TTL input levels). This busin-
terfaces withan MPEG video decoder output port
and typically carriesa streamof Cb,Y,Cr,Y digital
videoat VCLK frequency, clocked on the rising
edge (by default)of VCLK.A 54-Mbit/s ‘double’
Cb,Y, Cr,Y input multiplexis supportedfor double
encoding application (rising and falling edgeof
CKREF are operating).
2.2.4 TV OUTPUT
RED_TV/ C_TV Analog video outputs synchro-
nized with CVBS. This outputis current-driven and
must be connectedto analog ground overa load
resistor (RLOAD). Following the load resistor,a
simple analog low pass filteris recommended.In
S-VHS mode, thisis the Chrominance Output.
GREEN_TV/ Y_TV Analog video outputs syn-
chronized with CVBS. This outputis current-driv- and mustbe connectedto analog ground over load resistor (RLOAD). Following the load resis-
tor,a simple analog low pass filteris recommend-
ed.In S-VHS mode, thisis the Luminance Output.
BLUE_TV/ CVBSAnalog video outputs synchro-
nized with CVBS. This outputis current-driven and
must be connectedto analog ground overa load
resistor (R LOAD). Following the load resistor,a
simple analog low pass filteris recommended.In
S-VHS mode, thisisa second composite output.
VCS Line synchronisation Output. This pinis an
inputin ODDEV+HSYNCor VSYNC+ HSYNCor
VSYNC slave modes and an outputinall other
modes (master/slave)
The signalis synchronousto rising edgeof CK-
REF. The default polarity usesa negative pulse
ODD_EVEN Frame Synchronisation Ourput. This
pin supports the Frame synchronisation signal.It an inputin slave modes, except when syncis
extracted from YCrCb data, andan outputin mas-
ter mode and when syncis extracted from YCrCb
data
The signalis synchronousto rising edgeof DCLK.
The default polarity for this pinis: odd (not-top) field: LOW level even (bottom) field: HIGH level
IREF1_TV Ref. current for CVBS 10-bit DAC.
VREF1_TV Ref. voltage for CVBS 10-bit DAC.
IREF2_TV Reference currentfor RGB 9-bit DAC.
VREF2_TV Reference voltagefor RGB 9-bit DAC.
VSSA_TV AnalogVSS for DAC
VDDA_TV AnalogVDDfor DAC
CVBS Analog video composite output (luminance/
chrominance). CVBSis current-driven and must connectedto analog ground overa load resis-
tor (RLOAD). Following the load resistor,a simple
analog low pass filteris recommended.
2.2.5 PCI INTERFACE
AD[31:0] PCI Address/Data. Thisis the 32-bit
multiplexed address and data busof the PCI. This
busis driven by the master during the address
phase and data phaseof write transactions.Itis
PIN DESCRIPTION16/51
driven by the target during data phaseof read
transactions.
CBE#[3:0] Bus Commands/Byte Enables. These
are the multiplexed command and byte enable
signalsof the PCI bus. During the address phase
they define the command and during the data
phase they carry the byte enable information.
These pins are inputs whena PCI master other
than the STPC Consumer owns the bus and out-
puts when the STPC Consumer owns the bus.
FRAME# Cycle Frame. Thisis the frame signalof
the PCI bus.Itisan input when aPCI master owns
the bus andisan output when STPC Consumer
owns the PCI bus.
TRDY# Target Ready. Thisis the target ready sig-
nalof the PCI bus.Itis drivenasan output when
the STPC Consumeris the targetof the current
bus transaction.Itis usedasan input when STPC
Consumer initiatesa cycleon the PCI bus.
IRDY# Initiator Ready. Thisis the initiator ready
signalof the PCI bus.Itis usedasan output when
the STPC Consumer initiatesa bus cycle on the
PCI bus.Itis usedasan input during the PCI cy-
cles targetedto the STPC Consumerto determine
when the current PCI masteris readyto complete
the current transaction.
STOP# Stop Transaction. Stopis usedto imple-
ment the disconnect, retry and abort protocolof
the PCI bus.Itis usedasan input for the bus cy-
cles initiatedby the STPC Consumer andis usedan output whena PCI master cycleis targeted the STPC Consumer.
DEVSEL# I/O Device Select. This signalis used an input when the STPC Consumer initiatesa
bus cycle on the PCI busto determineifa PCI
slave device has decoded itselftobe the targetof
the current transaction.Itis assertedasan output
either when the STPC Consumeris the targetof
the current PCI transactionor whenno other de-
vice asserts DEVSEL# priorto the subtractive de-
code phaseof the current PCI transaction.
PAR Parity Signal Transactions. Thisis the parity
signalof the PCI bus. This signalis usedto guar-
antee even parity across AD[31:0], CBE#[3:0],
and PAR. This signalis drivenby the master dur-
ing the address phase and data phaseof write
transactions.Itis drivenby the target during data
phaseof read transactions. (Its assertionis identi-
calto thatof the AD bus delayedby one PCI clock
cycle)
SERR# System Error. Thisis the system error sig-
nalof the PCI bus.It may,if enabled,be asserted
for one PCI clock cycleif target abortsa STPC
Consumer initiated PCI transaction.Its assertion either the STPC Consumerorby another PCI
bus agent will trigger the assertionof NMIto the
host CPU. Thisisan open drain output.
LOCK# PCI Lock. Thisis the lock signalof the PCI
bus andis usedto implement the exclusive bus
operations when actingasa PCI target agent.
PCIREQ#[2:0] PCI Request. This pin are the
three external PCI master request pins. They indi-
catesto the PCI arbiter that the external agents
desire useof the bus.
PCIGNT#[2:0] PCI Grant. These pins indicate that
the PCI bus has been grantedto the master re-
questingitonits PCIREQ#.
2.2.6 ISA/IDE COMBINED ADDRESS/DATA
LA[23]/SCS3# Unlatched Address (ISA)/Second-
ary Chip Select (IDE). This pin has two functions,
dependingon whether the ISA busis activeor the
IDE busis active.
When the ISA busis active, this pinsis ISA Bus
unlatched addressbit23for 16-bit devices. When
ISA busis accessed by any cycle initiated from
PCI bus, this pinisin output mode. Whenan ISA
bus master owns the bus, this pinsisin input
mode.
When the IDE busis active, this signalsis usedas
the active high secondary slave IDE chip select
signal. This signalistobe externally NANDed with
the ISAOE# signal before driving the IDE devices guaranteeitis active only when ISA busis idle.
PIN DESCRIPTION17/51
LA[22]/SCS1# Unlatched Address (ISA)/Second-
ary Chip Select (IDE)
This pin has two functions, dependingon whether
the ISA busis activeor the IDE busis active.
When the ISA busis active, this pinsis ISA Bus
unlatched addressbit22for 16-bit devices. When
ISA busis accessed by any cycle initiated from
PCI bus, this pinisin output mode. Whenan ISA
bus master owns the bus, this pinsisin input
mode.
When the IDE busis active, this signalsis usedas
the active high secondary slave IDE chip select
signal. This signalistobe externally ANDed with
the ISAOE# signal before driving the IDE devices guaranteeitis active only when ISA busis idle.
LA[21]/PCS3# Unlatched Address (ISA)/Primary
Chip Select (IDE). This pin has two functions, de-
pending on whether the ISA busis activeor the
IDE busis active.
When the ISA busis active, this pinsis ISA Bus
unlatched addressbit21for 16-bit devices. When
ISA busis accessed by any cycle initiated from
PCI bus, this pinisin output mode. Whenan ISA-
bus master owns the bus, this pinsisin input
mode.
When the IDE busis active, this signalsis usedas
the active high primary slave IDE chip select sig-
nal. This signalisto be externally NANDed with
the ISAOE# signal before driving the IDE devices guaranteeitis active only when ISA busis idle.
LA[20]/PCS1# Unlatched Address (ISA)/Primary
Chip Select (IDE). This pin has two functions, de-
pending on whether the ISA busis activeor the
IDE busis active.
When the ISA busis active, this pinsis ISA Bus
unlatched addressbit20for 16-bit devices. When
ISA busis accessed by any cycle initiated from
PCI bus, this pinisin output mode. Whenan ISA
bus master owns the bus, this pinsisin input
mode.
When the IDE busis active, this signalsis usedas
the active high primary slave IDE chip select sig-
nal. This signalisto be externally NANDed with
the ISAOE# signal before driving the IDE devices guaranteeitis active only when ISA busis idle.
LA[19:17]/DA[2:0] Unlatched Address (ISA)/Ad-
dress (IDE). These pins are multi-function pins.
They are usedas the ISA bus unlatched address
bits [19:17] for ISA busor the three address bits
for the IDE bus devices.
When usedby the ISA bus, these pins are ISA
Bus unlatched address bits 19-17on 16-bit devic-
es. When ISA busis accessedby any cycle initiat- from the PCI bus, these pins arein output
mode. When an ISA bus master owns the bus,
these pins are tristated.
For IDE devices, these signals are used as the
DA[2:0] and are connectedto DA[2:0]of IDE de-
vices directlyor througha buffer.If the togglingof
signals areto be masked during ISA bus cycles,
they can be externally ORed before being con-
nectedto the IDE devices.
SA[19:8]/DD[11:0] Unlatched Address (ISA)/Data
Bus (IDE). These are multifunction pins. When the
ISA busis active, they are usedas the ISA bus
system address bits 19-8. When the IDE busis ac-
tive, they serveas IDE signals DD[11:0].
These pins are usedasan input whenan ISA bus
master owns the bus and are outputsatall other
times.
IDE devices are connectedto SA[19:8] directlyand
ISA busis connectedto these pins through two
LS245 transceivers. The OEof the transceivers
are connectedto ISAOE# and DIRis connectedto
MASTER#.A bus signalsof the transceivers are
connectedto CPC and IDE DD bus andB bus sig-
nals are connectedto ISA SA bus.
DD[15:12] Databus (IDE). The high4 bitsof the
IDE databus are combined with severalof theX-
bus lines. Referto the following section for X-bus
pinsfor further information.
SA[7:0] ISA Bus address bits [7:0]. These are the low bitsof the system address busof ISAon8-
bit slot. These pins are usedas an input whenan
ISA bus master owns the bus and are outputsat
all other times.
SD[15:0] I/O Data Bus (ISA). These pins are the
external databusto the ISA bus.
PIN DESCRIPTION18/51
2.2.7 ISA/IDE COMBINED CONTROL
IOCHRDY/DIORDY Channel Ready (ISA)/Busy/
Ready (IDE). Thisisa multi-function pin. When
the ISA busis active, this pinis IOCHRDY. When
the IDE busis active, this servesas IDE signal DI-
ORDY.
IOCHRDYis the IO channel ready signalof the
ISA bus andis drivenas an outputin responseto ISA master cycle targetedto the host busoran
internal register of the STPC Consumer. The
STPC Consumer monitors this signalasan input
when performing an ISA cycle on behalfof the
host CPU, DMA masteror refresh.
ISA masters whichdo not monitor IOCHRDY are
not guaranteedto work with the STPC Consumer
since the accessto the system memory can be
considerably delayed dueto CRT refresh ora
write back cycle.
2.2.8 ISA CONTROL
ALE Address Latch Enable. Thisis the address
latch enable outputof the ISA bus andis asserted the STPC Consumerto indicate that LA23-17,
SA19-0, AEN and SBHE# signals are valid. The
ALEis driven high during refresh, DMA masteror ISA master cyclesby the STPC Consumer.
ALEis driven low after reset.
BHE# System Bus High Enable. This signal, when
asserted, indicates thata data byteis being trans-
ferredon SD15-8 lines.Itis usedasan input when ISA master owns the bus andisan outputatall
other times.
MEMR# Memory Read. Thisis the memory read
command signalof the ISA bus.Itis usedasanin-
put when an ISA master owns the bus andisan
outputatall other times.
The MEMR# signalis active during refresh.
MEMW# Memory Write. Thisis the memory write
command signalof the ISA bus.Itis usedasanin-
put when an ISA master owns the bus andisan
outputatall other times.
SMEMR# System Memory Read. The STPC Con-
sumer generates SMEMR# signalof the ISA bus
only when the addressis below one megabyteor
the cycleisa refresh cycle.
SMEMW# System Memory Write. The STPC Con-
sumer generates SMEMW# signalof the ISA bus
only when the addressis below one megabyte.
This signalis multiplexed with COL_CMP on the
VGA Interface. The signalis selected by setting
Strap Option MD[0]as describedin Section3.
IOR# I/O Read. Thisis theIO read command sig-
nalof the ISA bus.Itisan input whenan ISA mas-
ter owns the bus andis an outputat all other
times.
IOW# I/O Write. Thisis theIO write command sig-
nalof the ISA bus.Itisan input whenan ISA mas-
ter owns the bus andis an outputat all other
times.
MASTER# Add On Card Owns Bus. This signalis
active whenan ISA device has been granted bus
ownership.
MCS16# Memory Chip Select16. Thisis the de-
codeof LA23-17 address pinsof the ISA address
bus without any qualificationof the command sig-
nal lines. MCS16#is always an input. The STPC
Consumer ignores this signal during IO and re-
fresh cycles.
IOCS16#IO Chip Select16. This signalis the de-
codeof SA15-0 address pinsof the ISA address
bus without any qualificationof the command sig-
nals. The STPC Consumer does not drive
IOCS16# (similarto PC-AT design). An ISA mas-
ter accesstoan internal registerof the STPC Con-
sumeris executedasan extended 8-bitIO cycle.
REF# Refresh Cycle. Thisis the refresh command
signalof the ISA bus.Itis driven as an output
when the STPC Consumer performsa refresh cy-
cleon the ISA bus.Itis usedasan input whenan
ISA master owns the bus andis usedto triggera
refresh cycle.
The STPC Consumer performsa pseudo hidden
refresh.It requests the host bus for two host
clocksto drive the refresh address and captureit external buffers. The host busis then relin-
quished while the refresh cycle continues on the
ISA bus.
AEN Address Enable. Address Enableis enabled
when the DMA controlleris the bus ownerto indi-
cate thata DMA transfer will occur. The enabling the signal indicatestoIO devicesto ignore the
IOR#/IOW# signal during DMA transfers.
ZWS# Zero Wait State. This signal, when assert-by addressed device, indicates that current cy-
cle canbe shortened.
IOCHCK#IO Channel Check.IO Channel Check enabledby any ISA deviceto signal an error
condition that can notbe corrected. NMI signal be-
comes active upon seeing IOCHCK# activeif the
correspondingbitin PortBis enabled.
PIN DESCRIPTION19/51
ISAOE# Bidirectional OE Control. This signal con-
trols the OE signalof the external transceiver that
connects the IDE DD bus and ISA SA bus.
GPIOCS# I/O General Purpose Chip Select1.
This output signalis usedby the external latchon
ISA busto latch the data on the SD[7:0] bus. The
latch canbe useby PMU unitto control the exter-
nal peripheral devicesto powerdownor any other
desired function.
This pinis also servesasa strap input during re-
set.
2.2.9 IDE CONTROL
PIRQ Primary Interrupt Request. Interrupt request
from primary IDE channel.
SIRQ Secondary Interrupt Request. Interrupt re-
quest from secondary IDE channel.
PDRQ Primary DMA Request. DMA request from
primary IDE channel.
SDRQ Secondary DMA Request. DMA request
from secondary IDE channel.
PDACK# Primary DMA Acknowledge. DMA ack-
noledgeto primary IDE channel.
SDACK# Secondary DMA Acknowledge. DMA
acknoledgeto secondary IDE channel.
PIOR# Primary I/O Read. Primary channel read.
Active low output.
PIOW# Primary I/O Write. Primary channel write.
Active low output.
SIOR# Secondary I/O Read Secondary channel
read. Active low output.
SIOW# Secondary I/O Write Secondary channel
write. Active low output.
2.2.10 IPC
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They are be encoded before connectionto the STPC
Consumer using ISACLK and ISACLKX2 as the
input selection strobes.
Note that IRQ8B, whichby conventionis connect-to the RTC,is inverted before being sentto the
interrupt controller,so thatit maybe connected di-
rectlyto the IRQ pinof the RTC.
PCI_INT[3:0] PCI Interrupt Request. These are
the PCI bus interrupt signals. They aretobe en-
coded before connectionto the STPC Consumer
using ISACLK and ISACLKX2as the input selec-
tion strobes.
DREQ_MUX[1:0] ISA Bus Multiplexed DMA Re-
quest. These are the ISA bus DMA request sig-
nals. They aretobe encoded before connectionto
the STPC Consumer using ISACLK and
ISACLKX2as the input selection strobes.
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Consumer before output
and should be decoded externally using ISACLK
and ISACLKX2as the control strobes.
ISA Terminal Count. Thisis the terminal count
outputof the DMA controller andis connectedto
the TClineof the ISA bus.Itis asserted during the
last DMA transfer, when the byte count expires.
SPKRD Speaker Drive. This the outputto the
speaker andis ANDof the counter2 output with
bit1of Port 61, and drives an external speaker
driver. This output should be connectedto 7407
type high voltage driver.
2.2.11 X-Bus Interface pins/ IDE Data
RMRTCCS#/ DD[15] ROM/Real Time clock chip
select. This pinisa multi-function pin. When
ISAOE#is active, this signalis used as RM-
RTCCS#. This signalis assertedifa ROM access decoded duringa memory cycle.It should be
combined with MEMR#or MEMW# signalsto
properly access the ROM. DuringaIO cycle, this
signalis assertedif accessto the Real Time Clock
(RTC)is decoded.It shouldbe combined with IOR IOW# signalsto properly access the real time
clock.
When ISAOE#is inactive, this signalis usedas
IDE DD[15] signal.
This signal mustbe ORed externally with ISAOE#
andis then connectedto ROM and RTC. An
LS244or equivalent function canbe usedif OE#is
connectedto ISAOE# and the outputis provided
witha weak pull-up resistor.
KBCS#/ DD[14] Keyboard Chip Select. This pina multi-function pin. When ISAOE#is active,
this signalis usedas KBCS#. This signalis assert-ifa keyboard accessis decoded duringa I/O
cycle.
When ISAOE#is inactive, this signalis usedas
IDE DD[14] signal.
This signal mustbe ORed externally with ISAOE#
andis then connectedto keyboard. An LS244or
equivalent function canbe usedif OE#is connect-
PIN DESCRIPTION20/51to ISAOE# and the outputis provided witha
weak pull-up resistor.
RTCRW#/ DD[13] Real Time Clock RW. This pina multi-function pin. When ISAOE#is active,
this signalis usedas RTCRW#. This signalis as-
serted for any I/O writeto port 71H.
When ISAOE#is inactive, this signalis usedas
IDE DD[13] signal.
This signal mustbe ORed externally with ISAOE#
and then connectedto the RTC. An LS244or
equivalent function canbe usedif OEis connect-to ISAOE# and the outputis provided witha
weak pull-up resistor.
RTCDS#/ DD[12] Real Time Clock DS. This pinis multi-function pin. When ISAOE#is active, this
signalis usedas RTCDS. This signalis asserted
for any I/O readto port 71H.
When ISAOE#is inactive, this signalis usedas
IDE DD[12] signal.
This signal mustbe ORed externally with ISAOE#
andis then connectedto RTC.An LS244or equiv-
alent function can be usedif OE#is connectedto
ISAOE# and the outputis provided witha weak
pull-up resistor.
RTCAS# Real time clock address strobe. This sig-
nalis assertedfor any I/O writeto port 70H.
2.2.12 Monitor Interface
RED, GREEN, BLUE RGB Video Outputs. These
are the3 analog color outputs from the RAMDACs
VSYNC Vertical Synchronisation Pulse. Thisis
the vertical synchronization signal from the VGA
controller.
HSYNC Horizontal Synchronisation Pulse. Thisis
the horizontal synchronization signal from the
VGA controller.
VREF_DAC DAC Voltage reference. An external
voltage referenceis connectedto this pinto bias
the DAC.
RSET Resistor Current Set. Thisis reference cur-
rent inputto the RAMDACis usedto set the full-
scale outputof the RAMDAC.
COMP Compensation. Thisis the RAMDAC com-
pensation pin. Normally, an external capacitor
(typically 10nF)is connected between this pin andDDto damp oscillations.
DDC[1:0] Direct Data Channel Serial Link. These
bidirectional pins are connectedto CRTC register
3Fhto implement DDC capabilities. They conformI2C electrical specifications, they have open-
collector output drivers which are internally con-
nectedto VDD through pull-up resistors.
They can insteadbe usedfor accessing I C devic-on board. DDC1 and DDC0 correspond toSCL
and SDA respectively.
COL_CMP Color Compare Output. Allows access the video signal which flags when thereisa
color compare hit. This signalis multiplexed with
SMEMEW#on the ISA Bus. The signalis selected setting Strap Option MD[0]as describedin Sec-
tion3.
2.2.13 MISCELLANEOUS
SCAN_ENABLE Reserved. The pins are re-
servedfor Test and Miscellaneous functions)
PIN DESCRIPTION21/51
Table 2-3. Pinout.
Pin# Pin nameAF3 SYSRSTI XTALI XTALO
G23 HCLK
F25 DEV_CLK
AF15 GCLK2X
AF9 DCLK
AD15 MA[0]
AF16 MA[1]
AC15 MA[2]
AE17 MA[3]
AD16 MA[4]
AF17 MA[5]
AC17 MA[6]
AE18 MA[7]
AD17 MA[8]
AF18 MA[9]
AE19 MA[10]
AF19 MA[11]
AD18 RAS#[0]
AE20 RAS#[1]
AC19 RAS#[2]
AF20 RAS#[3]
AE21 CAS#[0]
AC20 CAS#[1]
AF21 CAS#[2]
AD20 CAS#[3]
AE22 CAS#[4]
AF22 CAS#[5]
AD21 CAS#[6]
AE23 CAS#[7]
AC22 MWE#
AF23 MD[0]
AE24 MD[1]
AF24 MD[2]
AD25 MD[3]
AC25 MD[4]
AC26 MD[5]
AB24 MD[6]
AA25 MD[7]
AA24 MD[8]
Y25 MD[9]
Y24 MD[10]
V23 MD[11]
W24 MD[12]
V26 MD[13]
V24 MD[14]
U23 MD[15]
U24 MD[16]
R26 MD[17]
P25 MD[18]
P26 MD[19]
N25 MD[20]
N26 MD[21]
M25 MD[22]
M26 MD[23]
M24 MD[24]
M23 MD[25]
L24 MD[26]
J25 MD[27]
J26 MD[28]
H26 MD[29]
G25 MD[30]
G26 MD[31]
AD22 MD[32]
AD23 MD[33]
AE26 MD[34]
AD26 MD[35]
AC24 MD[36]
AB25 MD[37]
AB26 MD[38]
Y23 MD[39]
AA26 MD[40]
Y26 MD[41]
W25 MD[42]
W26 MD[43]
V25 MD[44]
U25 MD[45]
U26 MD[46]
T25 MD[47]
R25 MD[48]
T24 MD[49]
R23 MD[50]
R24 MD[51]
N23 MD[52]
P24 MD[53]
N24 MD[54]
L25 MD[55]
L26 MD[56]
K25 MD[57]
K26 MD[58]
K24 MD[59]
H25 MD[60]
J24 MD[61]
H23 MD[62]
H24 MD[63]
F24 PCI_CLKI
Pin# Pin nameD25 PCI_CLKO
A20 AD[0]
C20 AD[1]
B19 AD[2]
A19 AD[3]
C19 AD[4]
B18 AD[5]
A18 AD[6]
B17 AD[7]
C18 AD[8]
A17 AD[9]
D17 AD[10]
B16 AD[11]
C17 AD[12]
B15 AD[13]
A15 AD[14]
C16 AD[15]
D15 AD[16]
A14 AD[17]
C15 AD[18]
B13 AD[19]
D13 AD[20]
A13 AD[21]
C14 AD[22]
C13 AD[23]
A12 AD[24]
B11 AD[25]
C12 AD[26]
A11 AD[27]
D12 AD[28]
B10 AD[29]
C11 AD[30]
A10 AD[31]
D10 CBE[0]
C10 CBE[1] CBE[2] CBE[3] FRAME# TRDY# IRDY# STOP# DEVSEL# PAR SERR# LOCK#
C21 PCI_REQ#[0]
A21 PCI_REQ#[1]
B20 PCI_REQ#[2]
C22 PCI_GNT#[0]
Pin# Pin name
PIN DESCRIPTION22/51
B21 PCI_GNT#[1]
D20 PCI_GNT#[2] PCI_INT[0] PCI_INT[1] PCI_INT[2] PCI_INT[3] LA[17]/DA[0] LA[18]/DA[1] LA[19]/DA[2] LA[20]/PCS1# LA[21]/PCS3# LA[22]/SCS1# LA[23]/SCS3# SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8]/DD[0] SA[9]/DD[1] SA[10]/DD[2] SA[11]/DD[3] SA[12]/ DD[4] SA[13]/ DD[5] SA[14]/ DD[6] SA[15]/ DD[7] SA[16]/ DD[8] SA[17]/ DD[9] SA[18]/ DD[10] SA[19]/ DD[11] RTCDS/ DD[12] RTCRW#/ DD[13] KBCS#/ DD[14] RMRTCCS#/ DD[15] SD[0] SD[1] SD[2] SD[3] SD[4] SD[5] SD[6] SD[7] SD[8] SD[9] SD[10]
Pin# Pin name SD[11] SD[12] SD[13] SD[14] SD[15] IOCHRDY
AE4 SYSRSTO#
AD4 ISA_CLK
AE5 ISA_CLK2X
AF8 OSC14M ALE
AC9 ZWS#
AA2 BHE# MEMR#
AA1 MEMW# SMEMR#
AB2 SMEMW#/COL_CMP
AA3 IOR#
AC2 IOW#
AB4 MASTER#
AC1 MCS16#
AB3 IOCS16#
AD2 REF#
AC3 AEN
AD1 IOCHCK#
AF2 ISAOE# RTCAS#
AE3 GPIOCS# PIRQ SIRQ PDRQ SDRQ PDACK# SDACK# PIOR# PIOW# SIOR# SIOW#
E23 IRQ_MUX[0]
D26 IRQ_MUX[1]
E24 IRQ_MUX[2]
C25 IRQ_MUX[3]
A24 DREQ_MUX[0]
B23 DREQ_MUX[1]
C23 DACK_ENC[0]
Pin# Pin nameA23 DACK_ENC[1]
B22 DACK_ENC[2]
D22 TC SPKRD
AE6 RED
AD6 GREEN
AF6 BLUE
AD5 VSYNC
AC5 HSYNC
AD7 VREF_DAC
AE8 RSET
AF5 COMP SDA/ DDC[0] SCL/ DDC[1]
AC12 VCLK
AE13 VIN[0]
AD14 VIN[1]
AD12 VIN[2]
AE14 VIN[3]
AC14 VIN[4]
AF14 VIN[5]
AD13 VIN[6]
AE15 VIN[7]
AF10 RED_TV
AC10 GREEN_TV
AF11 BLUE_TV
AE10 VCS
AD9 ODD_EVEN
AD11 CVBS
AD8 IREF1_TV
AE9 VREF1_TV
AE11 IREF2_TV
AD10 VREF2_TV SCAN_ENABLE
AF12 VDDA_TV
AC7 VDD_DAC1
AF4 VDD_DAC2
AD19 VDD_GCLK_PLL
AF13 VDD_DCLK_PLL
F26 VDD_HCLK_PLL
G24 VDD_DEVCLK_PLL
A16 VDD5
B12 VDD5 VDD5
Pin# Pin name
PIN DESCRIPTION23/51
D18 VDD5
A22 VDD
B14 VDD VDD VDD
D11 VDD
D16 VDD
D21 VDD VDD
F23 VDD VDD
K23 VDD VDD
L23 VDD VDD VDD
T23 VDD
T26 VDD VDD
AA4 VDD
AA23 VDD
AB1 VDD
AB23 VDD
AC6 VDD
AC11 VDD
AC16 VDD
AC21 VDD
AE12 VSSA_TV
AE7 VSS_DAC1
AF7 VSS_DAC2
E25 VSS_DLL
E26 VSS_DLL
A1:2 VSS
A26 VSS VSS
B25:26 VSS VSS
C24 VSS VSS VSS
D14 VSS
D19 VSS
D23 VSS VSS
J23 VSS
L11:16 VSS
M11:16 VSS VSS
Pin# Pin nameN11:16 VSS
P11:16 VSS
P23 VSS
R11:16 VSS
T11:16 VSS VSS
W23 VSS
AC4 VSS
AC8 VSS
AC13 VSS
AC18 VSS
AC23 VSS
AD3 VSS
AD24 VSS
AE1:2 VSS
AE16 VSS
AE25 VSS
AF1 VSS
AF25 VSS
AF26 VSS
C26 RESERVED
D24 RESERVED
B24 RESERVED
A25 RESERVED
Pin# Pin name
PIN DESCRIPTION24/51
Update History for Pin Description chapter25/51
2.4 Update History for Pin Description chapterThe following changes have been madeto the Pin Description Chapteron 08/02/2000
The following changes have been madeto the Pin Description Chapteron 13/01/2000
Section Change Text
2.2 Added Color Compare Signal
Section Change Text
2.2 Added “toa minimumof 8MHz”
Update History for Pin Description chapter26/51
