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STMPE812ABJR
Touchscreen controller S-Touch with PWM and dedicated RESET pin
July 2011 Doc ID 18225 Rev 4 1/53
STMPE812A ouchscreen controller S-Touch®
with PWM and dedicated RESET pin
Features Integrated 4-wire resistive touchscreen
controller, pen-down/real-time mode, fully-
autonomous 12-bit ADC for high-resolution touchscreen Operating voltage 1.65- 3.6V Low power consumption: Hibernation mode: 0.5 µA Active mode: 100µA Auto-hibernation and hotkey wake-up features Up to 3 GPIOs with alternate functions 1 PWM controller 1 general purpose 12-bit ADC input Optional interrupt output pin Dedicated reset input pin 400 kHz I2 C interface8 kV HBM, 1 kV CDM ESD protection on
X+/X-/Y+/Y-2 kV HBM, 250 V CDM ESD protection on all
other pins
Applications Portable media players Game consoles Mobile and smart phones
DescriptionThe STMPE812A is a 4-wire resistive
touchscreen controller with 4-bit port expander
integrated.
The touchscreen controller is designed to be fully
autonomous, requiring only minimal CPU
intervention for sampling, filtering and pre-
processing operations.
Table 1. Device summary
Contents STMPE812A2/53 Doc ID 18225 Rev 4
Contents STMPE812A functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1 Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 T ypical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STMPE812A registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176.1 Auto-increment/non auto-increment address . . . . . . . . . . . . . . . . . . . . . . 18
System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ADC controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2810.1 Register map for PWM function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.2 Interrupt of PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3111.1 T ouchscreen controller detection sequence . . . . . . . . . . . . . . . . . . . . . . . 32
11.2 3 modes of acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11.3 T ouchscreen controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.4 Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STMPE812A ContentsDoc ID 18225 Rev 4 3/53
GPIO port controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4213.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.2 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Package mechanical section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STMPE812A functional overview STMPE812A
4/53 Doc ID 18225 Rev 4 STMPE812A functional overview
The STMPE812A consists of the following blocks: I2 C interface GPIO/PWM controller Touchscreen controller (TSC) Analog-to-digital converted (ADC) Driver and switch control unit
Figure 1. STMPE812A block diagram
STMPE812A STMPE812A functional overview
Doc ID 18225 Rev 4 5/53
1.1 Pin configuration and functions
Figure 2. Pin configuration (top through view)
Table 2. Pin assignments
STMPE812A functional overview STMPE812A
6/53 Doc ID 18225 Rev 4
Note: All I/O operates on VCC. All I/O tolerant up to 3.6V , across VCC = 1.65- 3.6V kV HBM ESD on all touchscreen pins (+/- 8 kV vs GND)
0.5 µA max input leakage as input, across VCC range (GPIO, SCL/SDA) µs hardware filter on the 3 GPIOs as input
Table 2. Pin assignments (continued)
STMPE812A STMPE812A functional overview
Doc ID 18225 Rev 4 7/53
1.2 Typical application
Figure 3. Typical application
I2C interface STMPE812A
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2 I2 C interface
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
address, there is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from
the bus by not responding to the transaction.
Figure 4. I2 C timing diagram
Table 3. I2 C timing Minimum TF is subject to system capacitive load (CLOAD) condition.
STMPE812A I2C interface
Doc ID 18225 Rev 4 9/53
2.1 I2 C features
The features that are supported by the I2 C interface are listed below: I2 C slave device Operates at VCC (1.65 V - 3.6 V) Compliant to Philips I2 C specification version 2.1 Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes I2 C address in 0x41 (0x82/83 including Rd/Wr bit) or 0x40 (0x80/81 including Rd/Wr
bit)
The slave address is selected by the state of P0 pin. The state of the pin is read upon reset
and then the pin can be configured for normal operation. The pin shall have an external pull-
up or pull-down to set the address.
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDA TA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I2 C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
2.2 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Table 4. Slave address
I2C interface STMPE812A
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Table 5. Operating modes
STMPE812A I2C interface
Doc ID 18225 Rev 4 11/53
Figure 5. Read and write modes (random and sequential)
I2C interface STMPE812A
12/53 Doc ID 18225 Rev 4
2.3 Read operation
A write is first performed to load the register address into the Address Counter but without
sending a Stop condition. Then, the bus master sends a reStart condition and repeats the
Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the
content of the addressed byte. If no additional data is to be read, the bus master must not
acknowledge the byte and terminates the transfer with a Stop condition.
If the bus master acknowledges the data byte, then it can continue to perform the data
reading. To terminate the stream of data bytes, the bus master must not acknowledge the
last output byte, and be followed by a Stop condition. If the address of the register written
into the Address Counter falls within the range of addresses that has the auto-increment
function, the data being read is coming from consecutive addresses, which the internal
Address Counter automatically increments after each byte output. After the last memory
address, the Address Counter 'rolls-over' and the device continues to output data from the
memory address of 0x00. Similarly, for the register address that falls within a non-increment
range of addresses, the output data byte comes from the same address (which is the
address referred by the Address Counter).
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an
acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a
low state, then the slave device terminates and switches back to its idle mode, waiting for
the next command.
2.4 Write operations
A write is first performed to load the register address into the Address Counter without
sending a Stop condition. After the bus master receives an acknowledgement from the slave
device, it may start to send a data byte to the register (referred by the Address Counter).
The slave device again acknowledges and the bus master terminates the transfer with a
Stop condition.
If the bus master needs to write more data, it can continue the write operation without
issuing the Stop condition. Whether the Address Counter autoincrements or not after each
data byte write depends on the address of the register written into the Address Counter.
After the bus master writes the last data byte and the slave device acknowledges the receipt
of the last data, the bus master may terminate the write operation by sending a Stop
condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the
next data byte write.
STMPE812A Power supply
Doc ID 18225 Rev 4 13/53
3 Power supply
The STMPE812A GPIO operates from a supply pin VCC. For better resolution and noise
immunity, VCC above 2.8 V is recommended.
Power up reset
The STMPE812A is equipped with an internal POR circuit that holds the device in reset
state, until the VCC supply input is valid. The internal POR is tied to the VCC supply pin.
Charge pump STMPE812A
14/53 Doc ID 18225 Rev 4
4 Charge pump
The STMPE812A is integrated with an internal charge-pump. The charge pump is required
for any ADC/TSC operations when VCC is less than 2.5V.
Activating the charge pump when VCC > 2.5 V may result in permanent damage of the
device.
STMPE812A Power modes
Doc ID 18225 Rev 4 15/53
5 Power modes
The STMPE812A operates in a 2 states: active and hibernate.
Active: Whenever PEN-DOWN is detected, the device remains in active mode Whenever PWM is active, the device remains in active mode Whenever ADC is active, the device remains in ACTIVE MODE
Hibernate:
-PWM/ADC must be “off” (clock disable bit SET)
-Any GPIO input, with interrupt enabled, causes a transition to “active” state, if an input
change is detected.
-Pen down even causes transition to “active” state if the touchscreen controller is enabled.
Table 6. Power mode At Vcc=1.8V, TCS running at 100sets of X/Y per second, MAV disabled.
Power modes STMPE812A
16/53 Doc ID 18225 Rev 4
Figure 6. Power modes state diagram
On power up reset, device goes to active state. However, as all the functional blocks are
clocked off by default, no touch/hotkey activity is possible. If there are no I2 C activities,
device goes into auto-hibernate mode automatically.
The auto-hibernate feature of STMPE812A is always enabled. Whenever there is a period of
inactivity, the device enters this mode to reduce power consumption. On detection a touch,
correctly addressed I2 C data, GPIO activity, the device wakes up immediately.
As the device is able to wake up very quickly, there is no loss of touch data.
STMPE812A STMPE812A registers
Doc ID 18225 Rev 4 17/53
6 STMPE812A registers
This section lists and describes the registers of the STMPE812A device, starting with a
register map and then provides detailed descriptions of register types.
Table 7. Register summary map table
STMPE812A registers STMPE812A
18/53 Doc ID 18225 Rev 4
6.1 Auto-increment/non auto-increment address
The STMPE812A supports auto-increment accesses on all, except for TSC data register
(0x44). While accessing auto-increment register location, consecutive read/write access
data from the consecutive registers. Note that for register accesses started on auto-
incremental addresses, the address 0x44 is skipped.
For example:
Write register address (0x40)
Read data (data of 0x40)
Read data (data of 0x41)
Read data (data of 0x42)
Read data (data of 0x43)
Read data (data of 0x45) <= 0x44 is skipped.
Table 7. Register summary map table (continued)
STMPE812A System and identification registers
Doc ID 18225 Rev 4 19/53 System and identification registers
SYS_CTRL System control register
Address: 0x03
Type: R/W
Reset: 0x0F
Description: System control register.
If the clock supply to a particular functional block is turned off, the registers of these
modules are not accessible.
Table 8. System and identification registers map 5 4 3 2 1 0
[7] RESERVED
[6] SOFT_RESET
Reset the 812 using serial communication
ALL REGISTER VALUES ARE RESET. State machines all back to POR states.
[5] TSC_EN
Write ‘1’ to enable operation of TSC. Write ‘0’ to disable it.
[4] RESERVED
[3] PWM_OFF
Writing ‘1’ switches OFF the clock supply to PWM
[2] GPIO_OFF
Writing ‘1’ switches OFF the clock supply to GPIO
[1] TSC_OFF
Writing ‘1’ switches OFF the clock supply to touchscreen controller
[0] ADC_OFF
Writing ‘1’ switches OFF the clock supply to ADC
System and identification registers STMPE812A
20/53 Doc ID 18225 Rev 4
PORT_FUNCTION Port function control register
Address: 0x04
Type: R/W
Reset: 0xF8
Description: Port function control register.
Port function:
'00' - GPIO input
'01' - GPIO output
'10' - ADC input (P1 only)
'11' - Special function
Special function for:
P0 - NONE
P1 - PWM
P2 - INT output
SCRATCH_PAD Scratch pad register
Address: 0x06 - 07
Type: R/W
Reset: 0x00
Description: General purpose scratch pad register. Could be used for testing of serial interface
reliability.
7654 3 2 1 0
[7:6] PORT 2 FUNCTION
[5:4] RESERVED
[3:2] PORT 1 FUNCTION
[1:0] PORT 0 FUNCTION
7654 3 2 1 0
[15:0] SCRATCHPAD
STMPE812A Interrupt system
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8 Interrupt system
The STMPE812A uses a 2-tier interrupt structure. In normal mode, interrupts from the GPIO
and touchscreen controller assert the INT pin and are available in the Interrupt Status
register (ISR).
In pen down mode, the INT pin is asserted as long as pen down is detected.
Since the INT pin is a OR function of the pen down and all other enabled interrupts, in order
for INT pin to provide the exclusive indication of pen down (INT= Low) and pen up
(INT= High), as such benefit from minimal I2 C transactions, it is recommended to use pen
down mode when the GPIO/PWM/ADC functions are not required or the GPIO/PWM/ADC
interrupts are disabled.
Figure 7. Interrupt system diagram
Interrupt system STMPE812A
22/53 Doc ID 18225 Rev 4
INT_CTRL Interrupt control register
Address: 0x08
Type: R/W
Reset: 0x00
Description: This register is used to enable the interruption from a system related interrupt source
to the host.
7654 3 2 1 0
[7] INT_MODE:
‘0’ for Pen-Down INT mode (INT pin asserted as long as pen down detected). Nothing can de-
assert the INT pin as long as PEN is down. TSC_TOUCH in INT_EN register must be enabled
for PEN_DOWN interrupt to operate.
If any other interrupt sources are enabled, the INT output is:
PEN_STA TUS OR OTHER_INT
INT_E setting is not required for PEN-DOWN mode. It is recommended Pen-Down INT mode
enabled in applications where GPIO/ADC/PWM functions or interrupts are not in used, such
that the INT pin signal provides the exclusive indication for pen down and pen up.
‘1’ for normal INT mode (INT pin asserted if any bit in INT STATUS REGISTER is set)
When INT_MODE is changed, all interrupt status are cleared. Pending INT output (if any) is
cleared too.
[6:3] RESERVED
[2] INT_ POLARITY:
‘1’ for active high/rising edge
‘0’ for active low/falling edge
Interrupt pin should be pulled to VCC if “active low” polarity is used, and pulled to GND if “active
high” polarity is used.
[1] INT_TYPE:
‘1’ for edge interrupt (pulse width = 50-150 µs)
‘0’ for level interrupt
Edge interrupt does not work in PEN_DOWN INT mode
This bit is ignored in PEN_DOWN INT mode.
[0] GLOBAL_INT:
‘1’ allows global interrupt
‘0’ stops all interrupt
This bit overwrites INT_MODE: If global_int is stop (in pen down INT_MODE), even pen down
does not generate an interrupt.
STMPE812A Interrupt system
Doc ID 18225 Rev 4 23/53
INT_EN Interrupt enable register
Address: 0x09
Type: R/W
Reset: 0x00
Description: This register is used to enable the interruption from a system related interrupt source
to the host.
Note: * Hotkey interrupt should have respond time of <5 µs in active mode and less than 1 ms in
hibernate mode. 6 543 2 1 0
[7] TSC_ERR
Error encountered in coordinate calculation in touchscreen controller
[6] TSC_RELEASE:
Release of TSC is detected
[5] P2:
Port 2 activity (GPIO)
[4] RESERVED
[3] P1
Port 1 activity (GPIO/ADC/PWM)
[2] P0
Port 0 activity (GPIO)
[1] TSC_DATA
Touch data available
[0] TSC_TOUCH
Touch is detected
Interrupt system STMPE812A
24/53 Doc ID 18225 Rev 4
ISR Interrupt status register
Address: 0x0A
Type: R
Reset: 0x00
Description: ISR register monitors the status of the interruption from a particular interrupt source
to the host. Regardless whether the INT_EN bits are enabled, the ISR bits are still
updated.
Writing to this register has no effect. Reading the register clears any asserted bit
Implementation: A shadow register MUST be used to ensure that Read+Clear action
DOES NOT clear up any bit that is not READ.
Note: Reading the Interrupt Enable Register also clears the ISR. It is recommended that no read operation on IER
to be executed during normal operation. IER should only be accessed during initialization.
In PEN_DOWN interrupt mode, this status register will still be updated with event interrupt
status data, and cleared on read. However no interrupt will be issued based on this status
register. 6 543 2 1 0
[7] TSC_ERR
Error encountered in coordinate calculation in TSC, or touch detect not valid after sampling
[6] TSC_RELEASE:
Release of touch is detected
[5] P2
Port 2 activity (GPIO)
[4] RESERVED
[3] P1
Port 1 activity (GPIO/ADC/PWM)
[2] P0
Port 0 activity (GPIO)
[1] TSC_DATA
Touch data available. In internal timer and host-read controlled mode, this bit can only
be cleared after the data has been read by the host. In ACQ mode, this bit is cleared after the
data or the ISR is read by the host.
[0] TSC_TOUCH
Touch is detected.
(In PEN-DOWN interrupt mode, this bit is never cleared until pen is removed)
STMPE812A ADC controller
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9 ADC controller
A 12-bit ADC is integrated in the STMPE812A. The ADC could be used as generic analog-
digital converter, or a touchscreen controller capable of controlling a 4-wire resistive
touchscreen.
The ADC works ONL Y with internal reference (equal to VCC), always 12 bit.
Table 9. ADC controller registers
ADC controller STMPE812A
26/53 Doc ID 18225 Rev 4
ADC control register ADC control
Address: 0x20
Type: R/W
Reset: 0x33
Description: This register is used to configure the ADC operations.
7654 3 2 1 0
[7] ADC_MODE: ADC capture mode
‘0’ – Continuous capture according to sampling rate specified by ADC_FREQ register. New
data over-writes old data in ADC_DATA register.
‘1’ – One-shot capture. One sample is taken every time system writes ‘1’ to ADC_CAP bit
[6] ADC_CAP: ADC channel data capture
In one-shot mode:
Write ‘1’ to initiate data acquisition for the corresponding channel. Writing ‘0’ has no effect.
Reads ‘1’ if conversion is in progress.Reads ‘0’ if conversion is completed.
One-shot mode ADC generates interrupt in corresponding interrupt status bit on completion of
conversion
In continuous capture mode:
Write ‘1’ to initiate data acquisition for the corresponding channel. Writing ‘0’ to stop capturing.
[5:4] ADC_FREQ: ADC sampling frequency based on 1MHz RC (minimum 880 KHz)
00 – 10 K samples/sec
01 – 12.5K samples/sec
10 – 15K samples/sec
11 – 20K samples/sec
NOTE: As the ADC is also used for TSC operation. This setting affects the maximum sampling
rate possible with TSC.
[3] CP_Arm: Writing ‘1’ arms the charge-pump for unlocking
Writing ‘0’ un-arms it
Charge-pump is required for ADC/TSC operation when VCC is less than 2.5 V. Activating the
charge pump when VCC is more than 2.5 V may result in permanent damage of the
device.
Charge-pump can be activated by unlocking CP_Lock after it is armed.
[2:1] CP_Lock[1:0]: Only effective if CP_Arm is set to ‘1’.
Always reads ‘00’.
Writing ‘01’ when CP_Arm is ‘1’ activates the charge pump.
Writing ‘00’, ‘10’ and ‘11’ does NOT activate the charge-pump, and clears the CP_Arm bit.
CP_Arm MUST BE set before writing to CP_Lock. Accesses to CP_Lock will be ignored, if
CP_Arm is ‘0’.
Note: CP_Arm and CP_Lock CANNOT be accessed in a single I2 C transaction. System must
first ARM the CP with 1 I2 C transaction, and unlocks it in the next. CP_LOCK reads “00”
if charge pump is activated
CP_LOCK reads “01” if charge pump is not activated
[0] RESERVED
STMPE812A ADC controller
Doc ID 18225 Rev 4 27/53
ADC data ADC data register
Address: 0x21-0x22
Type: R
Reset: 0x0000
Address: ADC data register.
Note: When the I2 C master accesses the data register, upper/lower byte consistency must be
guaranteed (once access starts, content will only be updated after BOTH bytes has been
read, OR I2 C master accesses other register address):
- 0x21 is LSB
- 0x22 is MSB
7654 3 2 1 0
[7:0] ADC_DATAx
