IC Phoenix
 
Home ›  SS106 > STM690RM6E-STM690RM6F-STM690SM6E-STM690SM6F-STM690TM6E-STM690TM6F-STM704M6E-STM704M6F-STM704RM6E-STM704RM6F-STM704SM6E-STM704SM6F-STM704TM6F-STM795RM6E-STM795RM6F-STM795SM6E-STM795SM6F-STM795TM6E-STM795TM6F-STM802RM6E-STM802RM6F-STM802SM6E-STM802SM6F-ST,3V Supervisor with Battery Switchover
STM690RM6E-STM690RM6F-STM690SM6E-STM690SM6F-STM690TM6E Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
STM704M6ESTN/a5200avai3V Supervisor with Battery Switchover
STM704M6FSTN/a5200avai3V Supervisor with Battery Switchover
STM704RM6ESTN/a6000avai3V Supervisor with Battery Switchover
STM704RM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM704SM6ESTN/a6000avai3V Supervisor with Battery Switchover
STM704SM6FSTMN/a1800avai3V Supervisor with Battery Switchover
STM704TM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM802TM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM690RM6ESTN/a2500avai3V Supervisor with Battery Switchover
STM690RM6FSTN/a2500avai3V Supervisor with Battery Switchover
STM690SM6ESTN/a390avai3V Supervisor with Battery Switchover
STM690SM6FSTN/a2500avai3V Supervisor with Battery Switchover
STM690TM6ESTN/a2500avai3V Supervisor with Battery Switchover
STM690TM6FSTN/a2500avai3V Supervisor with Battery Switchover
STM795RM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM795RM6FSTN/a5200avai3V Supervisor with Battery Switchover
STM795SM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM795SM6FSTN/a5200avai3V Supervisor with Battery Switchover
STM795TM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM795TM6FSTN/a5200avai3V Supervisor with Battery Switchover
STM802RM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM802RM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM802SM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM802SM6FSTN/a5544avai3V Supervisor with Battery Switchover
STM802TM6ESTN/a6000avai3V Supervisor with Battery Switchover
STM804RM6ESTN/a5544avai3V Supervisor with Battery Switchover
STM804RM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM804SM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM804SM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM804TM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM804TM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM805RM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM805RM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM805SM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM805SM6FSTN/a5200avai3V Supervisor with Battery Switchover
STM805TM6ESTN/a6000avai3V Supervisor with Battery Switchover
STM805TM6FSTN/a5512avai3V Supervisor with Battery Switchover
STM806RM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM806RM6FSTN/a6000avai3V Supervisor with Battery Switchover
STM806SM6ESTN/a5200avai3V Supervisor with Battery Switchover
STM806SM6FSTN/a5200avai3V Supervisor with Battery Switchover
STM806TM6ESTN/a6000avai3V Supervisor with Battery Switchover
STM806TM6FSTN/a5533avai3V Supervisor with Battery Switchover


STM806TM6E ,3V Supervisor with Battery SwitchoverFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1Table 1. Device Options ..
STM806TM6F ,3V Supervisor with Battery SwitchoverBlock Diagram (STM795) . 8Figure 11.Hardware Hookup . . . . . . . 8OPERATION . ..
STM809LWX6F ,320mW; I(o): 20mA; V(cc): -0.3 to +7.0V; reset circuitLogic Diagram (STM809/810) Table 2. Signal NamesVGroundV SSCCRST Active-Low RESET Output(1)Active-H ..
STM809MWX6F ,RESET CIRCUITLogic Diagram (STM811/812)V(For STM810)CCAI07833Figure 5. SOT143-4 Connections(1)MR STM811/812 RST ..
STM809RWX6F ,320mW; I(o): 20mA; V(cc): -0.3 to +7.0V; reset circuitAbsolute Maximum Ratings . . . . . . . 10DC and AC PARAMETERS . 11Table 4. Operating and ..
STM809SWX6F ,320mW; I(o): 20mA; V(cc): -0.3 to +7.0V; reset circuitSTM809, STM810STM811, STM812Reset Circuit
SY58607UMG , 3.2Gbps Precision, 1:2 LVPECL Fanout Buffer with Internal Termination and Fail Safe Input
SY58608UMGTR , 3.2Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input
SY58610UMG , 3.2Gbps Precision, LVPECL 2:1 MUX with
SY58610UMG , 3.2Gbps Precision, LVPECL 2:1 MUX with
SY58611UMG , 3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input
SY58620LMG , Precision 4.25Gbps CML Backplane Transceiver with Integrated Loopback


STM690RM6E-STM690RM6F-STM690SM6E-STM690SM6F-STM690TM6E-STM690TM6F-STM704M6E-STM704M6F-STM704RM6E-STM704RM6F-STM704SM6E-STM704SM6F-STM704TM6F-STM795RM6E-STM795RM6F-STM795SM6E-STM795SM6F-STM795TM6E-STM795TM6F-STM802RM6E-STM802RM6F-STM802SM6E-STM802SM6F-ST
3V Supervisor with Battery Switchover
1/32February 2005
STM690, STM704, STM795
STM802, STM804, STM805, STM806

3V Supervisor with Battery Switchover
* Contact local ST sales office for availability.
FEATURES SUMMARY
RST OR RST OUTPUTS NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM CHIP-ENABLE GATING (STM795 only) FOR
EXTERNAL LPSRAM (7ns max PROP
DELAY) MANUAL (PUSH-BUTTON) RESET INPUT 200ms (TYP) trec WATCHDOG TIMER - 1.6sec (TYP) AUTOMATIC BATTERY SWITCHOVER LOW BATTERY SUPPLY CURRENT - 0.4µA
(TYP) POWER-FAIL COMPARATOR (PFI/PFO) LOW SUPPLY CURRENT - 40µA (TYP) GUARANTEED RST (RST) ASSERTION
DOWN TO VCC = 1.0V OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
Table 1. Device Options

Note:1. All RST outputs push-pull (unless otherwise noted) Open drain output.
STM690/704/795/802/804/805/806
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 2. Logic Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. Logic Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Logic Diagram (STM795). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 5. STM690/802/804/805 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. STM704/806 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 7. STM795 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 8. Block Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Block Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 10.Block Diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Push-button Reset Input (STM704/806). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Watchdog Input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Chip-Enable Gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable Input (STM795 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable Output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 13.Chip Enable Waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Power-fail Input/Output (NOT available on STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 14.Power-fail Comparator Waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . .11
Using a SuperCap™ as a Backup Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 15.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Negative-Going VCC Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 16.VCC-to-VOUT On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 17.VBAT-to-VOUT On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 18.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 19.Battery Current vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 20.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/32
STM690/704/795/802/804/805/806

Figure 21.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 22.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 23.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 24.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 25.E to ECON On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 26.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 27.Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . .18
Figure 28.Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . .19
Figure 29.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 30.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 31.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 32.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 33.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . .21
Figure 34.E to ECON Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 35.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 36.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 37.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 38.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 39.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . .27
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . .27
Figure 40.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . .28
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . .28
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 11. Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
STM690/704/795/802/804/805/806
SUMMARY DESCRIPTION

The STM690/704/795/802/804/805/806 Supervi-
sors are self-contained devices which provide mi-
croprocessor supervisory functions with the ability
to non-volatize and write-protect external
LPSRAM. A precision voltage reference and com-
parator monitors the VCC input for an out-of-toler-
ance condition. When an invalid VCC condition
occurs, the reset output (RST) is forced low (or
high in the case of RST). These devices also offer
a watchdog timer (except for STM704/795/806) as
well as a power-fail comparator (except for
STM795) to provide the system with an early
warning of impending power failure.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
5/32
STM690/704/795/802/804/805/806
STM690/704/795/802/804/805/806
Pin Descriptions
MR.
A logic low on /MR asserts the reset output.
Reset remains asserted as long as MR is low and
for trec after MR returns high. This active-low input
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI.
If WDI remains high or low for 1.6sec, the in-
ternal watchdog timer runs out and reset is trig-
gered. The internal watchdog timer clears while
reset is asserted or when WDI sees a rising or fall-
ing edge.
The watchdog function cannot be disabled by al-
lowing the WDI pin to float.
RST.
Pulses low for trec when triggered, and stays
low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after
either VCC rises above the reset threshold, the
watchdog triggers a reset, or MR goes from low to
high.
RST (Open Drain).
Pulses high for trec when trig-
gered, and stays high whenever VCC is above the
reset threshold or when MR is a logic high. It re-
mains high for trec after either VCC falls below the
reset threshold, the watchdog triggers a reset, or
MR goes from high to low.
PFI.
When PFI is less than VPFI or when VCC falls
below VSW (2.4V), PFO goes low; otherwise, PFO
remains high. Connect to ground if unused.
PFO.
When PFI is less than VPFI, or VCC falls be-
low VSW, PFO goes low; otherwise, PFO remains
high. Leave open if unused.
VOUT.
When VCC is above the switchover voltage
(VSO), VOUT is connected to VCC through a P-
channel MOSFET switch. When VCC falls below
VSO, VBAT connects to VOUT. Connect to VCC if no
battery is used.
Vccsw.
When VOUT switches to battery, Vccsw is
high. When VOUT switches back to VCC, Vccsw is
low. It can be used to drive gate of external PMOS
transistor for IOUT requirements exceeding 75mA. The input to the chip-enable gating circuit. Con-
nect to ground if unused.
ECON.
ECON goes low only when E is low and re-
set is not asserted. If ECON is low when reset is as-
serted, ECON will remain low for 15µs or until E
goes high, whichever occurs first. In the disabled
mode, ECON is pulled up to VOUT.
VBAT.
When VCC falls below VSO, VOUT switches
from VCC to VBAT. When VCC rises above VSO +
hysteresis, VOUT reconnects to VCC. VBAT may ex-
ceed VCC. Connect to VCC if no battery is used.
Table 3. Pin Description
7/32
STM690/704/795/802/804/805/806
Figure 8. Block Diagram (STM690/802/804/805)

Note:1. For STM804/805, reset output is active-high and open drain.
Figure 9. Block Diagram (STM704/806)
STM690/704/795/802/804/805/806
Figure 10. Block Diagram (STM795)
Figure 11. Hardware Hookup

Note:1. For STM690/802/804/805. For STM795 only. Not available on STM795. For STM704/806.
9/32
STM690/704/795/802/804/805/806
OPERATION
Reset Output

The STM690/704/795/802/804/805/806 Supervi-
sor asserts a reset signal to the MCU whenever
VCC goes below the reset threshold (VRST), a
watchdog time-out occurs, or when the Push-but-
ton Reset Input (MR) is taken low. RST is guaran-
teed to be a logic low (logic high for STM804/805)
for 0V < VCC < VRST if VBAT is greater than 1V.
Without a back-up battery, RST is guaranteed val-
id down to VCC =1V.
During power-up, once VCC exceeds the reset
threshold an internal timer keeps RST low for the
reset time-out period, trec. After this interval RST
returns high.
If VCC drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period (trec). Any time VCC
goes below the reset threshold the internal timer
clears. The reset timer starts when VCC returns
above the reset threshold.
Push-button Reset Input (STM704/806)

A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for trec (see Figure
37., page 24) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
VCC when not used.
Watchdog Input (NOT available on STM704/
795/806)

The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within tWD (1.6sec typ), the
reset is asserted. The internal watchdog timer is
cleared by either: a reset pulse, or by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (tWD + trec).
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting (see Figure
38., page 24).
Note: Input frequency greater than 20ns (50MHz)

will be filtered.
Back-up Battery Switchover

In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
through VOUT. With a backup battery installed with
voltage VBAT, the devices automatically switch the
SRAM to the back-up supply when VCC falls.
Note: If back-up battery is not used, connect both

VBAT and VOUT to VCC.
This family of Supervisors does not always con-
nect VBAT to VOUT when VBAT is greater than VCC.
VBAT connects to VOUT (through a 100Ω switch)
when VCC is below VSW (2.4V) or VBAT (whichever
is lower). This is done to allow the back-up battery
(e.g., a 3.6V lithium cell) to have a higher voltage
than VCC.
Assuming that VBAT > 2.0V, switchover at VSO en-
sures that battery back-up mode is entered before
VOUT gets too close to the 2.0V minimum required
to reliably retain data in most external SRAMs.
When VCC recovers, hysteresis is used to avoid
oscillation around the VSO point. VOUT is connect-
ed to VCC through a 3Ω PMOS power switch.
Note: The back-up battery may be removed while

VCC is valid, assuming VBAT is adequately decou-
pled (0.1µF typ), without danger of triggering a re-
set.
Table 4. I/O Status in Battery Back-up
STM690/704/795/802/804/805/806
Chip-Enable Gating (STM795 only)

Internal gating of the chip enable (E) signal pre-
vents erroneous data from corrupting the external
CMOS RAM in the event of an undervoltage con-
dition. The STM795 uses a series transmission
gate from E to ECON (see Figure 12). During nor-
mal operation (reset not asserted), the E transmis-
sion gate is enabled and passes all E transitions.
When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting
the CMOS RAM. The short E propagation delay
from E to ECON enables the STM795 to be used
with most µPs. If E is low when reset asserts,
ECON remains low for typically 10µs to permit the
current WRITE cycle to complete.
Chip Enable Input (STM795 only)

The chip-enable transmission gate is disabled and
E is high impedance (disabled mode) while reset
is asserted. During a power-down sequence when
VCC passes the reset threshold, the chip-enable
transmission gate disables and E immediately be-
comes high impedance if the voltage at E is high.
If E is low when reset asserts, the chip-enable
transmission gate will disable 10µs after reset as-
serts (see Figure 13). This permits the current
WRITE cycle to complete during power-down.
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E remains
high impedance (regardless of E activity) for the
first half of the reset time-out period (trec/2). When
the chip enable transmission gate is enabled, the
impedance of E appears as a 40Ω resistor in se-
ries with the load at ECON. The propagation delay
through the chip-enable transmission gate de-
pends on VCC, the source impedance of the drive
connected to E, and the loading on ECON. The chip
enable propagation delay is production tested
from the 50% point on E to the 50% point on ECON
using a 50Ω driver and a 50pF load capacitance
(see Figure 36., page 23). For minimum propaga-
tion delay, minimize the capacitive load at ECON
and use a low-output impedance driver.
Chip Enable Output (STM795 only)

When the chip-enable transmission gate is en-
abled, the impedance of ECON is equivalent to a
40Ω resistor in series with the source driving E. In
the disabled mode, the transmission gate is off
and an active pull-up connects ECON to VOUT (see
Figure 12). This pull-up turns off when the trans-
mission gate is enabled.
11/32
STM690/704/795/802/804/805/806
Power-fail Input/Output (NOT available on STM795)

The Power-fail Input (PFI) is compared to an inter-
nal reference voltage (independent from the VRST
comparator). If PFI is less than the power-fail
threshold (VPFI), the Power-Fail Output (PFO) will
go low. This function is intended for use as an un-
dervoltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 11., page 8) to either
the unregulated DC input (if it is available) or the
regulated output of the VCC regulator. The voltage
divider can be set up such that the voltage at PFI
falls below VPFI several milliseconds before the
regulated VCC input to the STM690/704/795/802/
804/805/806 or the microprocessor drops below
the minimum operating voltage.
During battery back-up, the power-fail comparator
is turned off and PFO goes (or remains) low (see
Figure 14., page 11). This occurs after VCC drops
below VSW (2.4V). When power returns, the pow-
er-fail comparator is enabled and PFO follows PFI.
If the comparator is unused, PFI should be con-
nected to VSS and PFO left unconnected. PFO
may be connected to MR on the STM704/806 so
that a low voltage on PFI will generate a reset out-
put.
Applications Information

These Supervisor circuits are not short-circuit pro-
tected. Shorting VOUT to ground - excluding pow-
er-up transients such as charging a decoupling
capacitor - destroys the device. Decouple both
VCC and VBAT pins to ground by placing 0.1µF ca-
pacitors as close to the device as possible.
STM690/704/795/802/804/805/806
Negative-Going VCC Transients

The STM690/704/795/802/804/805/806 Supervi-
sors are relatively immune to negative-going VCC
transients (glitches). Figure 33., page 21 was gen-
erated using a negative pulse applied to VCC,
starting at VRST + 0.3V and ending below the reset
threshold by the magnitude indicated (comparator
overdrive). The graph indicates the maximum
pulse width a negative VCC transient can have
without causing a reset pulse. As the magnitude of
the transient increases (further below the thresh-
old), the maximum allowable pulse width decreas-
es. Any combination of duration and overdrive
which lies under the curve will NOT generate a re-
set signal. Typically, a VCC transient that goes
100mV below the reset threshold and lasts 40µs or
less will not cause a reset pulse. A 0.1µF bypass
capacitor mounted as close as possible to the VCC
pin provides additional transient immunity.
13/32
STM690/704/795/802/804/805/806
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25°C.
Figure 16. VCC-to-VOUT On-Resistance vs. Temperature
Figure 17. VBAT-to-VOUT On-Resistance vs. Temperature
STM690/704/795/802/804/805/806
15/32
STM690/704/795/802/804/805/806
STM690/704/795/802/804/805/806
Figure 22. Power-up trec vs. Temperature
Figure 23. Normalized Reset Threshold vs. Temperature
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED