STM706PM6E-STM706PM6F-STM706RM6E-STM706RM6F-STM706SM6E-STM706SM6F-STM706TM6E-STM706TM6F-STM708RM6E-STM708RM6F-STM708SM6F-STM708TM6E-STM708TM6F Fast Delivery |IC PHOENIX CO.,LIMITED

STM706SM6F ,3V SupervisorAbsolute Maximum Ratings . . . . . . . 17DC and AC PARAMETERS . 18Table 5. Operating and ..
STM706TAM6F ,3V SupervisorAbsolute maximum ratings . 21Table 5. Operating and AC measurement conditions . . . . 22Ta ..
STM706TM6E ,3V SupervisorFEATURES SUMMARY . . . . . 1Figure 1. Packages . . . . . . 1Table 1. Device Options ..
STM706TM6F ,3V SupervisorBlock Diagram (STM706T/S/R and STM706P) . 7Figure 9.
STM707M6E ,5V SupervisorSTM705, STM706,STM707, STM708, STM813L5V Supervisor
STM707M6F ,5V SupervisorAbsolute Maximum Ratings . . . . . . . 18DC AND AC PARAMETERS . 19Table 5. Operating and ..
SY58029UMG-TR , ULTRA PRECISION DIFFERENTIAL LVPECL 4:1 MUX with 1:2 FANOUT and INTERNAL TERMINATION
SY58030UMG , ULTRA PRECISION, 400mV DIFFERENTIAL LVPECL 4:1 MUX with 1:2 FANOUT and INTERNAL TERMINATION
SY58030UMG , ULTRA PRECISION, 400mV DIFFERENTIAL LVPECL 4:1 MUX with 1:2 FANOUT and INTERNAL TERMINATION
SY58031UMG , ULTRA-PRECISION 1:8 CML fanout buffer WITH INTERNAL I/O TERMINATION
SY58031UMI , ULTRA-PRECISION 1:8 CML FANOUT BUFFER WITH INTERNAL I/O TERMINATION
SY58032U , ULTRRA-PRECISION 1:8 FANOUT BUFFER WITH LVPECL OUTPUTS AND INTERNAL TERMINATION

STM706PM6E-STM706PM6F-STM706RM6E-STM706RM6F-STM706SM6E-STM706SM6F-STM706TM6E-STM706TM6F-STM708RM6E-STM708RM6F-STM708SM6F-STM708TM6E-STM708TM6F
3V Supervisor
1/26February 2005
STM706T/S/R, STM706P, STM708T/S/R
3V Supervisor
FEATURES SUMMARY PRECISION VCC MONITOR STM706/708
T: 3.00V ≤ VRST ≤ 3.15V
S: 2.88V ≤ VRST ≤ 3.00V
R; STM706P: 2.59V ≤ VRST ≤ 2.70V RST AND RST OUTPUTS 200ms (TYP) trec WATCHDOG TIMER - 1.6sec (TYP) MANUAL RESET INPUT (MR) POWER-FAIL COMPARATOR (PFI/PFO) LOW SUPPLY CURRENT - 40µA (TYP) GUARANTEED RST (RST) ASSERTION
DOWN TO VCC = 1.0V OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
Table 1. Device Options
Note:1. Push-Pull Output The STM706P is identical to the STM706R, except its reset output is active-high.
STM706T/S/R; STM706P; STM708T/S/R
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 2. Logic Diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. Logic Diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. STM706T/S/R and STM706P SO8 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. STM706T/S/R and STM706P TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. STM708T/S/R SO8 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 7. STM708T/S/R TSSOP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 8. Block Diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Block Diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 10.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Push-button Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Watchdog Input (STM706T/S/R and STM706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Watchdog Output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Ensuring a Valid Reset Output Down to VCC= 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 11.Reset Output Valid to Ground Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Interfacing to Microprocessors with Bi-directional Reset Pins . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 12.Interfacing to Microprocessors with Bi-directional Reset I/O. . . . . . . . . . . . . . . . . . . . . .10
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 13.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 14.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 15.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 16.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 17.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 18.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 19.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 20.Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . .14
Figure 21.Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . .14
Figure 22.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 23.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 24.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 25.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . .16
3/26
STM706T/S/R; STM706P; STM708T/S/R
Figure 26.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . .17
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 27.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 28.Power-fail Comparator Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 29.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 30.Watchdog Timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 6. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 31.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical. . . . . . .21
Table 7. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . .21
Figure 32.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . .22
Table 8. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . .22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 10. Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
STM706T/S/R; STM706P; STM708T/S/R
SUMMARY DESCRIPTION
The STM70x Supervisors are self-contained de-
vices which provide microprocessor supervisory
functions. A precision voltage reference and com-
parator monitors the VCC input for an out-of-toler-
ance condition. When an invalid VCC condition
occurs, the reset output (RST) is forced low (or
high in the case of RST).
These devices also offer a watchdog timer (except
for STM708T/S/R) as well as a power-fail compar-
ator to provide the system with an early warning of
impending power failure.
The STM706P is identical to the STM706R, except
its reset output is active-high.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
Table 2. Signal Names
Note:1. For STM706P and STM708T/S/R only.
5/26
STM706T/S/R; STM706P; STM708T/S/R
STM706T/S/R; STM706P; STM708T/S/R
Pin Descriptions
MR. A logic low on MR asserts the reset output.
Reset remains asserted as long as MR is low and
for trec after MR returns high. This active-low input
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI. If WDI remains high or low for 1.6sec, the in-
ternal watchdog timer runs out and reset (or WDO)
is triggered. The internal watchdog timer clears
while reset is asserted or when WDI sees a rising
or falling edge.
The watchdog function cannot be disabled by al-
lowing the WDI pin to float.
WDO. WDO goes low when a transition does not
occur on WDI within 1.6sec, and remains low until
a transition occurs on WDI (indicating the watch-
dog interrupt has been serviced). WDO also goes
low when VCC falls below the reset threshold; how-
ever, unlike the reset output, WDO goes high as
soon as VCC exceeds the reset threshold.
Note: For those devices with a WDO output, a
watchdog timeout will not trigger reset unless
WDO is connected to MR.
RST. Pulses low for trec when triggered, and stays
low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after
either VCC rises above the reset threshold, the
watchdog triggers a reset, or MR goes from low to
high.
RST. Pulses high for trec when triggered, and
stays high whenever VCC is above the reset
threshold or when MR is a logic high. It remains
high for trec after either VCC falls below the reset
threshold, the watchdog triggers a reset, or MR
goes from high to low.
PFI. When PFI is less than VPFI, PFO goes low;
otherwise, PFO remains high. Connect to ground
if unused.
PFO. When PFI is less than VPFI, PFO goes low;
otherwise, PFO remains high. Leave open if un-
used.
Table 3. Pin Description
7/26
STM706T/S/R; STM706P; STM708T/S/R
STM706T/S/R; STM706P; STM708T/S/R
Figure 10. Hardware Hookup
Note:1. For STM706T/S/R and STM706P. For STM706P and STM708T/S/R.
9/26
STM706T/S/R; STM706P; STM708T/S/R
OPERATION
Reset Output
The STM70x Supervisor asserts a reset signal to
the MCU whenever VCC goes below the reset
threshold (VRST), a watchdog time-out occurs (if
WDO is connected to MR), or when the Push-but-
ton Reset Input (MR) is taken low. RST is guaran-
teed to be a logic low (logic high for STM706P and
STM708T/S/R) for VCC < VRST down to VCC =1V
for TA = 0°C to 85°C.
During power-up, once VCC exceeds the reset
threshold an internal timer keeps RST low for the
reset time-out period, trec. After this interval RST
returns high.
If VCC drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period (trec). Any time VCC
goes below the reset threshold the internal timer
clears. The reset timer starts when VCC returns
above the reset threshold.
Push-button Reset Input
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for trec (see Figure
29., page 19) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
VCC when not used.
Watchdog Input (STM706T/S/R and STM706P)
The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within tWD (1.6sec), the
Watchdog Output pin (WDO) is asserted. The in-
ternal 1.6sec timer is cleared by either: a reset pulse, or by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns.
See Figure 30., page 19 for STM706T/S/R and
STM706P.
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting.
STM706T/S/R; STM706P; STM708T/S/R
Interfacing to Microprocessors with Bi-
directional Reset Pins
Microprocessors with bi-directional reset pins can
contend with the STM70x reset output. For exam-
ple, if the reset output is driven high and the micro
wants to pull it low, signal contention will result. To
prevent this from occurring, connect a 4.7kΩ resis-
tor between the reset output and the micro’s reset
I/O as in Figure 12.
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25°C.
Figure 13. Supply Current vs. Temperature (no load)
11/26
STM706T/S/R; STM706P; STM708T/S/R
STM706T/S/R; STM706P; STM708T/S/R
13/26
STM706T/S/R; STM706P; STM708T/S/R

Partno	Mfg	Dc	Qty	Available	Descript
STM706PM6E	ST	N/a	5200	avai	3V Supervisor
STM706PM6F	ST	N/a	5200	avai	3V Supervisor
STM706RM6E	ST	N/a	6000	avai	3V Supervisor
STM706RM6F	ST	N/a	6000	avai	3V Supervisor
STM706SM6E	ST	N/a	250	avai	3V Supervisor
STM706SM6F	ST	N/a	6000	avai	3V Supervisor
STM706TM6E	ST	N/a	6000	avai	3V Supervisor
STM706TM6F	ST	N/a	6000	avai	3V Supervisor
STM708RM6E	ST	N/a	6000	avai	3V Supervisor
STM708RM6F	ST	N/a	6000	avai	3V Supervisor
STM708SM6F	ST	N/a	6000	avai	3V Supervisor
STM708TM6E	ST	N/a	6000	avai	3V Supervisor
STM708TM6F	ST	N/a	6000	avai	3V Supervisor