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STM6520AQRRDG9FSTN/a460avaiDual push-button smart reset with push-button controlled output delay


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STM6520AQRRDG9F
Dual push-button smart reset with push-button controlled output delay
January 2011 Doc ID15953 Rev 6 1/23
STM6520

Dual push-button
Smart Reset™ with push-button controlled output delay
Features
Dual Smart Reset™ push-button inputs, with
user-selectable extended reset setup delay
(by two-state input logic): tSRC = 6, 10 s (min.) Push-button controlled reset pulse duration
(no fixed nor minimum pulse width guaranteed) No power-on reset Dual reset outputs
–RST1 - active-low, open-drain RST2 - active-high, push-pull Fixed Smart Reset™ input logic voltage levels Broad operating voltage range 1.65 V to 5.5 V,
inactive reset output levels valid down to 1.0 V Low supply current 1.5 µA Operating temperature: –30 °C to +85 °C TDFN8 package: 2 mm x 2 mm x 0.75 mm RoHS compliant

Applications
Mobile phones, smartphones e-books MP3 players Games Portable navigation devices Any application that requires delayed reset
push-button(s) response for improved system
stability
Contents STM6520
2/23 Doc ID 15953 Rev 6
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Ground (VSS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Smart Reset™ inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 User-selectable Smart Reset™ delay (DSR) . . . . . . . . . . . . . . . . . . . . . . . 7
3.5 Reset outputs (RST1, RST2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM6520 List of tables
Doc ID 15953 Rev 6 3/23
List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data . . . . . . . . . . . . . . . . . 15
Table 6. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 16
Table 7. Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
List of figures STM6520
4/23 Doc ID 15953 Rev 6
List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. RST1 output used for microcontroller reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. RST2 used for interrupting system power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Undervoltage condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Supply current (ICC ) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Smart Reset™ delay (tSRC ) vs. temperature, DSR = VSS . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. TDFN - 8-lead, 2 x 2 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Package marking area, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM6520 Description
Doc ID 15953 Rev 6 5/23
1 Description

The Smart Reset™ devices provide a useful feature that ensures inadvertent short reset
push-button closures do not cause system resets. This is done by implementing extended
Smart Reset™ input delay time (tSRC) and combined push-button inputs, which together
ensures a safe reset and eliminates the need for a specific dedicated reset button.
This reset configuration provides versatility and allows the application to discriminate
between a software generated interrupt and a hard system reset. When the input push-
buttons are connected to microcontroller interrupt inputs, and are closed for a short time, the
processor can only be interrupted. If the system still does not respond properly, continuing
to keep the push-buttons closed for the extended setup time tSRC causes a hard reset of the
processor through the reset outputs.
The STM6520 has two combined delayed Smart Reset™ inputs (SR0, SR1) with two user-
selectable delayed Smart Reset™ setup time (tSRC) options of 7.5 s and 12.5 s typ.,
selected by a dual-state Smart Reset™ DSR input pin. When DSR is connected to ground,
tSRC = 7.5 s, when connected to VCC, tSRC = 12.5 s (typ.). There are two reset outputs, both
going active simultaneously after both of the Smart Reset™ inputs were held active for the
selected tSRC delay time. The outputs remain asserted until either or both inputs go to
inactive logic level (for this device the output reset pulse duration is fully push-button
controlled, meaning neither fixed nor minimum reset pulse width, nor power-on reset pulse
is implemented). The first reset output, RST1, is active-low, open-drain; the second reset
output, RST2, is active-high, push-pull. The device fully operates over a broad VCC range
1.65 to 5.5 V. Below 1.575 V typ. the inputs are ignored and outputs are deasserted; the
deasserted reset output levels are then valid down to 1.0 V.
Figure 1. Logic diagram
Figure 2. Pin connections
Device overview STM6520
6/23 Doc ID 15953 Rev 6
2 Device overview

Table 1. Signal names
STM6520 Pin descriptions
Doc ID 15953 Rev 6 7/23
3 Pin descriptions
3.1 Power supply (VCC)

This pin is used to provide power to the Smart Reset™ device. A 0.1 µF ceramic decoupling
capacitor is recommended to be connected between the VCC and VSS pins, as close to the
STM6520 device as possible.
3.2 Ground (VSS)

This is the ground pin for the device.
3.3 Smart Reset™ inputs (SR0, SR1)

Push-button Smart Reset™ inputs, active-low. Both inputs need to be asserted
simultaneously for at least tSRC to activate the reset outputs.
3.4 User-selectable Smart Reset™ delay (DSR)

An input that allows the user to program the setup time (tSRC) for which both the push-
buttons need to be pressed to activate the reset outputs. Controlled by different voltage
levels on the DSR pin: when connected to ground, tSRC = 7.5 s, when connected to VCC,
tSRC = 12.5 s (typ.). DSR is a DC-type input, intended to be either permanently grounded or
permanently connected to VCC.
3.5 Reset outputs (RST1, RST2)

RST1 is active-low, open-drain, RST2 active-high, push-pull. Neither fixed nor minimum
output reset pulse duration, nor power-on reset is implemented. Releasing any of the push-
buttons while reset outputs are active, causes both outputs to deassert.
Figure 3. Block diagram
Typical application diagram STM6520
8/23 Doc ID 15953 Rev 6 Typical application diagram
Figure 4. RST1 output used for microcontroller reset
DSR pin (pin 5) must be tied to VCC or VSS. When only one Smart Reset™ input is used, connect the unused one permanently to VSS.
Figure 5. RST2 used for interrupting system power
DSR pin (pin 5) must be tied to VCC or VSS. When only one Smart Reset™ input is used, connect the unused one permanently to VSS.
STM6520 Typical application diagram
Doc ID 15953 Rev 6 9/23
Figure 6. Timing waveforms
Figure 7. Undervoltage condition

Note: If undervoltage occurs (VCC drops below 1.575 V typ.) while reset outputs are active, both
outputs are released and go inactive.
Typical operating characteristics STM6520
10/23 Doc ID 15953 Rev 6 Typical operating characteristics
Figure 8. Supply current (ICC ) vs. temperature
Figure 9. Smart Reset™ delay (tSRC) vs. temperature, DSR = VSS
STM6520 Maximum rating
Doc ID 15953 Rev 6 11/23
6 Maximum rating

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 2. Absolute maximum ratings Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. For RST2 –0.3 to VCC +0.3 V only.
DC and AC parameters STM6520
12/23 Doc ID 15953 Rev 6 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics table that
follow, are derived from tests performed under the Measurement Conditions summarized in able 3: Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.

Figure 10. AC testing input/output waveforms
Table 3. Operating and measurement conditions
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