STLC5412FN-STLC5412P Fast Delivery |IC PHOENIX CO.,LIMITED

STLC5412FN ,2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODEFUNCTIONAL DESCRIPTION . . . . 14Digital Interfaces . 14μW/DSI mode . . . 14μW ..
STLC5412FN ,2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODEFEATURESACTIVATION/DEACTIVATION CONTROLLERON CHIP CRC CALCULATION AND VERIFI-CATION INCLUDING TWO P ..
STLC5412P ,2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODEFEATURES160 KBIT/S FULL DUPLEX TRANSCEIVER2B1Q LINE CODING WITH SCRAMBLER/DE-SCRAMBLERSUPPORTS BRID ..
STLC5444B1 , QUAD FEEDER POWER SUPPLY
STLC5445 ,QUAD LINE FEED CONTROLLERSTLC5445QUAD LINE FEED CONTROLLER■ BATTERY VOLTAGE UP TO 120V■ SUPPLIES POWER FOR UP TO FOUR DIGITA ..
STLC5465B ,MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATEDTABLE OF CONTENTS (continued) PageV1 - MEMORY TIMING . . . . . . . . . . . . . . . . ..
SY10EL04ZC , 2-INPUT AND/NAND
SY10EL04ZG , 2-INPUT AND/NAND
SY10EL04ZG , 2-INPUT AND/NAND
SY10EL04ZI , 2-INPUT AND/NAND
SY10EL05ZG , 2-INPUT DIFFERENTIAL AND/NAND
SY10EL07ZC , 2-INPUT XOR/XNOR

STLC5412FN-STLC5412P
2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412
2B1Q U INTERFACE DEVICE
ENHANCED WITH DECT MODE
PRELIMINARY DATA
GENERAL FEATURES
SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER
SUITABLE FOR ISDN, PAIR GAIN AND DECT
APPLICATIONS
MEETS OR EXCEEDS ETSI EUROPEAN
STANDARD
SINGLE 5V SUPPLY
DIP28 AND PLCC44 PACKAGE
HCMOS3A SGS-THOMSON ADVANCED
1.2μm DOUBLE-METAL CMOS PROCESS
ROUND TRIP DELAY MEASUREMENT
EXTENDED TEMPERATURE RANGE (-40°C
TO +70°C)
TRANSMISSION FEATURES
160 KBIT/S FULL DUPLEX TRANSCEIVER
2B1Q LINE CODING WITH SCRAMBLER/DE-
SCRAMBLER
SUPPORTS BRIDGE TAPS, SPLICES AND
MIXED GAUGES
>70DB ADAPTIVE ECHO-CANCELLATION
ON CHIP HYBRID CIRCUIT
DECISION FEEDBACK EQUALIZATION
ON CHIP ANALOG VCO SYSTEM
DIRECT CONNECTION TO SMALL LINE
TRANSFORMER
SYSTEM FEATURES
ACTIVATION/DEACTIVATION CONTROLLER
ON CHIP CRC CALCULATION AND VERIFI-
CATION INCLUDING TWO PROGRAMMA-
BLE BLOCK ERROR COUNTERS
EOC CHANNEL AND OVERHEAD-BITS
TRANSMISSION WITH AUTOMATIC MES-
SAGE CHECKING
GCI AND μW/DSI MODULE INTERFACES
COMPATIBLE
DIGITAL LOOPBACKS
COMPLETE (2B+D) ANALOG LOOPBACK IN LT
ELASTIC DATA BUFFERS AND BACKPLANE
CLOCK DE-JITTERIZER
AUTOMODE NT1 AND REPEATER
"U ACTIVATION ONLY" IN NT1
IDENTIFICATION CODE AS PER GCI STANDARD
DECT FRAME SYNCHRONIZATION
EASILY INTERFACEABLE WITH ST5451
(HDLC & GCI CONTROLLER), STLC5464 /
STLC5465 AND ANY OTHER GCI, IDL or
TDM COMPATIBLE DEVICES
INDEX
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .μW/DSI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .μW Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GCI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line coding and frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Elastic buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dect synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maintenance functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EOC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M4 channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spare M5 and M6 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC calculation checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopbacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Identification code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General purpose I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turning on and off the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line signal detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power up control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power down control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activation deactivation sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case of restricted activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset of activation / deactivation state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quiet mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command/Indication (C/I) codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line interface circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX A: STATE MATRIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
APPENDIX B: ELECTRICAL PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
STLC5412
2/74
PIN CONNECTIONS (Top view)
STLC5412
3/74
Figure 1: Block Diagram.
STLC5412
4/74
GENERAL DESCRIPTION
STLC5412 is a complete monolithic transceiver
for ISDN Basic access data transmission on
twisted pair subscriber loops typical of public
switched telephone networks. The device is fully
compatible with ETSI ETRO80 and CSE (C32-11)
French specifications.
The equivalent of 160 kbit/s full-duplex transmis-
sion on a single twisted pair is provided, accord-
ing to the formats defined in the a.m. spec.
Frames include two B channels, each of 64 kbit/s,
one D channel of 16 kbit/s plus an additional 4
kbit/s M channel for loop maintenance and other
user functions. 12 kbit/s bandwidth is reserved for
framing. 2B1Q Line coding is used, where pairs of
bits are coded into one of 4 quantum levels. This
technique results in a low frequency spectrum
(160 kbit/s turn into 80 kbaud), thereby reducing
both line attenuation and crosstalk and achieving
long range with low Bit Error Rates.
STLC5412 is designed to operate with Bit Error
Rate near-end Crosstalk (NEXT) as specified in
european ETSI recommendation.
To meet these very demanding specifications, the
device includes two Digital Signal Processors,
one configured as an adaptive Echo-Canceller to
cancel the near end echoes resulting from the
transmit/receive hybrid interface, the other as an
adaptive line equalizer. A Digital Phase-Locked
Loop (DPLL) timing recovery circuit is also in-
cluded that provides in NT modes a 15.36 MHz
synchronized clock to the system. Scrambling
and descrambling are performed as specified in
the specifications.
On the system side, STLC5412 can be linked to
two bus configuration simply by pin MW bias.
MICROWIRE(μW/DSI) mode (MWpin = 5V): 144
kbit/s 2B+D basic access data is transferred on a
multiplex Digital System Interface with 4 different
interface formats (see fig. 2 and 3) providing
maximum flexibility with a limited pin count
(BCLK, Bx, Br, FSa, FSb). Three pre-defined
2B+D formats plus an internal time slot assigner
allows direct connection of the UID to the most
common multiplexed digital interfaces (TDM/IDL).
Bit and Frame Synchronisation signals are inputs
or outputs depending on the configuration se-
lected. Data buffers allow any phase between the
line and the digital interface. That permits building
of slave-slave configurations e.g. in NT12 trunk-
cards.
It is possible to separate the D from the B chan-
nels and to transfer it on a separate digital inter-
face (Dx, Dr) using the same bit and frame clocks
as for the B channels or in a continuous mode us-
ing an internally generated 16 kHz bit clock output
(DCLK).
All the Control, Status and Interrupt registers are
handled via a control channel on a separate serial
interface MICROWIRE compatible (CI, CO, CS,
CCLK, INT) supported by a number of microcon-
troller including the MCU families from SGS-
THOMSON
GCI mode (MWpin = 0V). Control/maintenance
channels are multiplexed with 2B+D basic access
data in a GCI compatible interface format (see fig.
4a) requiring only 4 pins (BCLK, Bx, Br, FSa). On
chip GCI channel assignement allows to multiplex
on the same bus up to 8 GCI channels, each sup-
porting data and controls of one device. Bit and
Frame Synchronisation signals can be inputs or
ouputs depending on the configuration selected.
Data buffers, again, allow to have any phase be-
tween the line interface and the digital interface.
Through the M channel and its protocol allowing
to check both direction exchanges, internal regis-
ters can be configured, the EOC channel and the
Overhead-bits can be monitored. Associated to
the M channel, there are A and E channels for
enabling the exchanged messages and to check
the flow control. The C/I channel allows the primi-
tive exchanges following the standard protocol.
In both mode (μW and GCI) CRC is calculated
and checked in both directions internally.
In LT mode, the transmit superframe can be syn-
chronized by an external signal (SFSx) or be self
running. In NT mode, the SFSx is always output
synchronized by the transmit superframe.
Line side or Digital Interface side loopbacks can
be selected for each B1, B2 or D channel inde-
pendently without restriction in transparent or in
non-transparent mode. A transparent complete
analog loopback allowing the test of the transmis-
sion path is also selectable.
Activation and deactivation procedures, which are
automatically processed by UID, require only the
exchange of simple commands as Activation Re-
quest, Deactivation Request, Activation Indica-
tion. Cold and Warm start up procedures are op-
erated automatically without any special
instruction.
Four programmable I/Os are provided in GCI for
external device control.
STLC5412
5/74

Partno	Mfg	Dc	Qty	Available	Descript
STLC5412FN	ST	N/a	4	avai	2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412FN	STM	N/a	1160	avai	2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
STLC5412P	ST	N/a	48	avai	2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE