STLC1502D ,STLC1502Block diagram.......45 System Overview .45.1 ARM7 domain .....45.2 D950 domain.......55.3 Clocks .. ..
STLC2150 ,BLUETOOTH RADIO TRANSCEIVERElectrical characteristics, rated for the operating rangeSymbol Parameter Min Max UnitV High Level ..
STLC2415 ,BLUETOOTH BASEBAND WITH INTEGRATED FLASHAbsolute Maximum RatingsSymbol Conditions Min Max UnitV Supply voltage baseband core V 0.5 2.5 VDD ..
STLC3055 ,WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUITAbsolute Maximum RatingsSymbol Parameter Value UnitV Positive Supply Voltage -0.4 to +13 VposA/BGND ..
STLC3055 ,WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUITapplications is the integrated ringing generator.The control interface is a parallel type with open ..
STLC3055N ,WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUITBlock Diagram PD D0 D1 D2 DET GA ..
SY10E151JI , 6-BIT D REGISTER
SY10E157JCTR , QUAD 2:1 MULTIPLEXER
SY10E166JC , 9-BIT MAGNITUDE COMPARATOR
SY10E167JC , 6-BIT 2:1 MUX-REGISTER
SY10E171JC , 3-BIT 4:1 MULTIPLEXER
SY10E171JC , 3-BIT 4:1 MULTIPLEXER
STLC1502D
STLC1502
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STLC1502August 2004
MAIN FEATURES HCMOS7 technology Power supply: Core 2.5 V and I/O: 3.3 V Industry standard 32-bit RISC microprocessor
(ARM7/TDMI core) 16-bit, fixed point 100 MIPs DSP (D950) 2 10/100 Base-T Ethernet MACs VLAN support JTAG Smart power management
GENERAL DESCRIPTIONSTMicroelectronics’ STLC1502 is a high perfor-
mance VoIP processor specially targeted for the
time effective design of IP-Phones and analog
gateway applications bundled with a comprehen-
sive embedded software solution.
When used in the Enterprise LAN IP Phone space,
this device enables the augmentation and replace-
ment of traditional telephone systems with net-
work based communications systems running
over local and wide area IP networks. To design
an IP phone, the only other parts required will be
an analog interface, some optional Flash memory
for upgradable software and Fast Ethernet physi-
cal layer devices. The ST complete IP Phone ref-
erence design includes standards compliant
Application Programming Interfaces (APIs), proto-
col management software and software develop-
ment tools.
The STLC1502 also has all the proper interfaces
to be a cost effective solution for Small Gateway
applications. ST also offer a complete SW refer-
ence design for Small Gateway applications.
Hence, the STLC1502 enables a superior and cost
effective platform development for IP-phones as
well as voice gateway applications, providing de-
velopers with a low risk, rapid time to market solu-
tion.
The STLC1502 integrates low power D950 DSP
with a ARM7/TDMI MCU and two Ethernet 10/100
Base-T media access control interfaces.
REFERENCE SOFTWARE FEATURES
3.1 ARM7/TDMI Industry standard Real time OS: VxWorks Network Protocol Stack TCP/IP, UDP, TFTP, DHCP, HTTP server Ethernet/PC communication drivers High Level Chip Control Stack management SNMP (optional) Application Specific MIBS Signalling Protocol MGCP, H.323 (including H.450), SIP
3.2 D950 VOICE CODEC UNIT (VCU) G.711 Packetized PCM G.729AB, 8kbps CS-ACELP G.726, 16-40 kbps ADPCM G.723.1a, 6.3/5.3 kbps MP-MLQ Encoding and decoding of PCM sample frames Packing/unpacking of compressed information
in Codewords Fax Modem : T.38 Fax Relay, V.21, V.17,
V.27ter and V.29 fax datapump Data Modem: V.34 datapump Rate selection High performance Voice Activity Detector Comfort noise generator (CNG) G.165 32 ms Line & acoustic echo canceller Low latency system implementation
PRELIMINARY DATAVOICE OVER IP PROCESSOR
REV. 2
STLC1502
TABLE OF CONTENTS MAIN FEATURES ..............................................................................................................................1 General Description............................................................................................................................1 Reference Software Features ............................................................................................................1
3.1 ARM7/TDMI .............................................................................................................................1
3.2 D950 Voice Codec Unit (VCU).................................................................................................1 Block diagram.....................................................................................................................................4 System Overview ...............................................................................................................................4
5.1 ARM7 domain ..........................................................................................................................4
5.2 D950 domain............................................................................................................................5
5.3 Clocks ......................................................................................................................................5
5.4 Reset scheme ..........................................................................................................................6 Pin Descriptions .................................................................................................................................6
6.1 Pin Description Table ...............................................................................................................7 ARM Memory Configuration .............................................................................................................12
7.1 ARM Memory Map .................................................................................................................12 AHB Bus...........................................................................................................................................13
8.1 Internal RAM..........................................................................................................................13
8.2 ESM interface.........................................................................................................................13
8.2.1 ESM Register Map [0x0C600000]....................................................................................15
8.3 EDM interface ........................................................................................................................15
8.3.1 EDM Register Map [0x0C580000]....................................................................................18
8.4 DMA Controller.......................................................................................................................21
8.5 Ethernet DMA-MACs..............................................................................................................21
8.5.1 The DMA Descriptors Chain.............................................................................................21
8.5.2 The Descriptor control bits ...............................................................................................22
8.5.3 Transfer interrupts............................................................................................................22
8.5.4 Frames transmission (TX) ................................................................................................22
8.5.5 Open list approach ...........................................................................................................22
8.5.6 Closed list approach.........................................................................................................23
8.5.7 Frames reception (RX) .....................................................................................................23
8.5.8 Ethernet block Register Map [0x0C680000].....................................................................24
8.6 Arbiter.....................................................................................................................................27
8.7 TIC-Test Interface Controller..................................................................................................28
8.8 AHB-ASB bridge ....................................................................................................................28 APB bus ...........................................................................................................................................28
9.1 Timer......................................................................................................................................30
9.1.1 Timer introduction.............................................................................................................30
9.1.2 Timer operation ................................................................................................................30
9.1.3 Timer register map [0x0C000000]....................................................................................32
9.2 Watchdog Timer.....................................................................................................................33
9.2.1 Watch Dog Register Map [0x0C500000]..........................................................................33
9.3 Miscellaneous I/O...................................................................................................................33
9.3.1 Miscellaneous Register Map [0x0C080000].....................................................................33
9.4 Interrupt Controller .................................................................................................................34
9.4.1 Interrupt control ................................................................................................................34
9.4.2 Interrupt control scheme...................................................................................................35
9.4.3 Interrupt register map [0x0C100000]................................................................................36
9.5 SPI-Serial Peripheral Interface...............................................................................................37
9.6 Main Features ........................................................................................................................38
9.6.1 Programming procedure...................................................................................................38
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STLC15029.6.2 Data Transfer Format.......................................................................................................39
9.6.3 Collision management......................................................................................................39
9.6.4 SPI register map [0x0C280000] .......................................................................................40
9.7 I2C bus interface....................................................................................................................40
9.7.1 Main Features ..................................................................................................................40
9.7.2 General Description..........................................................................................................40
9.7.3 Functional Description......................................................................................................42
9.7.4 I2C registers map [0X0C300000].....................................................................................45
9.8 UART-Universal Asynchronous Receiver Transmitter ...........................................................45
9.8.1 Operation..........................................................................................................................45
9.8.2 Baud rate generation........................................................................................................46
9.8.3 The timeout interrupt ........................................................................................................47
9.8.4 Interrupt control ................................................................................................................47
9.8.5 UART Memory map..........................................................................................................47
9.9 GPIO/Keypad encoder...........................................................................................................48
9.9.1 GPIO operation mode ......................................................................................................48
9.9.2 Keyboard operation mode ................................................................................................489.9.3 GPIO registers map [0x0C400000] ..................................................................................48
9.10 HPI (*) ....................................................................................................................................49
9.10.1 Send Message from Host Processor to ARM...................................................................50
9.10.2 Receive Message from ARM by Host Processor .............................................................50
9.10.3 Send Message from ARM to Host Processor...................................................................50
9.10.4 Receive Message from Host Processor by ARM .............................................................50
9.10.5 HPI Memory map .............................................................................................................51
9.11 Dual Port SRAM.....................................................................................................................51
9.11.1 DPRAM protocol...............................................................................................................51
9.11.2 Dual Port memory map [0x0C180000].............................................................................53
9.11.3 DPRAM registers map......................................................................................................54 STLC1502 Register Map..................................................................................................................54 D950 Domain ...................................................................................................................................57
11.1 D950 memory map.................................................................................................................58
11.2 DPRAM memory map [0x8000] .............................................................................................59 PCM Interface ..................................................................................................................................60
12.1 Miscellaneous Interface .........................................................................................................61
12.2 Interrupt Event Management..................................................................................................61
12.3 Clock Distribution ...................................................................................................................62
12.4 Reset Distribution and Configuration .....................................................................................62
12.5 Data Flow Management.........................................................................................................62
12.6 Basic Operation......................................................................................................................62
12.7 PCM coding Voice Frame ......................................................................................................63
12.7.1 Linear coding Voice Frame ..............................................................................................63
12.8 PCM Register List ..................................................................................................................63 Electrical Specifications and Timings...............................................................................................65
STLC1502
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STLC1502for boot coded and configuration data storage GPIO block includes as an alternative function a scanning key encoder for direct interface with a 6x6
keypad matrix Debouncing function is performed, so no overhead for the ARM controller is introduced UART port allows connection to a host terminal. Code downloaded through UART can be performed
during boot A Host Processor Interface (*) (HPI) allows direct connection of an external control processor. The
interface is directly compatible with the Motorola MPC850 external bus
(*) Note: HPI interface is available only on request
5.2 D950 DOMAINThe D950 domain is a DSP machine based on the D950 core. The D950 core is based on Harvard architecture with separate buses for instruction (I-bus) and data
(X-bus, Y-bus) The internal ROM runs basic system management code and standard vocoders like
G711,G723.1A,G729AB and others. Additional vocoders and algorithms are the ARM side through the DPRAM External CODEC is connected with a standard four wires PCM bus interface JTAG and emulation port are available for system software/hardware testing DPRAM is used as a communication channel between the ARM and D950 Control messages and voice packets are exchanged through the DPCOM Fax over IP support
5.3 CLOCKSThree main clock domains are present: D950 and peripherals (100 MHz max) ARM7 and peripherals (60 MHz max) PCM (8.192 MHz max)
The clock base is provided by a fixed external 25MHz crystal/oscillator. A 25MHz clock output can be used
as a master clock for external Ethernet PHY devices, in 10BaseT operation.
NOTE: For 100BaseT operation, this clock may not be sufficiently stable with tight jitter requirements.
Thus the PHY’s may need their own 25 MHz crystal.
Internal PLL’s provide independent clocks to the D950 and ARM7 domain.
The ARM frequency is set by external pin, that selects between 50 MHz and 60 MHz.
The D950 frequency can be set by the ARM via Status register programming.
Four possible values are provided:
100 MHz
180 MHz
190 MHz
200 MHz
To change the D950 master clock frequency the following procedure must be followed:
1) Disable the D950 clock, by resetting the DCLK bit in the control register of the MISC Control register.
2) Wait 10 ARM cycles
3) Select a new D950 master clock, by writing the MISC Status register.
4) Wait 4 ms
5) Disable the D950 clock, by setting the DCLK bit in the MISC Control register.
An Internal divider provides an internal PCM clock, 2083 KHz, that is not exactly the standard 2048 KHz. An external PCM clock frequency can be applied using a dedicated crystal or oscillator, to provide ex-
STLC1502 actly 8KHz synch and sampling clock on the PCM bus. (External pins configuration Testsel[3:0] at
[0011]).
The PCM clock rate can be selected via software to achieve the following values:
1536 (24 Ch.) 2048 (32 Ch.) 4096 (64 Ch.) 8192 KHz (128 Ch.). The PCM clock and Frame synch signals can be selected as inputs or outputs, by programming the con-
trol register in the miscellaneous block.
5.4 RESET SCHEMEA general hardware reset is provided by an external pin and is generated during power-on. Three blocks are reset by the general reset: ARM7 core, D950 core, PCM interface. The Watchdog timer can generate a reset of the ARM7 core, as well. A software reset is available for each of the blocks in the Control register.
The following Reset hierarchy should be implemented in order to provide a reliable start-up. They are list-
ed in the order
of propagation Thus it follows that when an ARM7 reset is generated, a D950 reset and a PCM reset are
also generated and further, when a D950 reset is generated a PCM reset is also generated:
1) Hw reset (pin and power-on)
2) Watchdog timer
3) ARM7 software reset
4) D950 reset
5) PCM block reset
PIN DESCRIPTIONSThe STLC1502 will be delivered in: PQFP 208 Pins
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STLC1502
STLC1502
Table 2. Pin Description (continued)
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STLC1502
Table 2. Pin Description (continued)
STLC1502
Table 2. Pin Description (continued)
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STLC1502
Table 2. Pin Description (continued)
STLC1502 ARM MEMORY CONFIGURATION The AMBA bus system allows to ha ndle memory blocks and peripherals on distinct buses, in order to
optimize the AHB architecture for maximum speed. The memory blocks are attac hed to the AHB bus so ARM code can run at maximum speed. An internal ROM is used to store boot code that polls serial peripherals (I2C EEPROM, UART) and
HPI for code download in external RAM. After download, the control is given to code in external
RAM. An internal RAM is used to store ARM7 interrupt vectors and some data (network frames) Four external memory types can be connected.
Flash
SRAM
DRAM (SDRAM or EDO)
Serial EEPROM Flash, SRAM, DRAM share the same 32 bits data bus and 32 bits address bus. Little/Big endian
mode is software programmable for the DRAM memory controller. Serial EEPROM can be con-
nected to the I2C bus. The chip provides the option of booting from Flash or from serial EEPROM, by selection from an
external BOOT_SEL pin. So different memory configurations are possible depending on the applica-
tion: Flash, DRAM: The boot code including BOOTP and TFTP is stored in Flash. Application can be
stored in flash also, or can be downloaded into DRAM from Ethernet Network or UART. EEPROM, DRAM: The boot is performed from internal ROM. The ROM code loads the code stored
in EPROM that includes BOOTP and TFTP . Application code will be downloaded into DRAM from
Ethernet or UART. Flash, DRAM, EEPROM: It is like case 1, but has more flexibility. The EEPROM can be used to store
Network parameter data (MAC address) and other specific board data, so the code to store in flash is
the same for all the platforms, and you do not need to split the flash in a permanent storage area and
in an upgradable storage area. The EEPROM can also be used to allow the programming of the flash
the first time with a code Ethernet Network. DRAM: The boot is performed from internal ROM. The application code is the host
processor through the HPI (*) interface. To access external memory bus an internal decoder is imple-
mented, that can select different external memory devices. 32 bits data bus is provided with the pos-
sibility to select external accesses at 16 and 8 bits for each memory bank. For example the flash can
be at 16 bits and the DRAM at 32 bits. There are 3 chip select available for static memory (4Mbytes
each), 4 chip selects for dynamic memory (8Mbytes each).
(*) Note: HPI interface is available only on request
7.1 ARM MEMORY MAP The ARM microprocessor sees 5 main memory areas.
Actually the memory map depends on the phase the microprocessor is working on: Boot from internal ROM phase (REMAP=0 and BOOT_SEL=0); Boot from external Flash phase (REMAP=0 and BOOT_SEL=1); Operating phase (REMAP=1).
The first two phases are alternative (only one of them happens at the power on reset, while the third happens
after the boot.
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STLC1502 AHB BUSAHB Bus is a 32 bits data and 32 bits address bus.
8.1 INTERNAL RAMAn internal Static RAM 2048x 32 is mapped starting at address 0x0 in operational mode and is used for ARM
interrupt vector tables.
8.2 ESM INTERFACE The ESM (External Static Memory) interface is used to access static RAMs or Flash devices. It pro-
vides 3 chip select signals and gives external access to 21 address bits, so that the memory space
accessible through each chip select is 4 Mbytes. The data bus on ESM external interface is 32bits wide, with the additional ability to perform 16 and 8
bits accesses. Little endian byte ordering is used. The data bus and address bus pins are shared with
the DRAM driver, using EBI interface. Programmable per chip-select wait-states from 0 to 15 internal clock cycles are available. At reset, every CS space has 15 wait states. The actual value is contained in the downloaded code. The external memory spaces are mapped by the ESM interface as reported in Figure 4. There are 3 addressable memory spaces 0x00400000 byte long each.
Figure 4. ESM memory mapFollowing is the list of the available external signals that implement SRAM or FLASH read and write cycles. Data
and address buses are not shown as they are shared with the DRAM EBI interface.
Table 3.
STLC1502 A scheme of the ESM control interface is reported in Figure 5.
Figure 5. ESM control interfaceEvery CS space can be programmed through internal register (one for each CS) in order to: select the number of wait states to perform external access depending on the speed of the external
device mapped on that memory area select if the data bus is x8 or x16 (available only for CS1 to CS2). When the x8 memories are used,
their data bus has to be placed on the ESM_D(7:0) signals
The wait states number for the external memories (depending on memory access time) is obtained from the
software code during the download phase. During the initialization phase, it is the responsibility of the software
to determine if a SRAM or a FLASH is present or not on a given CS space and the width of CS1-2 memories (if
present).
It is possible to connect every CSx to a Dual Port SRAM and use that as a communication mailbox between the
device and an external microprocessor. For example, the microprocessor can write a message in the memory
using one port and can send an interrupt to the device so that the execution routine related with that interrupt
can read from the other port of the memory connected to the same CSx of the ESM.
Viceversa, the ESM can write a message in the memory and then can send an interrupt to the external micro-
processor that will read the message from the other port of the memory.
The SRAM and the FLASH devices that are used as references are standard.
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STLC1502 ESM address decoding scheme
The ESM block includes also a decoder in order to generate the proper CS to the external device. In particular
this decoder will work on the bit 22,23,24 and 25 of the internal ARM address bus.
ESM decoding scheme
8.2.1 ESM REGISTER MAP [0X0C600000]The base address of the ESM register is 0x0C600000.
8.3 EDM INTERFACE The EDM interface is used to access external DRAMs. This block supports both EDO and SDRAM interfaces
with enough flexibility to be used with several DRAM chips available in the market. This block has a separate
bus for control (the registers are placed on the APB bus) and for data (data and address are placed on the ASB
bus) and also includes an external bus interface that allows to share address and data bus pins with the static
ESM interface.
Figure 6 shows a block diagram of the EDM block.
STLC1502
Figure 6. EDM block diagramIt is possible to connect up to 4 external chips with x8, x16, and x32 data bus. Each memory bank space is
8Mbytes big so that a standard 64Mbit DRAM device can be connected. It is not possible to use a single
32Mbytes memory device.
It is the responsibility of the ARM code to properly configure the EDM block to initialize the DRAM at startup.
The external memory is mapped by the EDM interface as shown in Fig. 7.
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STLC1502
Figure 7. EDM memory mapIn the following table there is the list of the available external signals of the EDM interface.
Table 4. The EDM block includes a decoder in order to generate proper CS to the external device. In particular this de-
STLC1502 coder will work on bits 25 and 26 of internal ARM address bus.
EDM decoding scheme Every CS space can be programmed through internal register in order to configure the EDM to work
with the proper external device The DRAM Controller has nine registers, the config uration register, four bank registers and four
SDRAM configuration registers. The registers are accesses via the APB bus. The register data path
is 16 bits wide.
8.3.1 EDM REGISTER MAP [0X0C580000] The base address of the EDM register is 0x0C580000
Table 5.
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STLC1502 Memory Bank Configuration registers
Memory bank configuration registers are used to setup memory bank specific parameters:
DEVWID: Device Width Defines the data width of the external memory device: 00 - Byte (8 bit) 01 - Half Word (16 bit) 10 - Word (32 bit)
DATALAT: Data Latency Defines the number of memory clock cycles between the start of a memory read access and the first
valid data. The DATALAT value is valid between 0 and 3.
SETUPTIME: Setup Time Defines the number of memory clock cycles the me mory driver spends in the DECODE state before
accessing the external memory. The SETUPTIME value is valid between 0 and 7.
IDLETIME: Idle Time Defines the minimum time the memory driver must spend in the IDLE state following memory
accesses. The value defines the number of Memory Clock cycles. The IDLETIME value is valid between 0 and 7.
SDRAMCOL: SDRAM Column Width Definition Specifies the width of the SDRAM column address: 00 - 8 bits 01 - 9 bits 10 - 10 bits 11 - reserved
SDRAM Configuration registers
These registers are write only. A write access to the high registers will start the SDRAM configuration cycle,
during which the value written to the register will be asserted on the memory bus for a one clock period.
Low SDRAM Configuration Registers
STLC1502 MIAB: Memory Interface Address Bus
High SDRAM Configuration Registers
MIAB: Memory Interface Address Bus
MIWE: Memory Interface Write Enable
MIAA: Memory Interface Access Active (nCAS)
MISA: Memory Interface Setup Active (nRAS)
After the power-up the CPU must configure each SDRAM device, i.e. perform precharge-refresh-mode register
set procedure.
Memory Configuration register
Memory configuration registers are used to setup parameters that are same for all banks:
PWS: Power save mode If PWS bit is set to’1’, the next refresh cycle will set the memory devices in the self-refresh mode. The memories will exit the self-refresh mode, when the PWS mode is set to’0’.
TYPE: Memory type: The TYPE bit is used to select a type of the external memory.
1 - SDRAM
0 - EDO
B3EN: Bank 3 enable
B2EN: Bank 2 enable
B1EN: Bank 1 enable
B0EN: Bank 0 enable The bank enable bits are used to enable each bank separately. If an AHB transfer is accessing a disabled bank, the DRAM Controller will return the error response
to the AHB master.
REFR: Refresh period The REFR value is used to determine the refresh period. The period can be set in the 1 us steps. REFR Refresh Period 00000000 Refresh is disabled 00000001 Refresh period is 1us 00000010 Refresh period is 2us. 11111111 Refresh period is 255us
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STLC1502
STLC1502 A Descriptor can be stored in any main memory location with a 32-bit aligned address. The first 3 words stored in a Descriptor are expected to be the values of the 3 DMA_MAC registers
describing a DMA transfer (DMA_Cntl, DMA_Addr and DMA_Next). When the DMA_MAC fetches a
Descriptor it loads this three values into its own corresponding registers. The last word is to be used by the DMA_MAC to report the transfer status.
8.5.2 THE DESCRIPTOR CONTROL BITSThe Descriptor keeps information about a single frame transfer and how to access the next Descriptor.
The following discussion is related to 3 bits of the Descriptor: the VALID bit, the NXT_EN bit and the
NPOL_EN bit.
The Descriptor can be accessed simultaneously by the CPU and the DMA_MAC. This concurrent access
is synchronized by the VALID bit in the DMA_Cntl register. When the VALID bit is equal to 0 then the CPU
is the owner of the Descriptor. Otherwise the owner is the DMA_MAC. Since the Descriptor can be ac-
cessed in write mode by the owner only at any time, race conditions are guaranteed to never happen.
The NXT_EN bit enables the fetch of the Next Descriptor. When the DMA_MAC finds this bit set to 0 then
its activity is considered to be completed as soon as the current descriptor DMA transfers have been com-
pleted.
The NPOL_EN bit enables the DMA_MAC to keep polling for a non-valid Descriptor until its VALID bit is
set to one. When the DMA_MAC finds both the NPOL_EN bit and the VALID bit set to 0 then its activity is
considered to be completed.
8.5.3 TRANSFER INTERRUPTSThe DMA_MAC can interrupt the CPU with three different levels of information about transfer completion.
The CPU can choose which interrupt needs to be enabled. They do not exclude each other though; they
can be all three enabled at the same time.
The TX_CURR_DONE (RX_CURR_DONE) interrupt bit reports the CPU when a single Descriptor (i.e.
one frame) has been completely treated by the DMA_MAC and the CPU is again the owner (VALID bit set
to 0).
The TX_NEXT (RX_NEXT) interrupt bit is set when next descriptor fetch is enabled (NXT_EN=1 in the
current descriptor) the next Descriptor is not valid (VALID bit is off).
The TX_DONE (RX_DONE) interrupt bit is set when a whole DMA transfer is complete. This can happen
either when the current is the last Descriptor in the chain (NXT_EN is off) or when the next Descriptor is
not valid yet (VALID bit is off) and the polling is disabled (NPOL_EN bit is off).
8.5.4 FRAMES TRANSMISSION (TX)When the CPU wants to transmit a set of frames on the cable, it needs to provide the DMA_MAC with a
Descriptor list. The CPU is expected to allocate a Descriptor for each frame it wants to send, to fill it with
the DMA control information and the pointer to the frame, and to link the Descriptor in the chain. The
frames will be sent on the cable in the same order they are found in the chain.
8.5.5 OPEN LIST APPROACHThe simplest way to construct a Descriptor chain is the open list approach. Every Descriptor but the last
one will have the DMA_Next field pointing to the next Descriptor in the chain, the NXT_EN bit and the VAL-
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STLC1502ID bit on, the NPOL_EN bit on/off. The last Descriptor will be set in the same way except for the NXT_EN
bit (off) and the DMA_Next field (NULL). The CPU starts the DMA activity loading the physical location of the first Descriptor into the DMA
Next register of the DMA_MAC and set the DMA Start register enable bit to on. The DMA_MAC will then keep fetching the Descriptors one by one until it finds the NXT_EN bit of the
last Descriptor set to off. Every time it completes a Descriptor (frame) it saves the transfer status into
TxRx_Status, it turns the Descriptor VALID bit to off and raises the TX_CURR_DONE interrupt bit. When the NXT_EN bit is found to be off, that means the DMA_MAC has fetched the last Descriptor in
the chain. When it completes also this Descriptor (the end of the DMA transfer) it raises both the
TX_CURR_DONE and the TX_DONE interrupt bits.
8.5.6 CLOSED LIST APPROACHThe approach above is easy since it doesn’t require the DMA_MAC and the CPU to synchronize their ac-
cess to the Descriptor chain. The problem is that it requires the CPU to build the list every time it needs a
transfer.
A faster way to operate is building a closed Descriptor list only the first time and using the VALID bit to
mark the end of the transfer. The polling facility could also be used to save the CPU from the activity of
programming the DMA Start register every time it needs to start the DMA transfer. Instead, the DMA Start
register will be activated only once and the DMA_MAC will keep polling the invalid descriptor, raising each
time the TX_NEXT interrupt bit (if enabled), until the CPU finally sets its VALID bit to on. Since the DMA
transfer practically never ends, note that in this case the TX_DONE interrupt bit is never raised.
With this approach every Descriptor will have the DMA_Next field pointing to the next Descriptor in the
chain (the last one will point to the first one), the NXT_EN bit, the VALID bit and the NPOL_EN bit on.
The DMA_MAC will keep fetching the Descriptors one by one until it finds one with its VALID bit set to off.
Every time the DMA_MAC completes a Descriptor (frame) it saves the transfer status into TxRx_Status,
it turns its VALID bit to off and raises the TX_CURR_DONE interrupt bit.
8.5.7 FRAMES RECEPTION (RX)The frame reception process is something that needs to be activated at the beginning and kept always
running. For this reason the closed Descriptor list (see above) is much more useful than the open list ap-
proach.
Again, with this approach every Descriptor will have the DMA_Next field pointing to the next Descriptor in
the chain (the last one will point to the first one), the NXT_EN bit, the VALID bit and the NPOL_EN bit on.
The CPU starts the transfer activity loading the DMA Next register of the DMA_MAC with the physical lo-
cation of the first Descriptor and set the DMA Start register enable bit to on.The DMA_MAC will start fetch-
ing the Descriptors one by one, driven by the frames reception from the line. Every time the DMA_MAC
completes a Descriptor (frame) it saves the transfer status into TxRx_Status, it turns its VALID bit to off
and raises the TX_CURR_DONE interrupt bit.
Eventually, the DMA_MAC will be faster than the CPU, it will wrap around the Descriptor chain and find a
Descriptor still invalid.
Then the DMA_CNT keeps polling the invalid descriptor, raising each time the TX_NEXT interrupt bit (if
enabled), until some Descriptor gets available (note that in this case some frame could be lost). In the
STLC1502 meantime the CPU should consume the frames received and set the VALID bit to on of all the Descriptor
released.
As soon as the DMA_CNT finds the Descriptor valid again, it will be able to complete the transfer and to
fetch the next Descriptor.
8.5.8 ETHERNET BLOCK REGISTER MAP [0X0C680000]The base address of the Ethernet registers is 0x0C680000
The memory map of the Dual MAC Ethernet block is shown below:
Table 6.
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8.6 ARBITERThe arbiter is used to ensure that, at any point in time, only one master has access to the bus. It performs this
function by observing all of the bus master requests to use the bus, and deciding which is currently the highest
priority. It has a standard interface to all bus masters and split-capable slaves in the system. However it does
not support SPLIT bus transfers.
A bus master may request the bus during any cycle by setting its HBUSREQ output HIGH. This is then sampled
by the arbiter on the rising edge of the clock, and passed through the priority algorithm to decide which master
will have access to the bus during the next cycle. The HGRANT then outputs change to indicate which master
currently is granted control of the bus.
The HLOCK signals may be used to ensure that during an indivisible transfer, the current grant outputs do not
change. HLOCK must be asserted at least one cycle before the locked transfer to prevent the arbiter from
changing the grant signals. When more than one master requests ownership of the system bus, the priority used
for arbitration is:
Highest: TIC
Printer Drive Control
DMA Controller
Lowest: ARM7TDMI (default master)
The ARM7TDMI will periodically assume top priority on the system bus: this period can be programmed. Also,
it will assume top priority when an interrupt occurs, if the interrupt mode is enabled. During reset, and when no
other masters are requesting control of the bus, the ARM7TDMI is selected as the currently granted master.
This minimizes the delay required for the core to perform a transfer on the bus, as it does not have to wait to be
granted control of the bus before it can start a new transfer.
The system also requires a default master, which is selected when no masters are granted control of the bus,
for example, when all system bus masters are waiting for split transfers to complete. The default master per-
forms IDLE transfers while it is granted control of the bus. The bus grant outputs may change while HREADY
is LOW, but the newly granted master may only drive the bus when the current transfer has completed. This
requires that bus masters only drive the bus after they detect that both their HGRANT and HREADY inputs are
set HIGH.
All registers used in the system are clocked from the rising edge of the system clock HCLK, and use the asyn-
chronous reset HRESETn. The arbiter control and status registers are accessed via the APB bus.
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8.7 TIC-TEST INTERFACE CONTROLLERThe Test Interface Controller (TIC) is a state machine that provides an AMBA AHB bus master for system test.
It reads test write and address data from the external data bus TESTBUS (XD), and uses the External Bus In-
terface (part of the DRAM Controller) to drive the external bus with test read data, allowing the use of only one
set of output tristate buffers onto TESTBUS.
The TIC is used to convert externally applied test vectors into internal transfers on the AHB bus. A three-wire
external handshake protocol is used, with two inputs controlling the type of vector that is applied and a single
output that indicates when the next vector can be applied. Typically the TIC is the highest priority AMBA bus
master, which ensures test access under all conditions. The TIC model supports address incrementing and con-
trol vectors. This means that the address for burst transfers can automatically be generated by the TIC.
8.8 AHB-ASB BRIDGEThe APB bridge is the only bus master on the Advanced Peripheral Bus. In fact, the APB bridge is also a slave
on the AHB. The bridge unit converts ASB transfers into APB transfers. On the APB bus only 16 bits wide data
accesses are permitted. 32 bit wide and 8 bit wide transfers are not supported. All the APB peripherals decodes
all the 16 bits of the PA bus.
APB decoding scheme
Every area is 128k x 16 bits but the area actually available is 32k x 16 due to the fact that the address lines on
the APB bus are 16 (PA(15:0)). That means that in every area dedicated to the several block on the APB bus
only the first FFFF is usable.
APB BUSThe APB bus is a 16 bits data and 16 bits address bus. The blocks attached on this bus are described in the
following sections while the memory area is reported in the following figure.
All the addresses in the APB space are word aligned (addresses are multiples of four)
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9.1 TIMERThe Timer module connects to the Advanced Peripheral Bus.
Figure 10. Timer block diagramThis implementation consists of two major sections comprising: All the control logic Two instantiations of the free-running counters (FRCs)
The timer module has a series of memory-mapped locations that allow the state of the timer module to be read
from and written to via the APB.
9.1.1 TIMER INTRODUCTIONTwo timers are defined and can be selected by the Control register: Free-running mode:The timer wraps after reaching its zero value, and continues to count down from
the maximum value. Periodic timer mode:The counter generates an interrupt at a constant interval.
9.1.2 TIMER OPERATIONThe timer is loaded by writing to the load register and, if enabled, counts down to zero. When zero is reached,
an interrupt is generated. The interrupt may be cleared by writing to the Clear register.
After reaching a zero count, if the timer is operating in free-running mode it continues to decrement from its max-
imum value. If periodic timer mode is selected, the timer reloads from the load register and continues to decre-
ment. In this mode the timer effectively generates a periodic interrupt. The mode is selected by a bit in the
Control register.
At any point, the current timer value may be read from the Value register.
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9.1.3 TIMER REGISTER MAP [0X0C000000]The base address of the timer register is 0x0C000000
The offset of any particular register from the base address is the following.
Table 7.
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9.2 WATCHDOG TIMERSTLC1502 contains a Watchdog timer. This timer is used to reset the ARM7 in case of a software deadlock.
The watchdog timer generates a hot reset when it overflows which will restart the ARM, but the code will
not be downloaded again. The timer should be cleared by the software before it overflows.
It is based on a 8 bit counter which is clocked by a slow signal coming from a 17 bit prescaler clocked by
the system clock.
So the elapsing time of the watchdog timer depend on the system clock:
SYS_CLK:
13MHz => 2.58 seconds
26MHz => 1.29 seconds
39MHz => 0.86 seconds
52MHz => 0.64 seconds
This peripheral consists of a timer that continue to run and to reset the core if the software doesn’ t clear
it before it elapses. The software can clear or disable the timer by writing the WDOG_CONTROL register
9.2.1 WATCH DOG REGISTER MAP [0X0C500000]The base address of the WDT register is 0x0C500000
The memory map of the WDT peripheral is shown below:
Table 8.
9.3 MISCELLANEOUS I/OAll the registers not related to any module attached to the APB/AHB bus such as EII, Test are considered Mis-
cellaneous I/O. Additionally, the ESM configuration register and the Dual Port register are also part of this block.
9.3.1 MISCELLANEOUS REGISTER MAP [0X0C080000]The Miscellaneous register address is 0x0C080000
Table 9.
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9.4 INTERRUPT CONTROLLERIn an ARM system, two levels of interrupt are available: FIQ (Fast Interrupt Request) for fast, low latency interrupt handling IRQ (Interrupt Request) for more general interrupts
Ideally, in an ARM system, only a single FIQ source would be in use at any particular time. This provides a true
low-latency interrupt, because a single source ensures that the interrupt service routine may be executed direct-
ly without the need to determine the source of the interrupt. It also reduces the interrupt latency because the
extra banked registers, which are available for FIQ interrupts, may be used to maximum efficiency by preventing
the need for a context save.
Separate interrupt controllers are used for FIQ and IRQ.
There are 15 interrupt causes available in the IRQ controller coming from: Software (internally generated)
Timer1
Timer2
UART Dual Port RAM
I2C Ethernet switch DMAC1 Ethernet switch DMAC2 SPI
DMAC
IRQ1/GPIO18
IRQ2/GPIO19
IKybd
HPI
Timer3
Even if only a single bit position is defined for FIQ, the interrupt controller can drive one of the interrupt source
(IRQ interrupt sources), through a register, in order to generate the FIQ interrupt.
The IRQ interrupt controller uses a bit position for each different interrupt source.
All interrupt source inputs must be active HIGH and level sensitive and it remain active until the interrupt cause
has been cancelled.
No hardware priority scheme nor any form of interrupt vectoring is provided, because these functions can be
provided in software.
A programmed interrupt register is also provided to generate an interrupt under software control.
Every interrupt source can be masked.
9.4.1 INTERRUPT CONTROLThe IRQ interrupt management is done as described in the following: An interrupt is generated by a given device/source; This cause is readable by the IRQRawStatus register; If not masked (the mask is set by IRQEnableSet and reset by IRQEnableClear), this interrupt will
generate a IRQ signal to the ARM and the interrupt source will be known by a read of the IRQStatus
register. The ARM will serve the IRQ reading at first in the IRQStatus the active interrupt requests and will
execute with a given priority the proper interrupt routine. Every routine must erase (quite soon) in
some way its interrupt request source. This causes also for the proper bit in the IRQRawStatus regis-
ter and in the IRQStatus register to disappear.
The same interlock is present for the FIQ interrupt.
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9.4.2 INTERRUPT CONTROL SCHEME
Figure 13. Interrupt block scheme
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Figure 14. IRQ control block
9.4.3 INTERRUPT REGISTER MAP [0X0C100000]The base address of the timer register is 0x0C100000
The offset of any particular register from the base address is the following.
Table 10.
