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STE180N10NAISPanasonicN/a3000avaiOLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-IN


STE180N10 ,OLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-INSTE180N10®N - CHANNEL 100V - 5.5 mΩ - 180A - ISOTOPPOWER MOSFETTYPE V R IDSS DS(on) DSTE180N10 100 ..
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STE180N10
OLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-IN
STE180N10
N - CHANNEL 100V - 5.5 mΩ - 180A - ISOTOP
POWER MOSFET TYPICAL RDS(on) = 5.5 mΩ 100% AVALANCHE TESTED LOW INTRINSIC CAPACITANCE GATE CHARGE MINIMIZED REDUCED VOLTAGE SPREAD

INDUSTRIAL APPLICATIONS:
SMPS & UPS MOTOR CONTROL WELDING EQUIPMENT OUTPUT STAGE FOR PWM, ULTRASONIC
CIRCUITS
February 1999
ABSOLUTE MAXIMUM RATINGS

(•) Pulse width limited by safe operating area (1) ISD ≤180 Α, di/dτ ≤ 200 A/μs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
1/8
THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (Tcase = 25
o C unless otherwise specified)
OFF
ON (∗)
DYNAMIC
STE180N10

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ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
(∗) Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area Thermal Impedance
STE180N10

3/8
Output Characteristics
Transconductance
Gate Charge vs Gate-source Voltage
Transfer Characteristics
Static Drain-source On Resistance
Capacitance Variations
STE180N10

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Normalized Gate Threshold Voltage vs
Temperature
Source-drain Diode Forward Characteristics
Normalized On Resistance vs Temperature
STE180N10

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Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuits For

Resistive Load
Fig. 2: Unclamped Inductive Waveform
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching

And Diode Recovery Times
STE180N10

6/8
ic,good price


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