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STE100P
STE100P
STE100P
1.0 DESCRIPTIONThe STE100P, also referred to as STEPHY1, is a
high performance Fast Ethernet physical layer inter-
face for 10BASE-T and 100BASE-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100BASE-
TX of IEEE802.3u and 10BASE-T of IEEE802.3.
The STEPHY1 supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2.0 FEATURE
2.1 Industry standard IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T compliant Support for IEEE802.3x flow control IEEE802.3u Auto-Negotiation support for
10BASE-T and 100BASE-TX MII interface Standard CSMA/CD or full duplex operation
supported
10/100 FAST ETHERNET 3.3V TRANSCEIVER
STE100P
2.2 Physical Layer Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T Provides Full-duplex operation on both 100Mbps and 10Mbps modes Provides Auto-negotiation(NWAY) function of full/half duplex operation for both 10 and 100 Mbps Provides MLT-3 transceiver with DC restoration for Base-line wander compensation Provides transmit wave-shaper, receive filters, and adaptive equalizer Provides loop-back modes for diagnostic Builds in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder Supports external transmit transformer with turn ratio 1:1 Supports external receive transformer with turn ratio 1:1
2.3 LED DisplayThe LED display, consists of five LEDs having the following characteristics: 10 Mbps Speed LED: 10Mbps(on) or 100Mbps(off) 100 Mbps Speed LED: 100Mbps(on) or 10Mbps(off) TX/RX Activity LED: Blinks at 10Hz when receiving, but not colliding Link LED: On when a good link is detected, blinks when there is TX or RX activity Full Duplex / Collision LED: On during Full Duplex operation. Blinks at 20Hz to indicate a collision
2.4 Miscellaneous Standard 64-pin QFP package pinout
3.0 PIN ASSIGNMENT DIAGRAM
STE100P
Figure 3. Pin Connection
4.0 PIN DESCRIPTION
Table 1. Pin Description
STE100P
Table 1. Pin Description
STE100P
Table 1. Pin Description
STE100P
Table 1. Pin Description
STE100P
5.0 HARDWARE CONTROL INTERFACE
5.1 Operating ConfigurationsThe Hardware Control Interface consists of the MF<4:0>, CFG <1:0> and FDE input pins as well as the LED/
PAD pins. This interface is used to configure operating characteristics of the STE100P. The Hardware Control
Interface provides initial values for the MDIO registers, and then passes control to the MDIO Interface. Individual
chip addressing via the LED/PAD pins allows multiple STE100P devices to share the MII interface. Table 2
shows how to set up the desired operating configurations using the Hardware Control Interface.
Table 2. Operating Configurations / Auto-Negotiation Enabled
Note: If pin 5, MF0 = 0, or ANE (pin MF0 / PR0:12) = 0 (Auto-Negotiation disabled), then PR4 bits 5-8 will contain the default value indicatedin the table describing register PR4.
5.2 LED / PHY Address InterfaceThe LED output pins can be used to drive LED’s directly, or can be used to provide status information to a net-
work management device. The active state of each LED output driver is dependent on the logic level sampled
by the corresponding PHY address input upon power-up/reset. For example, if a given PAD input is resistively
pulled low then the corresponding LED output will be configured as an active high driver. Conversely, if a given
PAD input is resistively pulled high then the corresponding LED output will be configured as an active low driver.
These outputs are standard CMOS drivers and not open-drain.
The STE100P PAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros
(00000) will result in a PHY isolation condition as a result of power-on/reset, as documented for PR0 bit 10.
(See Section 7 for more detailed descriptions of device operation.)
6.0 REGISTERS AND DESCRIPTORS DESCRIPTIONThere are 11 registers with 16 bits each supported for the STE100P. These include 7 basic registers which are
defined according to the clause 22 “Reconciliation Sublayer and Media Independent Interface” and clause 28
“Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of IEEE802.3u stan-
dard.
In addition, there are 4 special registers for advanced chip control and status information.
6.1 Register List
STE100P
6.2 Register Descriptions
Table 3. Register Descriptions
STE100P
Table 3. Register Descriptions
STE100P
Table 3. Register Descriptions
STE100P
Table 3. Register Descriptions
STE100P
Table 3. Register Descriptions
STE100P
Table 3. Register Descriptions
STE100P
Table 3. Register Descriptions
STE100P
7.0 DEVICE OPERATION The STE100P integrates the IEEE802.3u compliant functions of PCS (Physical Coding Sub-layer), PMA (Phys-
ical Medium Attachment), and PMD(Physical Medium Dependent) for 100BASE-TX, and the IEEE802.3 com-
pliant functions of Manchester encoding/decoding and transceiver for 10BASE-T. All the functions and
operation schemes are described in the following sections.
7.1 100BASE-TX Transmit OperationRegarding the 100BASE-TX transmission, the device provides the transmission functions of PCS, PMA, and
PMD for encoding of MII data nibbles to five-bit code-groups (4B/5B), scrambling, serialization of scrambled
code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and
then driving the MLT3 code into the category 5 Unshielded Twisted Pair cable through an isolation transformer
with the turns ratio of 1:1.
Data code-groups Encoder: In normal MII mode application, the device receives nibble type 4B data viathe TxD0~3 inputs of the MII. These inputs are sampled by the device on the rising edge of Tx-clk and
passed to the 4B/5B encoder to generate the 5B code-group used by 100BASE-TX.
Idle code-groups: In order to establish and maintain the clock synchronization, the device needs to keeptransmitting signals to the medium. The device will generate Idle code-groups for transmission when there
is no real data want to be sent by MAC.
Start-of-Stream Delimiter-SSD (/J/K/): In a transmission stream, the first 16 nibbles are MAC preamble.In order to let partner delineate the boundary of a data transmission sequence and to authenticate carrier
events, the device will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups.
End-of-Stream Delimiter-ESD (/T/R/): In order to indicate the termination of the normal data transmis-sions, the device will insert 2 nibbles of /T/R/ code-group after the last nibble of FCS.
Scrambling: All the encoded data(including the idle, SSD, and ESD code-groups) is passed to the datascrambler to reduce the EMI and spread the power spectrum using a 10-bit scrambler seed loaded at the
beginning.
Data conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3: After scrambled, the transmissiondata with 5B type in 25MHz will be converted to serial bit stream in 125MHz by the parallel to serial func-
tion. After serialized, the transmission serial bit stream will be further converted from NRZ to NRZI format.
This NRZI conversion function can be bypassed, if the bit 7 of PR19 register is cleared as 0. After NRZI
converted, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3
code. With this MLT3 code, it lowers the frequency and reduces the energy of the transmission signal in
the UTP cable and also makes the system easily to meet the FCC specification of EMI.
Wave-Shaper and Media Signal Driver: In order to reduce the energy of the harmonic frequency of trans-mission signals, the device provides the wave-shaper prior to the line driver to smooth but keep symmetric
the rising/falling edge of transmission signals. The wave-shaped signals include the 100BASE-TX and
10BASE-T both are passed to the same media signal driver. This design can simplify the external magnetic
connection with single one.
7.2 100BASE-TX Receiving OperationRegarding the 100BASE-TX receiving operation, the device provides the receiving functions of PMD, PMA, and
PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with turns
ratio of 1: 1. It includes the adaptive equalizer and baseline wander, data conversions of MLT3 to NRZI, NRZI
to NRZ and serial to parallel, the PLL for clock and data recovery, the de-scrambler, and the decoder of 5B/4B.
Adaptive Equalizer and Baseline Wander: Since the high speed signals over the unshielded (or shield-ed) twisted Pair cable will induce the amplitude attenuation and phase shifting. Furthermore, these effects
are depends on the signal frequency, cable type, cable length and the connectors of the cabling. So a re-
liable adaptive equalizer and baseline wander to compensate all the amplitude attenuation and phase shift-
ing are necessary. In the transceiver, it provides the robust circuits to perform these functions.
