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STD95NH02LSTN/a25200avaiN-CHANNEL 24V
STD95NH02L-1 |STD95NH02L1STN/a1425avaiN-CHANNEL 24V
STD95NH02LT4STN/a25200avaiN-CHANNEL 24V


STD95NH02LT4 ,N-CHANNEL 24VFeatures Figure 1: PackageTYPE V R IDSS DS(on) DSTD95NH02L 24 V < 0.005Ω 80(*) A

STD95NH02L-STD95NH02L-1-STD95NH02LT4
N-CHANNEL 24V
1/11September 2004
STD95NH02L

N-CHANNEL 24V - 0.0039Ω - 80A DPAK
ULTRA LOW GATE CHARGE STripFET™ MOSFET
Rev. 2
STD95NH02L
2/11
Table 3: Absolute Maximum ratings

(1) Garanted when external Rg = 4.7 Ω and tf < tf max.
(2) Pulse width limited by safe operating area.
(3) Starting Tj = 25°C, ID = 40A, VDD = 22V
(*) Value limited by wires
Table 4: Thermal Data
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 5: On/Off
3/11
STD95NH02L
ELECTRICAL CHARACTERISTICS (CONTINUED)
Table 6: Dynamic
Table 7: Source Drain Diode

(4). Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(5). Qoss = Coss*Δ Vin, Coss = Cgd+Cds. See Appendix A.
(6). Gate charge for Syncronous Operation.
STD95NH02L
4/11
Figure 3: Safe Operating Area
Figure 4: Output Characteristics
Figure 5: Transconductance
Figure 6: Thermal Impedance
Figure 7: Transfer Characteristics
Figure 8: Static Drain-source On Resistance
5/11
STD95NH02L
Figure 9: Gate Charge vs Gate-source Voltage
age vs Temperature
Figure 11: Dource-Drain Diode Forward Char-
acteristics
Figure 12: Capacitance Variations
Figure 13: Normalized On Resistance vs Tem-
perature
Figure 14: Normalized Breakdown Voltage vs
Temperature
STD95NH02L
6/11
Figure 15: Unclamped Inductive Load Test Cir-
cuit
Figure 17: Test Circuit For Inductive Load
Switching and Diode Recovery Times
Figure 18: Unclamped Inductive Wafeform

Figure 19: Gate Charge Test Circuit

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