STD2NK70Z ,N-CHANNEL 700 VFeatures Figure 1: PackageTYPE V R I PwDSS DS(on) D STD2NK70Z 700 V 7 Ω 1.6 A 45 WSTD2NK70Z-1 700 V ..
STD2NK70ZT4 ,N-CHANNEL 700 VAbsolute Maximum ratingsSymbol Parameter Value UnitV Drain-source Voltage (V = 0)DS GS 700 VV Drain ..
STD2NK90Z ,N-CHANNEL 900VAPPLICATIONS
STD2NK70Z-STD2NK70ZT4
N-CHANNEL 700 V
1/12January 2005
STD2NK70Z - STD2NK70Z-1N-CHANNEL 700 V - 6 Ω - 1.6 A DPAK/IPAK
Zener-Protected SuperMESH™ MOSFET
Table 1: General Features TYPICAL RDS(on) = 6 Ω EXTREMELY HIGH dv/dt CAPABILITY ESD IMPROVED CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED
DESCRIPTIONThe SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding application. Such series
complements ST full range of high vltage MOS-
FETs including revolutionary MDmesh™ products.
APPLICATIONS SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL
APPLICATION WELDING EQUIPMENT FLYBACK CONFIGURATION FOR BATTERY
CHARGER
Table 2: Order Codes
Figure 1: Package
Figure 2: Internal Schematic DiagramRev. 2
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Table 3: Absolute Maximum ratings(*) Pulse width limited by safe operating area
(1) ISD ≤ 1.6 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS
Table 4: Thermal Data
Table 5: Avalanche Characteristics
Table 6: Gate-Source Zener Diode
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODESThe built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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STD2NK70Z - STD2NK70Z-1
TABLE 7: ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
On /Off
Table 8: Dynamic
Table 9: Source Drain Diode (1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
(2) Pulse width limited by safe operating area
(3) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
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Figure 3: Safe Operating Area
Figure 4: Output Characteristics
Figure 5: Transconductance
Figure 6: Thermal Impedance
Figure 7: Transfer Characteristics
Figure 8: Static Drain-source On Resistance
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STD2NK70Z - STD2NK70Z-1
Figure 9: Gate Charge vs Gate-source Voltage
Figure 10: Normalized Gate Thereshold Volt-
age vs Temperature
Figure 11: Dource-Drain Diode Forward Char-
acteristics
Figure 12: Capacitance Variations
Figure 13: Normalized On Resistance vs Tem-
perature
Figure 14: Normalized Breakdown Voltage vs
Temperature
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Figure 15: Maximum Avalanche Energy vs
Temperature
