STD29NF03L-T4 ,N-CHANNEL 30VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 30 VDS GSV Drain- ..
STD2HNK60Z ,N-channel 600 V, 4.4 Ohm, 2 A Zener-protected SuperMESH(TM) Power MOSFET in DPAK packageElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 5. On/off statesSymbol P ..
STD2HNK60-Z-1 ,N-CHANNEL 600VFEATURES OF GATE-TO-SOURCE ZENER DIODESThe built-in back-to-back Zener diodes have specifically bee ..
STD2HNK60Z-1 ,N-CHANNEL 600VAPPLICATIONS
STD29NF03LT4-STD29NF03L-T4
N-CHANNEL 30V
1/10February 2002
STD29NF03LN-CHANNEL 30V - 0.015 Ω - 29A IPAK/DPAK
LOW GATE CHARGE STripFET™II POWER MOSFET TYPICAL RDS(on) = 0.015Ω OPTIMAL RDS(on) x Qg TRADE-OFF CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX “-1") SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX “T4")
DESCRIPTIONThis application specific Power MOSFET shows the best
trade-off between on-resistance and gate charge. When
used as high and low side in buck regulators, it give the
best performance in terms of both conduction and
switching losses. This is extremely important for
motherboards where fast switching and high efficiency
are of paramount importance.
APPLICATIONS SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS
ABSOLUTE MAXIMUM RATINGS(•) Current limited by the package (••) Pulse width limited by safe operating area.
(1) Starting Tj = 25 oC, ID = 15 A, VDD = 15 V
INTERNAL SCHEMATIC DIAGRAM
STD29NF03L
THERMAL DATA
ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified)OFF
ON (*)
DYNAMIC
3/10
STD29NF03LSWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
(*)Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %.
(•)Pulse width limited by safe operating area.
ELECTRICAL CHARACTERISTICS (continued) Thermal Impedance
STD29NF03L
5/10
STD29NF03LNormalized Gate Threshold Voltage vs Temperature Thermal Impedance .
STD29NF03L
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times
