STA5620A ,Automotive Fully integrated RF front-end receiver for GPS applicationsElectrical characteristics . . . . . . 125 Pin and I/O cells . . . . 155.1 Mode . . ..
STA5620A ,Automotive Fully integrated RF front-end receiver for GPS applicationsFeatures■ Low IF architecture (f = 4f )IF O■ Minimum external components■ VGA gain internally regul ..
STA575 ,100+100W STEREO BASH POWER AMPLIFIERSTA575100+100W STEREO POWER AMPLIFIERPRODUCT PREVIEW■ MONOCHIP BRIDGE STEREO AMPLIFIER ®ON BASH ARC ..
STA6610 , Dual N-Channel E nhancement Mode F ield E ffect Transistor
STA7360 ,20W BRIDGE/STEREO AUDIO AMPLIFIER WITH CLIPPING DETECTORSTA736020W BRIDGE/STEREO AUDIO AMPLIFIERWITH CLIPPING DETECTOR■ VERY FEW EXTERNAL COMPONENTS■ NO BO ..
STA801 , 2-Output Separate Excitation Switching Type
STTH2002CG-TR ,HIGH EFFICIENCY ULTRAFAST DIODEapplications.ABSOLUTE RATINGS (limiting values)Symbol Parameter Value UnitV Repetitive peak reverse ..
STTH2002CG-TR ,HIGH EFFICIENCY ULTRAFAST DIODEELECTRICAL CHARACTERISTICS (per diode)Symbol Parameter Tests conditions Min. Typ. Max. UnitI * Reve ..
STTH2002CR ,HIGH EFFICIENCY ULTRAFAST DIODEapplications.ABSOLUTE RATINGS (limiting values)Symbol Parameter Value UnitV Repetitive peak reverse ..
STTH2002CT ,HIGH EFFICIENCY ULTRAFAST DIODEFEATURES AND BENEFITSA2A2KK■ Suited for SMPSA1A12■ Low lossesTO-220AB I PAK■ Low forward and revers ..
STTH2003C , Hight frequency secondary rectifier
STTH2003CFP ,HIGH FREQUENCY SECONDARY RECTIFIER®STTH2003CT/CG/CF/CR/CFPHIGH FREQUENCY SECONDARY RECTIFIERMAJOR PRODUCT CHARACTERISTICSK A1KI 2x10A ..
STA5620A
Automotive Fully integrated RF front-end receiver for GPS applications
September 2013 Doc ID 14424 Rev 4 1/29
A5620A A5620CFully integrated RF front-end receiver for GPS applications
Features Low IF architecture (fIF = 4fO) Minimum external components VGA gain internally regulated On chip programmable PLL Typ. 2.7 V supply voltage SPI interface2 kV HBM ESD protected Compatible with GPS L1 Standard QFN-32 package Low power for portable designs
DescriptionThe chip is a fully integrated RF front-end able to
down-convert the GPS L1 signal from
1575.42 MHz to 4.092 MHz.
The IF signal is converted by a two bit ADC. Sign
(SIGN), Magnitude (MAG) and the 16.368 MHz
sampling clock (GPS_CLK) are provided to the
baseband.
The magnitude data is internally integrated in
order to control the variable gain amplifiers in
accordance to the RF input signal strength.
An excellent quality of reception in critical
environments is ensured by the good noise figure
and linearity of the receiver.
The on-chip oscillator supports crystal
frequencies in the range of 10 MHz to 40 MHz. It
is able to support TCXO providing also a buffered
copy of the oscillator frequency.
The chip, using STMicroelectronics BiCMOS
SiGe technology, is housed in a QFN-32 package.
Table 1. Device summary Automotive grade.
Contents STA5620A, STA5620C2/29 Doc ID 14424 Rev 4
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.1 RFA and MIXER section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 IF section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Variable gain amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 PLL synthesizer and VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 Output buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.9 Power control modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin and I/O cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155.1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 RF_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 CHIP_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.4 TEST_EN1, TEST_EN2 and TEST_CLK . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPI bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166.1 SPI_CS/ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 SPI_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 SPI_DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.4 SPI_DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STA5620A, STA5620C Contents
Doc ID 14424 Rev 4 3/29
7.1 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2 PLL N divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3 PLL R divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4 Radio configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.5 T est register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6 Debug register (sub-circuit enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.7 Radio trimming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.8 Receiver chain register (enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chip enable and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.2 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
List of tables STA5620A, STA5620C
4/29 Doc ID 14424 Rev 4
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pins list description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. PLL N divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. PLL R divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Radio configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Debug register (sub-circuit enables). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. Radio trimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Receiver chain register (enable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Default configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STA5620A, STA5620C List of figures
Doc ID 14424 Rev 4 5/29
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pins connection diagram (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SPI byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. SPI byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Chip enable and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6. VFQFPN32 (5x5x1.0 mm) mechanical data and package dimensions . . . . . . . . . . . . . . . 25
Figure 7. Reel, leader and trailer dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Carrier tape requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Block diagram STA5620A, STA5620C
6/29 Doc ID 14424 Rev 4
1 Block diagram
Figure 1. Block diagram
STA5620A, STA5620C Pins description
Doc ID 14424 Rev 4 7/29
2 Pins description
Table 2. Pins list description
Pins description STA5620A, STA5620C Doc ID 14424 Rev 4
Figure 2. Pins connection diagram (bottom view)
STA5620A, STA5620C Functional description
Doc ID 14424 Rev 4 9/29
3 Functional description
3.1 RFA and MIXER section
The 1575.42 MHz RF signal at the output of the external SAW filter is amplified by a RF
amplifier (RFA) and then down converted by an image rejection mixer.
The good performances of the cascade configuration and the technology choice guarantee
a noise figure better than 4.5 dB in typical conditions. In fact, the RFA gain is high enough to
minimize the effects on the noise figure of the following integrated stages.
The linearity of the RFA and Mixer section ensures immunity to RF blockers close to the
GPS signal. Then it allows the use of low quality external pre-selection filters. wo ninety degrees out of phase signals are derived from the VCO and send to the input of
the image rejection mixer. A minimum image rejection ratio of 20 dB is guaranteed.
The chosen IF frequency is 4fo = 4.092 MHz.
3.2 IF section
The output of the mixer combiner is processed through an integrated filter able to select the
GPS L1 bands. The IF filter cuts any out-of-band signal including the mixer products. In
addition it acts as an anti-aliasing filter for the A/D converter. An attenuation of 20 dB is
guaranteed at 12fo = 12.276 MHz.
The IF filter characteristic is calibrated by an internal loop which compensates process,
temperature and voltage variations.
In order to let the baseband reconstruct the received information, the IF filter must not
introduce an excessive phase shift within the signal bandwidth.
3.3 Variable gain amplifiers
A cascade of variable gain amplifiers and the relevant control circuit balance the system
gain in relationship to the RF input signal strength. In that way the signal level at the input of
the A/D converter is suitably compensated.
The device is able to self-adjust the AGC gain by integrating the MAG output by a dedicated
circuit in order to obtain 33 % of MAG bit duty cycle. The loop is compensated by an
external capacitor connected to the AGC_CTRL pin. The relevant voltage is used to control
the variable gain amplifiers.
The internal loop can be by-passed by setting a voltage to the AGC_CTRL input pin. A
dynamic range of around 55 dB is typically achieved.
3.4 A/D converter
The task of the A/D converter is to determine the sign and the magnitude of the received
signal. The A/D converter sampling frequency is 16fo = 16.368 MHz.
Those baseband chips with just one bit input will use only the sign bit. In that case the
AGC_CTRL pin must be connected to ground through an external capacitor (~ 10 µF).
Functional description STA5620A, STA5620C
10/29 Doc ID 14424 Rev 4
3.5 PLL synthesizer and VCO
The PLL synthesizer is fully integrated on-chip, it is made by the voltage controlled oscillator
(VCO), prescaler, dividers, phase-frequency detector (PFD), charge pump (CP) and loop
filter. Both the reference divider R and the feedback divider N are programmable helping the
user to choose the reference clock. The R divider ranges from 1 to 63 while the N divider
from 56 to 4095.
In order to achieve good phase noise performances, a LC voltage controlled oscillator has
been chosen. Quadrature signals are provided by means of a polyphase filter.
A programmable loop filter is integrated on-chip to reduce the number of external
components. The loop stability is guaranteed for any of the supported crystals and
comparison frequencies.
The charge pump is programmable and the output current can be selected among the
following values: 50 µA, 100 µA, 150 µA and 200 µA.
3.6 Crystal oscillator
The reference oscillator circuit is a CMOS inverter able to work with external crystals up to MHz. The crystal must be connected between the xtal input and the xtal output pins. The
load capacitances must be chosen in accordance to the values specified by the crystal
manufacturer. A limiting resistor can be placed at the output of the inverter in order to
contain the power dissipated in the crystal within its specified maximum value.
When a TCXO is used the external reference clock must be applied to the XTAL_IN
terminal.
3.7 Output buffers
The RF front-end provides a set of four different signals to the baseband chip.
The SIGN and the MAG outputs are the sampled bit streams of the down-converted
received signal.
GPS_CLK, nominally equal to 16.368 MHz, is the clock signal used by the baseband. Its
source can be chosen among the crystal oscillator signal and the VCO signal by means of a
96 divider.
XTAL_CLK is the buffered copy of either the crystal oscillator or the TCXO signal.
In order to let the application find the best compromise between electro-magnetic
interferences and the drivers speed, the output stages slew-rate can be programmed by
SPI, except for XTAL_CLK and SPI_DO that have always a fast slew-rate.
3.8 SPI interface
A SPI interface manages the communication between the baseband chip and the RF front-
end. Four lines are required to accomplish this task: a data input line (SPI_DI), a data output
line (SPI_DO), a clock line (SPI_CLK) and a chip select line (SPI_CS/) active low.
Any information can be passed to the RF receiver through the SPI interface depending on
the CHIP_EN and RF_EN input pins status.
STA5620A, STA5620C Functional description
Doc ID 14424 Rev 4 11/29
3.9 Power control modes
Three different power control modes can be chosen by means of the CHIP_EN and the
RF_EN pins. If the CHIP_EN pin is forced low the device goes to standby mode with very
low power consumption. On the other hand, if CHIP_EN is set high, two scenarios are
possible: IIf RF_EN = 0 the crystal oscillator and only one output buffer are enabled, AL_CLK if MODE = 1 or GPS_CLK if MODE = 0;
2. If RF_EN = 1 the whole chip is active and functional.
Only if MODE = 0 the XTAL_CLK output is disabled.
A logic reset of the SPI registers is generated by the low to high transitions of the CHIP_EN
pin. External pin strapping dominates until some SPI commands reverse the priority and
overrides the strapping until next reset.
Electrical specifications STA5620A, STA5620C
12/29 Doc ID 14424 Rev 4
4 Electrical specifications
4.1 Absolute maximum ratings
4.2 Thermal data
4.3 Electrical characteristics
Table 3. Absolute maximum ratings
Table 4. Thermal data
Table 5. Electrical characteristics
(VCC = 2.7V , TJ = 25 °C unless otherwise noted)
STA5620A, STA5620C Electrical specifications
Doc ID 14424 Rev 4 13/29
Table 5. Electrical characteristics (continued)
(VCC = 2.7V , TJ = 25 °C unless otherwise noted)
Electrical specifications STA5620A, STA5620C
14/29 Doc ID 14424 Rev 4 This value is guaranteed by design. Simulation data.
Table 5. Electrical characteristics (continued)
(VCC = 2.7V , TJ = 25 °C unless otherwise noted)
STA5620A, STA5620C Pin and I/O cells
Doc ID 14424 Rev 4 15/29 Pin and I/O cells
5.1 Mode
This pin allows a choice of initial configuration of the registers at reset. This pin will always
be an input. In application this pin will be connected either LO or HI.
When it is low the chip is configured to use 16.368 MHz as reference frequency, otherwise
the reference frequency is 19.2 MHz. T o use other reference frequencies the MODE bit must
be overwritten by SPI.
5.2 RF_EN
This pin provides control over the operating state of the RF and PLL sections. When it is low
those blocks are off, when high the status of the blocks depends of CHIP_EN. This pin will
always be an input.
5.3 CHIP_EN
This pin provides control over the operating state of the chip. When it is low the entire chip is
disabled and only a leakage current is present (< 10 µA). On the rising edge it provides the
SPI with a reset signal, the SPI default status depends on MODE and RF_EN pins status.
When it is high the entire chip is enabled. This pin will always be an input.
5.4 TEST_EN1, TEST_EN2 and TEST_CLK
Those PINs are for ST test only. In the application TEST_EN1 must be set LOW, TEST_EN2
must be set HIGH (VCC_IO) and TEST_CLK must be not connected.
