STA529Q ,2 x 100 mW class-D amplifer with analog or digital input, 2.0 multichannel digital audio processor with FFXApplications scheme 272/57 Doc ID 13095 Rev 3STA529 Contents7.4 Configuration examples . ..
STA530 ,4X30W STEREO BASH POWER AMPLIFIERBLOCK DIAGRAMGND +V -V PWR_INP1 STBY/MUTE PWR_INP3S SCD+1&2 CD+3&4TURN-ON/OFFSEQUENCEOUT1+ OUT3++10 ..
STA533WF ,18 V, 3 A quad power half-bridgeAbsolute maximum ratingsSymbol Parameter Value UnitV DC supply voltage (Pins 4, 7, 12, 15) 23 VCCV ..
STA533WF13TR ,18 V, 3 A quad power half-bridgeElectrical characteristics Symbol Parameter Test conditions Min Typ Max UnitP Output power in BTL m ..
STA533WF13TR ,18 V, 3 A quad power half-bridgeFeatures■ Multipower BCD technology■ Low input/output pulse width distortion■ 200-mΩ R complementar ..
STA540 ,4 x 13 W dual/quad power amplifierFeatures■ High output power capability– 2x 38 W into 4 Ω at 18 V, 1 kHz, 10% THD– 2x 34 W into 8 Ω ..
STTH16R04CFP , Ultrafast recovery diode
STTH16R04CT ,Ultrafast recovery diodesFeatures and benefitsSTTH16R04CT STTH16R04CFP■ Very low switching losses■ High frequency and/or hig ..
STTH1L06 ,TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIERELECTRICAL CHARACTERISTICSSymbol Parameter Tests conditions Min. Typ. Max. UnitI Reverse leakage V ..
STTH1L06A ,TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIERapplications.ABSOLUTE RATINGS (limiting values)Symbol Parameter Value UnitV Repetitive peak reverse ..
STTH1L06U ,TURBO 2 ULTRAFAST HIGH VOLTAGE RECTIFIERFEATURES AND BENEFITSn Ultrafast switchingn Low reverse recovery currentn Reduces switching & condu ..
STTH1R02 ,Ultrafast recovery diodeFeatures and benefitsDO-15DO-41KK■ Very low conduction lossesSTTH1R02QSTTH1R02■ Negligible switchin ..
STA529-STA529Q
2 x 100 mW class-D amplifer with analog or digital input, 2.0 multichannel digital audio processor with FFX
March 2012 Doc ID 13095 Rev 3 1/57
A529FFX™ audio codec with analog and digital inputs
and 2 x 1.2 W (or 2 x 100 mW HP) class-D amplifier
Datasheet − production data
Features Up to 96 dB dynamic range Sample rates from 8 kHz to 192 kHz FFX™ class-D driver 1.55 V to 1.95 V digital power supply 1.80 V to 3.60 V analog and I/O power supply 18-bit audio processing and class-D FFX™
modulator >90-dB SNR analog-to-digital converter Digital volume control: +36 dB to -105 dB in 0.5-dB steps Software volume update 16-bit ADC Individual channel and master gain/attenuation Automatic invalid input detect mute 2-channel I2 S input/output data interface Digitally controlled pop-free operation 90% efficiency Output power for stereo headphones or stereo
speakers applications (at THD = 10% and
VCC= 3.3 V): 45 mW with 32-Ω headphones 85 mW with 16-Ω headphones 720 mW with 8-Ω speakers 1.1 W with 4-Ω speakers
Applications Portable devices Laptops Digital cameras Microless applications
Table 1. Device summary
Contents STA5292/57 Doc ID 13095 Rev 3
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Connection diagrams and pin descriptions . . . . . . . . . . . . . . . . . . . . . . 82.1 TFBGA48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 VFQFPN52 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical and thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.1 SELCLK33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185.1 Signal processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 I2 C interface disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Volume control and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3 Set fractional PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257.1 ADC performance values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2.1 Digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.2 High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2.3 Programmable gain amplifier (PGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.3 Applications scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STA529 ContentsDoc ID 13095 Rev 3 3/57
7.4 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288.1 I2 S bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299.1 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.2 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3 Serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.3.1 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3.2 I2 S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3.3 PCM/IF (non-delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.3.4 PCM/IF (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I2 C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3410.1 Data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.6 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.6.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.6.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.7.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3711.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.2 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5312.1 Package TFBGA48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.2 Package VFQFPN52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Contents STA5294/57 Doc ID 13095 Rev 3
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STA529 List of figures
Doc ID 13095 Rev 3 5/57
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Connection diagram for TFBGA48 (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Connection diagram for VFQFPN52 (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Circuit for crystal drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Diagram of input coupling and supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Right justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. Left justified. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13.I2 S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14. PCM/IF (non delayed mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15. PCM/IF (delayed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16.I2 C write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17.I2 C read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. Package outline (TFBGA48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 19. Package outline (VFQFPN52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
List of tables STA529
6/57 Doc ID 13095 Rev 3
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description for TFBGA48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Pin description for VFQFPN52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8. Load power at 1% distortion in headphone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Load power at 10% distortion in headphone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Load power at 1% distortion in speaker mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Load power at 10% distortion in speaker mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. PLL lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Master volume offset as a function of register MVOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. Channel volume as a function of registers LVOL and RVOL . . . . . . . . . . . . . . . . . . . . . . . 19
Table 15. Oversampling table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Programmable gain performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. Digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18. High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. Pin functions in driver-configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. Slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23. Package dimensions (TFBGA48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 24. Package dimensions (VFQFPN52). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
STA529 Description
Doc ID 13095 Rev 3 7/57
1 Description
The STA529 is a digital stereo class-D audio amplifier. It includes an audio DSP , an ST
proprietary high-efficiency class-D driver and CMOS power output stage. It is intended for
high-efficiency digital-to-power-audio conversion for portable applications. The STA529 also
provides output capabilities for FFX™ . In conjunction with a power device, the STA529
provides high-quality digital amplification.
The STA529 contains an on-chip volume/gain control.
The PWM amplifier achieves greater than 90% efficiency for longer battery life for portable
systems.
The innovative class-D modulation, allows the STA529 to work without external LC filters
and without a heatsink.
The STA529 I2CDIS pin disables the audio DSP functions and the I2 C interface provides a
direct conversion of the input signal into output power. This conversion is done without the
microcontroller.
The STA529 is designed for low-power operation with extremely low-current consumption in
standby mode. It is available in packages TFBGA48 and VFQFPN52. These are very thin
packages (1.2 mm thick) ideal for small portable applications.
Figure 1. Block diagram
Connection diagrams and pin descriptions STA529
8/57 Doc ID 13095 Rev 3 Connection diagrams and pin descriptions
This section includes connection diagrams and pin descriptions for the following packages: TFBGA48 VFQFPN52
2.1 TFBGA48 package
Figure 2. Connection diagram for TFBGA48 (bottom view)
Table 2. Pin description for TFBGA48
STA529 Connection diagrams and pin descriptions
Doc ID 13095 Rev 3 9/57
Table 2. Pin description for TFBGA48 (continued)
Connection diagrams and pin descriptions STA529
10/57 Doc ID 13095 Rev 3
2.2 VFQFPN52 package
Figure 3. Connection diagram for VFQFPN52 (bottom view)
Table 2. Pin description for TFBGA48 (continued)
Table 3. Pin description for VFQFPN52
STA529 Connection diagrams and pin descriptions
Doc ID 13095 Rev 3 11/57
Table 3. Pin description for VFQFPN52 (continued)
Connection diagrams and pin descriptions STA529
12/57 Doc ID 13095 Rev 3
Table 3. Pin description for VFQFPN52 (continued)
STA529 Electrical and thermal specifications
Doc ID 13095 Rev 3 13/57 Electrical and thermal specifications
3.1 Thermal data
3.2 Absolute maximum ratings
Note: All grounds must be within 0.3 V of each other.
Table 4. Thermal data
Table 5. Absolute maximum ratings
Electrical and thermal specifications STA529
14/57 Doc ID 13095 Rev 3
3.3 Recommended operating conditions
Table 6. Recommended operating conditions
STA529 Electrical and thermal specifications
Doc ID 13095 Rev 3 15/57
3.4 Electrical characteristics
The electrical specifications in Table 7 below are given for operation under the
recommended conditions listed in Table 6. Unless otherwise specified, LRCLKI frequency
(fs) = 48 kHz, input frequency = 1 kHz, and RLOAD = 32 Ω.
Table 7. Electrical characteristics
Electrical and thermal specifications STA529
16/57 Doc ID 13095 Rev 3
The following tables give the output power for 1% and 10% THD levels for headphones and
speakers.
3.5 Lock time
Table 12 gives the typical lock time of the PLL using the suggested loop filter with 1.8V
supply and 30o C junction temperature.
Table 8. Load power at 1% distortion in headphone mode
Table 9. Load power at 10% distortion in headphone mode
Table 10. Load power at 1% distortion in speaker mode
Table 11. Load power at 10% distortion in speaker mode
Table 12. PLL lock time
STA529 Input clock
Doc ID 13095 Rev 3 17/57
4 Input clock
4.1 SELCLK33
In STA529 the oversampling clock comes from MCLK33 or from pin XTI. The selection is
done by applying the appropriate voltage to pin SELCLK33. If SELCLK33 is logical 1 then
MCLK33 is selected, otherwise XTI is selected.
If an external crystal is used, SELCLK33 pin must be connected to GND and the suggested
circuit shown below should be used.
Figure 4.
Digital processing STA529
18/57 Doc ID 13095 Rev 3
5 Digital processing
The STA529 processor block is a digital block providing two channels of audio processing
and channel-mapping capability.
5.1 Signal processing flow2 S or stereo ADC data can be selected. The I2 S frequency range is 8 kHz to 192 kHz. The
ADC sampling frequency can be selected between 8 kHz and 48 kHz.
5.2 I2 C interface disable
When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low
to change certain parameters of operation. SDA = 0: FFX input comes from ADC
SDA = 1: FFX input comes from digital audio interface SCL = 0: binary output mode (binary soft start/stop enabled)
SCL = 1: phase shift output mode LRCLKO = 0: no volume change
LRCLKO = 1: channel volume up on both channel BICLKO = 0: no volume change
BICLKO = 1: channel volume down on both xchannel.
At power up, the channel volume is set to -60 dB. When holding pin LRCLKO = 1 and pin
BICLKO = 1 simultaneously, the channel volume is set to 0 dB. A high pulse on pin LRCLKO
causes a channel volume change of +0.5 dB and a high pulse on pin BICLKO causes a
channel volume change of -0.5 dB.
STA529 Digital processing
Doc ID 13095 Rev 3 19/57
5.3 Volume control and gain
The volume control structure of the STA529 consists of individual volume registers for each
channel and a master volume register that provides an offset to each channel’s volume
setting. The individual channel volumes are adjustable in 0.5-dB steps from +36 dB -91.5 dB. As an example, if register LVOL = 0x00 or +36 dB and register MVOL = 0x18 -12 dB, then the total gain for the left channel is +24 dB.
When the mute bit is set to 1, all channels are muted. The volume control provides a soft
mute with the volume ramping down to mute in 4096 samples from the maximum volume
setting at the internal processing rate (around 48 kHz).
Table 13. Master volume offset as a function of register MVOL
Table 14. Channel volume as a function of registers LVOL and RVOL
PLL STA529
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6 PLL
Figure 5 shows the main components of the PLL.
Figure 5. PLL block diagram
6.1 Functional description
Phase/frequency detector
The phase/frequency detector (PFD) compares the phase difference between the
corresponding rising edges of INFIN and FBCLK, (clock output from the loop frequency
divider) by generating voltage pulses with widths proportional to the input phase error.
Charge pump and loop filter
This block converts the voltage pulses from the phase/frequency detector to current pulses
which charge the loop filter and generate the control voltage for the voltage-controlled
oscillator. The loop filter is placed external to the PLL on pin FILT.
Voltage controlled oscillator
The voltage controlled oscillator (VCO) is the oscillator inside the PLL. It produces a
frequency (f VCO ) proportional to the input control voltage.
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Input frequency divider
This frequency divider divides the PLL input clock CLKIN by a factor called the input division
factor (IDF) to generate the PFD input frequency INFIN.
Loop frequency divider
This frequency divider is present within the PLL for dividing fVCO by a factor called the loop
division factor (LDF). The output of this block is clock FBCLK.
Output frequency divider
The output frequency divider divides fVCO by the output division factor (ODF) to produce the
output clock PHI and the clock to the core. In the ST A529, ODF = 2 and cannot be
reconfigured.
Lock-detect circuit
The output of this block (signal LOCKP) is asserted high when the PLL enters the state of
Coarse Lock in which the output frequency is within ±10%, approximately, of the desired
frequency. LOCKP is refreshed every 32 cycles of clock INFIN. The generated value is
based on the result of comparing the number of FBCLK cycles in a window of 14 INFIN
cycles. The different cases generated after comparison are as follows. If LOCKP is already at 0, then in the next refresh cycle LOCKP goes to 1 if the number
of FBCLK cycles in the 14-cycle INFIN window is 13, 14, or 15. Otherwise LOCKP
stays at 0. If LOCKP is already at 1, then in the next refresh cycle LOCKP goes to 0 if the number
of FBCLK cycles in the 25-cycle INFIN window is less than 11 or higher than 17,
otherwise LOCKP stays at 1. If LOCKP is already at 1 and CLKIN is lost (no longer present on the input pin), LOCKP
stays at 1. In this case, the PLL is unlocked.
PLL filter
Figure 6 below shows the PLL filter circuit. Recommended values are R1 = 12.5 kΩ, = 250 pF and C2 = 82 pF.
Figure 6. PLL filter circuit able 12 on page 16 gives a typical lock time value for the PLL.
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6.2 Configuration examples
The STA529 PLL can be configured in two ways: default startup configuration direct PLL programming
The default startup configuration reads the device defaults. With this configuration, it is not
necessary to program the PLL dividers directly as preset values are used. In this mode, the
oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256.
The direct PLL programming bypasses the automatic presets allowing direct programming
of the PLL dividers.
The output PLL frequency can be determined by the following equations.
Output division factor:
ODF = 2.
Relation between input and output clock frequency:
fINFIN = fXTI / IDF.
If register bit PLLCFG0.FRAC_CTRL = 1
fVCO = fINFIN * (LDF + FRACT / 216 + 1 / 217)
fPHI = fVCO / ODF.
When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/217 factor is not in the
multiplication. This is recommended in order to keep register bit
PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output
clock spectrum.
If register bit PLLCFG0.FRAC_CTRL = 0, then:
fVCO = fINFIN * LDF
fPHI = fVCO / ODF.
In the above equations:
FRACT = decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0]
IDF = input division factor
LDF = loop division factor
ODF = output division factor = 2
fINFIN = INFIN frequency
fXTI = XTI frequency
fVCO = VCO frequency
fPHI = frequency of the PLL output clock.
When selecting the values for IDF , LDF and FRACT, ensure that the following limits are
maintained:
2.048 MHz < fXTI < 49.152 MHz
2.048 MHz < fINFIN < 16.384 MHz
65.536 MHz < fVCO < 98.304 MHz
There are also some additional constraints on IDF and LDF . IDF should be greater than 0,
LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1.
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When automatic settings are not used, the PLL must be configured to generate an internal
frequency, fPHI, of N * fs, where fs is the frequency of pin LRCLKI. Values for N are given in
Table 15.
Example 1
fXTI = 13 MHz and fs = 44.1 kHz
IDF should be equal to 3 otherwise LDF becomes less than 8 (FRAC_CTRL must be 1):
LDF = floor(45.1584 / (13 / IDF)) = 10
FRACT = round([(45.1584 / (13 / IDF)) - floor(45.1584 / (13 / IDF))] * 216 ) = 27602.
where:
floor means rounded down and
round means rounded to nearest integer.
Using the above configuration, the system clock is 45.15841675 MHz, the approximate
static error is 16 Hz (that is, 0.5 ppm).
Example 2
fXTI = 19.2 MHz and fs = 48 kHz
IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1):
LDF = floor(49.152 / (19.2 / IDF)) = 10
FRACT = round([(49.152 / (19.2 / IDF)) - floor(49.152 / (19.2 / IDF))] * 216 ) = 15728.
Using the above configuration, the system clock is 49.151953125 MHz, the approximate
static error is 47 Hz (that is, 1 ppm).
Table 15. Oversampling table
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6.3 Set fractional PLL
The following procedure is mandatory to configure the fractional PLL: Set bit D7 reg 0x18 ( PLL_BYP_UNL) to "1"
2. Write reg 0x17 (PLLCFG3)
3. Write reg 0x14 (PLLCFG0)
4. Write reg 0x15 (PLLCFG1)
5. Write reg 0x16 (PLLCFG2)
6. Set bit D7 reg 0x18 ( PLL_BYP_UNL) to "0"
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7 ADC
7.1 ADC performance values
7.2 Functional description
The STA529 analog input is provided through a low-power, low-voltage, 16-bit stereo audio
analog-to-digital converter front end designed for audio applications. It includes a
programmable gain amplifier, anti-aliasing filter, low-noise microphone biasing circuit,
third-order MASH2-1 delta-sigma modulator, digital decimating filter and a first-order
DC-removal filter.
The ADC works in the microphone input (mic-in) mode and in the line-input mode. If the line
input mode is selected, the ADC is configured in stereo and all conversion channels are
active.
If the microphone input mode is selected, the ADC is configured in mono. The mono
channel is routed through the left conversion path, and the right conversion path is kept in
power-down mode to minimize power consumption. A programmable gain amplifier (PGA) is
available in mic-in mode, making it possible to amplify the signal from 0 to +42 dB in steps of
6dB.
Table 16. Programmable gain performance
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7.2.1 Digital filter characteristics
7.2.2 High-pass filter characteristics
7.2.3 Programmable gain amplifier (PGA)
The PGA is available in mic-in mode only. The input signal can be amplified from 0 to 42 dB
in 6-dB steps via bits PGA of register ADCCFG on page 49.
Table 17. Digital filter characteristics
Table 18. High-pass filter characteristics
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7.3 Applications scheme
Figure 7. Diagram of input coupling and supply decoupling
7.4 Configuration examples
The ADC sampling frequency can be selected from three values: normal (from 32 kHz to 48 kHz) low (from 16 kHz to 24 kHz) very-low (from 8 kHz to 12 kHz)
The setting is done through bits ADC_FS_RANGE of register MISC on page 50. For all
other settings register ADCCFG on page 49 is used.
Driver configuration STA529
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8 Driver configuration
A driver configuration is available that allows PWM commands to be used on an external
power device. For this purpose, the output serial audio interface is disabled and the
respective pins have an alternative name and a new function, as shown in Table 19.
The driver configuration is selected with the two programmable registers, PWMINT1 = 0x93
and PWMINT2 = 0x81, on page 51.
8.1 I2 S bypass
A configuration is available which allows the passing of the I2 S input signal straight to the 2 S output signal.
This configuration is set using two programmable registers PWMINT1 = 0x93 and
PWMINT2 = 0x80.
Table 19. Pin functions in driver-configuration mode
STA529 Serial audio interface
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The serial-to-parallel interface and the parallel-to-serial interface can have different
sampling rates.
The following terms are used in this section: BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change
synchronously with BITCLK active edges. The active edge can be configured as a
rising or falling edge via register programming. BICLK strobe edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO should be stable near
BICLK strobe edges, the slave device is able to use strobe edges to latch serial data
internally.
9.1 Master mode
In this mode, pins BICLKI/BICLKO and pins LRCLKI/LRCLKO are configured as outputs.
Figure 8. Master mode
Table 20. Master mode
