STA310 ,6+2-CH. MULTISTANDARD AUDIO DECODERAPPLICATIONS■ Downmix for Dolby Prologic compatible.■ High-end audio equipment.❚ A separate (2-ch) ..
STA310 ,6+2-CH. MULTISTANDARD AUDIO DECODERFEATURES■ DVD Audio decoder:❚ Meridian Lossless Packing (MLP), with up to 6 channels,❚ Uncompressed ..
STA312A , NPN General purpose
STA321 ,4-channel digital audio system with FFX driverFeatures High efficiency FFX™ class-D modulator 100-dB dynamic range2 Two stereo channels with I ..
STA323W ,2.1-channel high-efficiency digital audio systemSTA323W2.1 channel high-efficiency digital audio systemDatasheet - production data Individual cha ..
STA323W13TR ,2.1-channel high-efficiency digital audio systemFeatures Input and output channel mapping Wide supply voltage range (10 V - 36 V) AM noise-redu ..
STS3C2F100 ,N-CHANNEL 100VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)jTAB.2 OFFSymbol Parameter Test Co ..
STS3C3F30L ,N-CHANNEL 30VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
STS3DNE60L ,DUAL N-CHANNEL 60VSTS3DNE60L®N - CHANNEL 60V - 0.065W - 3A SO-8STripFET
STA310
6+2-CH. MULTISTANDARD AUDIO DECODER
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STA310June 2003
FEATURES DVD Audio decoder: Meridian Lossless Packing (MLP), with up to 6 channels, Uncompressed LPCM with 1-8 channels, Precision of up to 24 bits and sample rates
of between 44.1 kHz and 192 kHz.
Dolby Digital (*)
decoder: Decodes 5.1 Dolby Digital Surround. Output up to 6 channels. downmix modes:
1, 2, 3 or 4 channels.
MPEG -1 2- channel audio decoder, layers I and II.
MPEG-2 6-channel audio decoder, layer II. 24 bits decoding precision.
MP3 (MPEG layer III) decoder. Accepts MPEG-2 PES stream format for:
MPEG-2, MPEG-1, Dolby Digital and linear
PCM.
Karaoke System. Prologic decoder. Downmix for Dolby Prologic compatible. A separate (2-ch) PCM output available for Bitstream input interface: serial, parallel or
SPDIF. SPDIF and IEC-61937 input interface. SPDIF and IEC-61937 output interface. PLL for internal PCM clock generation.
frequencies supported: 44.1KHz family (22.05,
88.2, 176.4) and 48KHz family (24, 48, 96, 192). PCM: transparent, downsampling 192 to 96 Khz
and 96 to 48kHz. PTS handling control on-chip.
No external DRAM requiredI2 C or parallel control bus Embedded Development RAM for
customizable software capability. Configurable internal PLLs for system and
audio clocks, from an externally provided clock. 80-PIN TQFP package 2.5V (for core) and 3V (for I/O) power supply. 3V Capable I/O Pads . True-SPDIF input receiver supporting AES/
EBU, IEC958, S/PDIF. No external chip required. Differential or single ended inputs can be
decoded.
APPLICATIONS High-end audio equipment. DVD consumer players. Set top box. HDTV . Multimedia PC.
(*) “Dolby “, “AC-3” and “ProLogic” are
trademarks of Dolby Laboratories.
DESCRIPTIONThe STA310 is a fully integrated Audio Decoder ca-
pable of decoding all the above listed formats.
Encoded input data can be entered either by a serial
(I2S or SPDIF) or a parallel interface. A second input
data stream (I2S) is available for micro input.
The control interface can be either I
2 C or a parallel 8-bit interface. No external DRAM is necessary for a to-
tal of 35ms surround delays.
PRELYMINARY DATA6+2-CH. MULTISTANDARD AUDIO DECODER
STA310 2/90
STA310 AUDIO DECODER PIN DESCRIPTION
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STA310 STA310 AUDIO DECODER PIN DESCRIPTION (continued)
STA310
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Notes (1) Open Drain
(2) Internal Pull-up
(3) Tri-State
PIN CONNECTION (Top view) STA310 AUDIO DECODER PIN DESCRIPTION (continued)
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STA310
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (VDD = 3.3V +/-0.3V; Tamb = 0 to 70°C; Rg = 50 Ω unless otherwise spec-
ified
GENERAL INTERFACE
Note:1. The leakage currents are generally very small, <1nA. The value given here, 1μA, is a maximum that can occur after an Electrostatic
Stress on the pin. V> Vdd3 for 3.3V buffers. Human Body Model
LVTTL & LVCMOS DC Input Specification 2.7V
Note:1. Takes into account 200mV voltage drop in both supply lines. X in the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability
STA310
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ELECTRICAL CHARACTERISTICS (continued)
Note:1. Min condition: VDD = 2.7V, 125°C Min precess Max condition: VDD = 3.6V, -20°C Max
POWER DISSIPATION
INTRODUCTION
The STA310 is a fully integrated multi-format audio decoder. It accepts as input, audio data streams coded with
all the formats listed above.
2.1 Inputs and Outputs
2.1.1 Data Inputs Through a parallel interface (shared with the control interface) Through a serial interface (for all the I2 S formats) Through a S/P DIF (SPDIF or IEC-61937 standards). Trough a second, independent,I2 S (for application like i..e. Karaoke mixing).
2.1.2 Data outputs The PCM audio ooutput interface, which provide: PCM data on 4 outputs: Left/Right, Centre/Subwoofer Left Surround/Right Surround.
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STA310 Data From a Prologic downmix (encoder) “Lrclk” “Sclk” “PcmClk” S/P DIF Output
2.1.3 Control I/F
I2C slave or parallel interface:
The device configuration and the command issuing is done via this interface. To facilitate the contact with the
MCU, 2 interrupt lines (IRQB and INTLINE) are available. ARCHITECTURE OVERVIEW
3.1 Data flow
The STA310 is based on a programmable MMDSP+ core optimized for audio decoding algorithms.
Dedicated hardware has been added to perform specific operations such as bitstream depacking or IEC data
formatting.
The arrows in Figure 3 indicate the data flow within the chip.
The compressed bitstream is input via the data input interface.
Data are transferred on a byte basis to the FIFO. This FIFO allows burst input data at up to 33Mbit/s.
The input processor, which is composed of a packet parser and an audio parser, unpacks the bitstream (Packet
parser) and verifies the syntax of the incoming stream (audio parser).
The compressed audio frames with their associated information (PTS) are stored into the circular frame buffer.
While a second frame is stored in the circular frame buffer, the first frame is extracted by the audio core decoder
which decodes it to produce audio samples.
The PCM unit converts the samples to the PCM format. The PCM unit controls also the channel delay buffer in
order to delay each channel independently.
In parallel, the IEC unit transmits non compressed data or compressed data according to the selected mode. In
the compressed mode, the data are extracted directly from the circular buffer and formatted according to the
IEC-61937 standard. In non compressed mode, the left and right PCM channels formatted by the PCM unit are
output by the IEC unit, according to the SPDIF standard
Figure 1. Architecture and data flows
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3.2 Functional diagram
Figure 2. Audio decoder top level functional diagram
3.3 Control interface description
The IC can be controlled either by a host using an I²C interface, or by a general purpose host interface.
These interfaces provide the same functions and are described in the following sections. The selection is per-
formed by the means of the pin SELI2C: when high, this pin indicates that the I²C interface is used. When low,
the parallel interface is used.
3.3.1 Parallel control interface
When the pin SELI2C is low, the control of the chip is performed through the parallel interface. When accessing
the device through the parallel interface, the following signals are used: The address bus A[7..0]. It is used to select one of the 256 register locations. The data bus DATA[7..0]. If a read cycle is requested, the data lines D[7:0] will be driven by the IC.
For a write cycle, the STA310 will latch the data placed on the data lines when the WAIT signal is
driven high. The signal R/W. It defines the type of register access: either read (when high), or write (when low).
Some registers can be either written or read, some are read only, some are write only. The signal DCSB. A cycle is defined by the assertion of the signal DCSB.
Note:1. The address bus A[7..0], and read/write signal R/W must be setup before the DCSB line is activated.
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STA310 The signal WAIT. This signal is always driven low in response to the DCSB assertion.
The timing diagrams for the parallel control interface are given in Electrical specifications on page 5.
3.4I2 C control interface
When the pin SELI2C is high, the chip is controlled through the I²C interface. The I²C unit works at up to 400kHz
in slave mode with 7-bit addressing. The Pin MAINI2CADR selects the device address. When MAINI2CADR is high the slave address is
0x5C, when low the device address is equal to the value on the address bus (A0...A6). The pin SDAI2C is the serial data line. The pin SCLKI2C is the serial clock.
The I²C Bus standard does not specify sub-addressing. There are thus potentially multiple ways to implement
it. Any implementation that respects the standard is of course legal but a particular implementation is used by
many companies. The following paragraphs describe this implementation.
3.4.1 Protocol description
For write accesses only, the first data which follows the slave address is always the sub-address.
This is the one and only way to declare the sub-address. It should be noticed that the sub-address is implement-
ed as a standard data on the I²C Bus protocol point of view. It is a sub-address because the slave knows that it
must load its address pointer with the first data sent by the master.
See in the Appendix X.x for I2 C message format examples.
3.5 Decoding process
The decoding process in the STA310 is done in several stages: Parsing, Main decoding, Post decoding, Bass redirection, Volume and Balance control.
Each of the stages can be activated or bypassed according to the configuration registers.
Parsing
The bitstream parsing (performed by the input processor) is in charge of discarding all the non audio information
in order to transmit to the next stage (the circular frame buffer) only the audio elementary stream (AC3, MPEG1/
2, LPCM, PCM, DVD Audio).
The parsing stage operates in two phases: the packet parser unpacks the stream, the audio parser checks the
syntax of the bitstream.
Main Decoding
The input of this stage is an elementary stream, the outputs are decoded samples. The number of output chan-
nels is defined by the downmix register (1 channel up to 6 channels). For details, please refer to the description
of the register.
The decoding formats currently supported are AC3, MPEG1 layers I and II, MPEG2 layer II, LPCM. It is neces-
sary to select the appropriate stream format by configuring the registers STREAMSEL and DECODESEL before
running the decoder.
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Post Decoding
The post decoding includes specific PCM processing: DC filter, de-emphasis filter, downsampling filter. These
filters can be independently enabled or disabled through the register DWSMODE.
It provides also a Pro Logic decoder, which is described in detail in a next section.
Bass Redirection
This stage redirects the low frequency signals to the subwoofer.
The subwoofer is extracted from the other channels (L, R, C, Ls, Rs, LFe). There are six possible configurations
to extract the subwoofer channel, which can be selected thanks to the OCFG register.
Volume and Balance Control
The volume is a master volume (no independent control for each channel). It is controlled by the PCMSCALE
register, which enables to attenuate the signals by steps of 2dB.
Two balance controls are available: one for Left/Right channels, one for Left Surround/Right Surround channels.
They are configurable by means of registers BAL_LR (Left-Right Balance) and BAL_SUR (Left Surround-Right
Surround Balance), which provide attenuation of signals by steps of 0.5dB. OPERATION
4.1 Reset
The STA310 can be reset either by a hardware reset or by a software reset: The hardware reset is sent when the pin RESET is activated low during at least 60ns. This is equiv-
alent to a power-on reset.
This resets all the configuration registers, i.e. PLL registers (PLLSYS, PLLPCM), Interrupt registers
(INTE, INT, ERROR), interface registers (SIN_SETUP, CAN_SETUP) and command registers
(SOFTRESET, RUN, PLAY, MUTE, SKIP_FRAME, REPEAT_FRAME). The software reset is sent when the register SOFTRESET is written to 1 (the register is automatically
reset once the software reset is performed). It resets only the interrupt related registers (INTE, INT,
ERROR) and the command registers (SOFTRESET, RUN, PLAY, MUTE, SKIP_FRAME,
REPEAT_FRAME). All other decoding configurations are not changed by softreset.
Some information concerning the post-processing are anywayt of date after a soft-reset
Note:1. The chip must be soft reset before changing any configuration register.
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STA310
4.2 Clocks
There are two embedded PLLs in the STA310: the system PLL and the PCM PLL.
The following is the block diagram of the system and audio clocks used in the STA310
Figure 3. PLL Block Diagram
Figure 4. Block Diagram of Functional PLL
STA310
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4.2.1 System clock
The system clock sent to the DSP core and the peripherals can be derived from 4 sources and the selection is
performed through an Host Register; external clock, external clock divided by 2, internal system PLL and inter-
nal system PLL divided by 2.
The system PLL is used to create the system clock from the input clock. This PLL is software programmable
through the Host Registers mechanism. The system PLL is used to set the any frequency up to the maximum
allowed device speed. After hard reset the system clock is running at 47.25MHz. An RC network must be con-
nected to the filter Pin PLLSF.
The system clock is output on the pin CLKOUT after a programmable divider ranging from 1 to 16.
4.2.2 DAC clocks
4.2.2.1 PCM clock
The PCM clock can be either input to the device or generated by the internal PLL or recovered by the embedded
SPDIF receiver. The selection is done via the Host Registers.
After a hardware reset, the internal PLL is disabled and the PCMCLK pad is an input. PCMCLK may be equal
to the PCM output bit rate, or it may be an integer multiple of this, allowing the use of oversampling D-A con-
verters.
The internal fractional PLL is able to generate PCMCLK at any “FsX Oversampling Factor” frequencies, where
Fs is any multiple or sub-multiple of the two 44.1kHz and 48kHz sampling frequencies. An RC network must be
connected to the filter pin PLLAF; refer to External circuitry on page 9 for recommended values.
If the PCMCLK is recovered from the embedded SPDIF receiver, the only supported overampling frquency is
128 Fs.
4.2.2.2 Bit clock SCLK
The PCM serial clock SCLK is the bit clock. It provides clocks for each time slot (16 cycles for each channel in
16-bit mode, 32 cycles for each channel in 18-, 20-, 24-bit modes). The frequency of SCLK is therefore fixed to
2 x Nb time slots x Fs, where Fs is the sample frequency.
The clock is derived from the clock PCMCLK. The register PCMDIVIDER must be configured according to the
selected output precision and the frequency of PCMCLK, so that the device can construct SCLK:
Fsclk = Fpcmclk / (2 x (PCMDIVIDER+1)) gives
Table 1.
The value of PCMDIVIDER = 0 is reserved. If this number is loaded, the divider is bypassed and the frequency
of SCLK equals the frequency of PCMCLK. The PCMDIVIDER register must be setup before the output of SCLK
starts.
This can be done by first disabling PCM outputs, by de-asserting the MUTE and PLAY commands and then
writing into the PCMDIVIDER register. Once the register is setup, the MUTE and/or PLAY commands can be
asserted. PCMDIVIDER can not be changed “on the fly”.
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STA310
4.2.2.3 Word clock LRCLK
The frequency of LRCLK is given by: Flrclk = Fsclk/32; for 16 bit PCM output, Flrclk = Fsclk/64; for 18, 20 or 24 bits PCM output.
No special configuration is required. The polarity can be changed in the register PCMCONF, by setting up the
field INV as needed.
4.3 Decoding states
There are two different decoder states: Idle state and decode state (see Figure 3). To change states,
register
Figure 5. Decoding States
Idle Mode
This is the state entered after a hardware or software reset. In this state, the embedded DSP does not decode,
i.e. no data are processed. The chip is waiting for the RUN command, and during this state all configuration
registers must be initialized. In this state, even if the chip is not processing data, the DACs clocks can be output,
which enables to setup the external DACs. Once the PCMCLK, SCLK and LRCLK clocks are configured, it is-
possible to output them by setting the MUTE register.I
Table 2. Idle mode. play and mute commands effects
Note:1. The PLAY command has no effect in this state as the decoder is not running. It can however be sent and it will be taken into account
as soon as the decoder enters the decode state.
Decode Mode
This state is entered after the RUN command has been sent (i.e. RUN register = 1). In this mode, the data are
processed. The decoder can play sound, or mute the outputs, by using the PLAY and MUTE registers: To decode streams, the PLAY register must be set. When decoding, the sound will be sent to outputs
if the MUTE register is reset. The outputs are muted if the MUTE register is set. To stop decoding, the PLAY register should be reset. Resuming decoding is performed by writing
PLAY to 1 again
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Table 3. Decode Mode. Play and Mute commands effects
Note:1. It is not possible to change configuration registers in this state. It is necessary to soft reset the chip before. Only the following reg-
isters can be changed “on-the-fly”: PCM_SCALE, BAL_LR, BAL_SUR, OCFG, DOWNMIX registers.
4.4 Data input interface description.
Figure 6. Block Diagram of Data Flow
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STA310
Two independent inputs are available on the STA310.
The main one allows to enter input data stream through through: A serial interface (referred to as Data Serial Interface), And a parallel interface (referred to as Data Parallel Interface).
The choice is performed by the register SIN_SETUP.
4.4.1 Data serial interface
When the serial mode is selected, the bitstreams can be entered into the STA310 through either: a four-signal data interface or , trough a SPDIF input (no external circuit is required).
The four-signal data interface (see Figure 5) provides: An input data line SIN, An input clock DSTR, A word clock input LRCLKIN And a hand-shake output signal REQ.
Note:1. Only 16-bit PCM streams are supported. For 20-bit or 24-bit PCM, the 4 or 8 least significant bits are ignored
The specifications of those signals can be configured by the means of the register CAN_SETUP.
Two modes exist in serial mode, one that uses the LRCLKIN pin and one that does not use the LRCLKIN pin.
4.4.1.1 Modes without the LRCLKIN pin
In this mode the signal LRCLKIN is not used by the STA310. The input data SIN is sampled on the rising edge
of DSTR. When the STA310 input buffer is full the REQ signal is asserted. The polarity of REQ signal is pro-
grammable through the register SIN_SETUP. The data must be sent most significant bits first.
When the decoder cannot accept further data the REQ is de-asserted and the DSTR clock must be stopped as
soon as possible to avoid data loss. After the REQ is de-asserted, the decoder is still able to accept data for a
limited number of clock cycles.
The maximum number of data that can be transmitted with respect to the change of REQ is given by the follow-
ing formula: Nbits = 23 - 6 * FDSTR/33MHz, where: FDSTR is the DSTR clock frequency, (max is 33 MHz).
4.4.1.2 Modes using the LRCLKIN pin
When receiving data from an A/D converter or from an S/PDIF receiver, the signal LRCLKIN is used.
The LRCLKIN signal is used to make the distinction between the left and right channels. Any edge of the LR-
CLKIN signal indicates a word boundary.
The data transfer between the input interface and the FIFO is done on a byte basis. After the edge (rising or
falling) of the LRCLKIN, a new byte is transferred to the first stage of the STA310 every 8 DSTR clock cycles.
If the number of time slots is not a multiple of 8, the remaining data is lost. The polarity of LRCLKIN and DSTR
is programmable.
The LRCLKIN can be delayed by one time slot, in order to support PCM delayed mode. All these configurations
are programmable through the CAN_SETUP register.
The register CAN_SETUP has 4 significant bits, and each bit has a specific meaning, see CAN_SETUP on page
Only the first byte is transferred to the STA310 because the number of time slots is 12 (8 + 4). SIN and LRCLKIN
are sampled on the falling edge of DSTR In this case SIN_SETUP = 3 and CAN_SETUP = LeftFirstChannel +
FallingStrobe + AllSlot = 2 + 4 + 8 = 14
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Table 4.
Figure 7.
Example 2: Only the first 2 bytes are transferred to the STA310 because the number of slots is 20 (16 + 4). SIN
and LRCLKIN are sampled on the falling edge of DSTR. The data is in delayed mode.
The register configuration is SIN_SETUP=3 and CAN_SETUP = DelayMode + LeftFirstChannel + FallingStrobe
+ AllSlot = 1 + 2 + 4 + 8 = 15.
This mode is a specific mode where only the first 16 data bits are transferred. The remaining bits are discarded.
The register configuration is SIN_SETUP = 3 and CAN_SETUP = DelayMode + FallingStrobe = 1 + 4 = 5.
4.4.1.3 SPDIF Input
A true SPDIF Input SPDIF (PCM audio samples) or IEC-61937 (compressed data) is selectable as a main serial
input.
4.4.1.4 Autodetected formats
The STA310 cut 2.0 is able the following audio format changes on the s/pdif input
Table 5. Audio Format detection
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STA310
4.4.1.5 Second Input
A second independent input allows to input bitstreams in serial mode.
This second input can be used, to input audio stream from a microphone, while we decode a data stream trough
the main input.
4.4.2 Data parallel interface
Two ways are available to input data in parallel mode: Either through the parallel data bus, shared with the external controller, Or through the DATAIN register
4.4.2.1 Using the parallel data bus
In this mode the data must be presented on the 8-bit parallel host data bus D[7..0]. Note that this bus is shared
with the external controller. On the rising clock of DSTR the data byte is sampled by the STA310. The signal
REQ is used to signal when the input FIFO is full. When REQ is de-asserted the transfer must be stopped to
avoid data loss.
After the REQ is de-asserted, the decoder is still able to accept data for a limited number of clock cycles.
The maximum number of data that can be transmitted with respect to the change of REQ is given by the follow-
ing formula: Nbits = 23 - 6 * FDSTR/33MHz, where: FDSTR is the DSTR clock frequency, (max is 33 MHz).
The signals DSTR and DCSB are used to make the distinction between Stream Data (strobed by DSTR) and
Control Data (strobed by DCSB). To avoid conflicts, the DSTR signal and the DCSB signal must respect given
timing constraints.
4.4.2.2 Using the DATAIN register
The data can be input by using the control parallel interface as if accessing any other register.
The signal DCSB is therefore used. When using this register to input data stream, there is no need to byte-align
the data.
Figure 8.
STA310
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Figure 9.
4.5 Streams parsers
The parsing stage is operated by two parts: the packet parser and the audio parser.
The packet parser unpacks stream, sorts packets and transmit data to the audio parser. The audio parser ver-
ifies the stream syntax, extracts non-audio data and sends audio data to the frame buffer.
Packet parser
Before unpacking packets and transmitting data, the packet parser needs to detect the packet start by recog-
nizing the packet synchronization word. It is possible to force the parser to search for two packet synchronization
words before starting to unpack and transmit.
This is done by setting the register PACKET_LOCK to 1. Otherwise, the packet parser will start handling the
stream once it has detected information matching the packet synchronization word.
The packet parser is also able to perform selective decoding: it can decode audio packets that are matching a
specified Id. This Id is specified in AUDIO_ID and AUDIO_ID_EXt registers, and the function is enabled by set-
ting the AUDIO_ID_EN register.
Audio parser
The audio parser needs to detect the audio synchronization word corresponding to the type of stream that must
be decoded. It is possible to force the audio parser to detect more than one synchronization word before pars-
ing.
This is done by setting the SYNC_LOCK register to a value between 1 and 3 - number of supplementary sync
words to detect before considering to be synchronized.
The status of synchronization of both parsers is provided in the register SYNC_STATUS. Each time the syn-
chronization status of one of the two parsers changes, the interrupt SYN is generated (if enabled) and the status
can be read in SYNC_STATUS.
4.6 Decoding modes
4.6.1 AC-3
The STA310 is Dolby Digital certified for class A products. The decoder must be programmed so to specify the
stream format as AC-3 encoded: register DECODESEL = 0.
In the sections below are provided the modes specific to the AC-3 decoding.
4.6.1.1 Compression modes
Four compression modes are provided in the STA310:
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STA310 Custom A (also named custom 0 in Dolby specifications), Custom D (also named custom 1 in Dolby specifications), Line mode, RF mode.
These modes refer to different implementation of the dialog normalization and dynamic range control features.
The mode is selected by programming the register COMP_MOD to the appropriate value.
Line Mode
In Line Mode (COMP_MOD = 2), the dialog normalization is always enabled. It is done by the decoder itself and
the dialog is reproduced at a constant level.
The dynamic range control variable encoded in the bitstream is used and can be scaled by the two scaling reg-
isters HDR (for high-level cut compression) and LDR (for low-level boost compression). In case of 2/0 downmix,
the high-level cut compression is not scalable.
RF Mode
In RF Mode (COMP_MOD=3), the dialog normalization is always performed by the decoder. The dialog is re-
produced at a constant level.
The dynamic range control and heavy compression variables encoded in the bitstream are used, but the com-
pression scaling is not allowed. This means that the HDR and LDR registers can not be used in this mode. A
+11dB gain shift is applied on the output channels.
Custom A Mode
In Custom A mode (COMP_MOD=0), the dialog normalization is not performed by the decoder and must be
done by another circuit externally.
The dynamic range control variable encoded in the bitstream is used and can be scaled by the two scaling reg-
isters HDR (for high-level cut compression) and LDR (for low-level boost compression).
Custom D Mode
In Custom D mode (COMP_MOD=1), the dialog normalization is performed by the decoder. The dynamic range
control variable encoded in the bitstream is used and can be scaled by the two scaling registers HDR (for high-
level cut compression) and LDR (for low-level boost compression).
4.6.1.2 Karaoke mode
The AC-3 decoder is karaoke aware and capable.
A karaoke bitstream can be composed of 5 channels: L for Left, R for Right, M for guide Melody, V1 for vocal
track 1 and V2 for Vocal track 2. When in karaoke aware mode, the channels L,R and M are reproduced, and the channels V1 and V2
are reproduced at a level fixed by the bitstream. When in karaoke capable mode, it is possible to choose to reproduce one, two or none of the two
incoming vocal tracks, V1 and V2.
The karaoke decoder is activated by the use of KARAMODE register, which specifies the downmix for the dif-
ferent modes. This register replaces DOWNMIX register. It is however possible to consider the incoming
karaoke channels as any other multichannel stream and output it with a downmix specified in DOWNMIX reg-
ister. For details, refer to the Digital Audio Compression AC-3 ATSC standard, annex C.
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4.6.1.3 Dual Mode
The Dual Mode corresponds to a mode where two completely independent mono program channels (e.g. bilin-
gual) are encoded in the bitstream, referenced to as channel 1 and channel 2.
The possible ways to output channels on left/right outputs are: Output channel 1 on both L/R outputs, Output channel 2 on both L/R outputs, Mix channels 1 and 2 to monophonic and output on both L/R, Output channel 1 on Left output, and channel 2 on Right output.
This channels downmix is specified in the register DUALMODE.
4.6.2 MPEG
The STA310 is able to decode MPEG-1 layerI and layerII encoded data, as well as MPEG-2 layer I, layer II data
without extension (i.e. 2-channel streams).
The MPEG input format should be specified in the DECODESEL register: DECODESEL=1 for MPEG1. The MC bit in MC_OFF register should be set. DECODESEL=2 for MPEG2. The MC bit in MC_OFF register should be set.
4.6.3 MP3
The STA310 is able to decoder MPEG2 layer III (MP3) data.
The MP3 input format aboved be specified in the DECODESEL register: DECODESEL=9 for MP3.
4.6.3.1 Dual Mode
The Dual Mode corresponds to a mode where two completely independent mono program channels (e.g. bilin-
gual) are encoded in the 2-channel incoming bitstream, referenced to as channel 1 and channel 2.
The audio decoder allows to: Output channel 1 on both L/R outputs, Output channel 2 on both L/R outputs, Mix channels 1 and 2 to monophonic and output on both L/R, Output channel 1 on Left output, and channel 2 on Right output.
The output configuration is chosen by special downmix for dual mode through register MPEG_DUAL.
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STA310
4.6.3.2 Decoding flow
Figure 10. AC-3 Decoding Flow
Figure 11. MPEG Decoding Flow
4.6.4 PCM/LPCM
The decoder supports PCM (2-channels) and LPCM Video (8-channels) and Audio (6-channels) streams. This
is selected by DECODESEL=3.
4.6.4.1 Downsampling filter
When decoding PCM/LPCM streams encoded at 96kHz, it is possible to use a filter that downsamples the
stream from 96kHz to 48kHz. The chip can not output streams at 96kHz. The register DWSMODE is used to
configure the use of this filter.
Figure 12. PCM/LPCM Decoding flow
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4.6.5 MLP
MLP is a lossless coding system for use on digital audio data originally represented as linear PCM. MLP is man-
datory in DVD Audio. It allows transmission and storage of up to 6 channels. each up to 24 bits precision and
with sample rates between 44.1 KHz and 192KHz. DECODESEL = 8
4.6.6 CDDA DECODESEL = 5
4.6.7 Beep Tone DECODESEL = 7
4.6.8 Pink noise generator
The pink noise generator can be used to position the speakers in the listening room so to benefit of the best
listening conditions.
The decoder must be programmed so to generate pink noise by writing 4 in the DECODESEL register. The
DOWNMIX register is used to select independently the channels on which the pink noise will be output.
When generating pink noise, the output configuration should be: OCFG=0 and PCM_SCALE=0.
Figure 13. Pink Noise Generator Flow
4.7 Post Processing
The following post processing alghorithms are available
4.7.1 Prologic
Pro Logic Compatible Downmix
The STA310 can decode an AC-3 multichannel bitstream and encode it to provide a 2-channel Pro Logic com-
patible output (Lt, Rt). These 2 channels are the result of a specific downmix referred to as Pro Logic compatible.
This downmix is selected by the register DOWNMIX. The 2 channels can be used as the input of a Pro Logic
decoder and player (e.g. home theatre).
Pro Logic Decoding
The STA310 can decode a 2-channel Pro Logic bitstream. The 2 channels could come from a CD player, an
AC-3 2-channel bitstream or an MPEG1 bitstream. The 2-channel bitstream can be converted into a 4-channel
output (L, R, C, S). The surround (S) is simultaneously sent on Ls and Rs channels. A Pro Logic downmix en-
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ables to configure which channels to output on PCM data. This is done through the register PL_DWN.
An auto-balance feature is available and activated through PL_AB register. The delay on surround channel is
configurable thanks to the LSDLY register (while resetting the RSDLY register).
The bass redirection is performed after the Pro Logic decode. The same bass redirection configuration than
those available in non-Pro Logic modes can be used except that the surround channels will not be added to the
bass redirection. In the case of AC-3 or MPEG the STA310 is therefore capable of first decoding the AC-3 or
MPEG stream then performing the Pro Logic decode.
4.7.2 Others Karaoke system Bass Management + Volume Control
-Deemphasis DC Remove
4.8 How to choose a decoder
To set up the device you have to select two registers.
The first one is DECODESEL for Audio data type,
The second one is STREAMSEL for Transport data type,
The STREAMSEL can be set-up as follows:
0= PES
1= PES DVD Video
2= Packet MPEG1
3= Elementary stream or IEC.60958
4= reserved
5= IEC.61937
6= PES DVD Audio
So the possible configurations on listed in the following table:
Table 6. Possible configurations:
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4.9 How to Program a Post Processing
4.9.1 2 registers for the mode:
PDEC (0x62) to define the type of PostProcessing
4.9.2 1 or 2 registers to control the “PostProcessing”
Prologic decoder (PDEC = 0x01):
Remark: When playing “Dolby Digital Prologic encoded”, if PL_DOWNMIX is correctly set, Prologic decoder’ is
automatically applied even if the register “PDEC” different to 1.
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4.10 What Can Be Processed at the Same Time
Same Time 1
Same Time 2 PCM OUTPUT CONFIGURATIONS
5.1 Output configurations
The figure below shows the different configurations supported at PCM output stage. They are selected by the
OCFG register contents. In configuration 1, 3 and 4, the main channels are attenuated by 18.5dB, and the LFE by 8.5dB before
summing.
After digital/analog conversion, the subwoofer preamplifier has to compensate for the different gains
of the main channels and subwoofer. In configuration 2, the main channels are attenuated by 16dB and the LFE by 6dB before processing. In configuration 0, outputs are only scaled and rounded (see next section).
The same configurations will be used in case of a decoded Pro Logic program with the exception that the sur-
round channels will not be added to the bass redirection (the surround channels of a Pro Logic program are
band limited and bass is considered as leakage).
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Figure 14. PCM Output Configurations
5.2 PCM scaling
PCM scaling is needed for every decoding mode (AC3, Pro Logic, MPEG, PCM). It is applied at the end of the
filtering steps before PCM output, allowing maximum effective word width for most of the signal processing be-
fore.
Master volume (PCM_SCALE register) and balances (BAL_LR and BAL_SUR registers) are implemented for
PCM scaling.
5.3 Output quantization
For optimal results for 16/18/20-bit DACs, a quantization with rounding is applied together with the PCM scaling.
The sample value is multiplied by a rounding factor and rounded to 24 bits. The result is then left shifted (4/6/8)
for PCM output.
The output precision is selectable from the 16bits/word to 24 bits/word by configuring the field PREC in the reg-
ister PCMCONF.
5.4 Interface and output formats
The decoded audio data are output in serial PCM format.
The interface consists of the following signals
PCM_OUT0, 1, 2 PCM data, output,
SCLK Bit clock (or serial clock), output,
LRCLK Word clock (or Left/Right channel select clock), output,
PCMCLK PCM clock, input or output (see Clocks on page 11 for details).
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5.4.1 Output precision and format selection
Output precision is selectable from 16 bits/word to 24 bits/word by setting the output precision select, in the PC-
MCONF (16-, 18-, 20- and 24-bit mode) register.
In 16-bit mode, data may be output either with the most significant bit first or least significant bit first. This is
configured by the contents of the field ORD in the PCMCONF register.
When PCMCONF.PREC is more than 16 bits, 32 bits are output for each channel. In this configuration, the field
FOR of register PCMCONF is used to select Sony or I²S- compatible format. The field DIF of PCMCONF is used
to position the 18, 20 or 24 bits either at the beginning or at the end of each 32-bit frame.
Figure 15. Output formats
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How to read the above table:
The first 4 columns list the possible configurations for output formats on the PCM outputs. The 5th column gives
the description of the internal 24-bit decoded, scaled and rounded audio samples as they are stored in memory.
These 24 bits are referred to as d23, d22,..., d0, where MSB=d23, LSB=d0. The last column describes the se-
quence of bits that are output on PCM_OUT according to the selected format.
Example 1: in 16-bit mode, with PCMCONF.ORD=1: In memory, 24 bits are stored, where only the 16 MSB bits
(d23, d22,... to d8) are significant and the 8 remaining bits are 0. This is noted: {d23-d8} {8*0}. The data are sent
LSB first, i.e. d8 is sent first and d23 is sent last. This is noted {d8-d23}. 16 bits only are transmitted per channel.
Example 2: in 20-bit mode (PCMCONF.ORD field is meaningless in this mode), with PCMCONF.FOR=1 and
PCMCONF.DIF=0: In memory, 24 bits are stored, where only the 20 MSB (d23 to d4) are significant and the
remaining 4 LSB are 0.This is noted: {d23-d4} {4*0}. 32 bits are transmitted per channel on the PCM outputs:
the 12 first transmitted bits are d23, the last bits are d23 to d4, where d23 is transmitted first. This is noted:
{12*d23} {d23-d4}.
5.4.2 Clocks polarity selection
The polarity of the PCM serial output clock, SCLK and the polarity of the PCM word clock LRCLK are selected
by the field SCL and INV respectively, in the PCMCONF register.
5.4.3I2 S format compatible outputs
To output I²S compatible data, the PCMCONF register must be configured as follows
5.4.4 Sony format compatible outputs
Figure 16. SCLK Polarity
Figure 17. LRCLK Polarity
PCMCONF.DIF = 1 not right padded,
PCMCONF.FOR = 0 I²S format,
PCMCONF.INV = 0 do not invert LRCLK,
PCMCONF.SCL = 0 do not invert SCLK.
PCMCONF.FOR = 1 Sony format,
PCMCONF.INV = 1 Invert LRCLK.
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STA310 S/PDIF OUTPUT
The S/PDIF output pad is a TTL output pad with slew rate control. The output DC capability is 4 mA. The voltage
drop is 3V. This output must be connected to a TTL driver before the transformer.
The S/PDIF output supports SPDIF and IEC-61937 standards. Several registers must be initialized to configure
the SPDIF output: The category code must be entered in the IEC958_CAT register. It is related to the type of application.
The category code is specified in the Digital Output Interface standard. The status bits that will be transmitted on the SPDIF output, must be programmed in the
IEC958_STATUS register. IEC clock setting must be specified in the IEC958_CONF register. The data type dependent information can be specified in the IEC958_DTDI register. The S/PDIF type is selected through the IEC958_CMD register: the IEC unit can output decoded data
(PCM mode), encoded data, or null data.
Note:1. The SPDIF output handles only 48kHz or 44.1kHz sample rates.
6.1 SPDIF output
When configured in SPDIF mode, the S/PDIF output is used to transmit either the L/R channels (PCMOUT1) or
VCR_L/VCR_R (PCMOUT0).
The selection is done by choosing the PCM mode and AUX = 1 in the register SPDIF_CMD and resetting the
COM status of SPDIF_STATUS register.
6.2 IEC-61937 output
When configured in IEC-61937 mode, the S/PDIF output is used to transmit encoded data taken directly from
the frame buffer.
The selection is done by choosing the encoded mode (ENC mode) in the register IEC958_CMD and setting the
bit COM in IEC958_STATUS register.
The decompressed data are output simultaneously on the PCM_OUT outputs.
Latency in software versions 6 and later
For software versions 6 and later, when choosing to output encoded S/PDIF data, a latency is automatically in-
serted between S/PDIF output and PCM outputs. The PCM outputs are delayed compared to the SPDIF output.
The latency value is defined by standards and applied when the auto-latency mode is selected.
AC3 decoding
MPEG decoding
where Fs is the sampling frequency in kHz, Framesize is expressed in 16-bit words, Datarate is the bit rate in
kbits per second.
The latency insertion can not be disabled however it can be programmed to values different from those required
in the standard by selecting the user-programmable-latency mode (by setting the bit 7 of IEC858_CONF regis-
Latency = 1/Fs * (1/3 * Framesize + 256)
= 1/Fs * (32 * Datarate/Fs + 256)
Latency = 1/Fs * (36 * Datarate/Fs + 96)
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ter). In this case, the latency is specified in the IEC958_LATENCY register.
Note that there are minimum and maximum values to respect
Table 7.
If those limits are not respected, an error interrupt occurs corresponding to error type: LATENCY_TOO_BIG,
which automatically makes the chip switch to auto_latency mode.
For software versions prior to 6, the latency is not implemented.
6.3 PCM null data
When configured in muted mode (in the IEC958_CMD register), the outputs are PCM null data. This can be
used to synchronize the external IEC receiver. INTERRUPTS
7.1 Interrupt register
The decoder can signal to the external controller that an interrupt has occurred during the execution.
The register INTE enables to select which interrupts will be generated and output on the IRQ output pin.
When an interrupt occurs, the signal IRQ is activated low and the controller can check which interrupt was de-
tected by reading the register INT.
According to the type of interrupt detected, other information can be obtained by reading associated registers
(such as stream header, type of error detected, PTS value).
7.2 IRQ Signal
This signal, IRQ, is a three-state line. This signal indicates (by going low) when an interrupt occurs. It returns to
high level once the corresponding bit in the interrupt register has been cleared.
7.3 Error concealment
Errors are signaled as interrupts by the audio core. The error list is provided in. Most of the errors are automat-
ically handled by the core, some require that software be changed.
AC-3 decoding errors:
Those errors are signaled in the ERROR register but handled directly by the core. Nothing can be done by the
software. They signal that something wrong happened during the decoding. The core soft mutes the frame and
continues to decode.
MPEG decoding errors:
Those errors are also signaled in the ERROR register but handled directly by the core. Nothing can be done by
the software. They signal that something wrong happened during the decoding. The core soft mutes the frame
and continues to decode. Only one error in this category indicates a programming error: if triggering the
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MPEG_EXT_CRC_ERROR, the bit MC_OFF must be set. This indicates that the decoder tries to decode more
than 2 channels whereas the incoming stream contains only 2 channels.
Packet and audio synchronization errors:
Those errors are handled internally, and usually indicate that the incoming bitstream is incorrect or incorrectly
input to the chip. In those cases, the decoder resets the corresponding parsing stage (packet or audio parser)
then searches for the next correct frame.
Miscellaneous errors: LATENCY_TOO_BIG error indicates a problem of latency programming which is superior to the max-
imum authorized value.
Change the latency value or switch to auto-latency mode to solve the problem. Other miscellaneous
errors are internally handled.
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8.1 Presentation time stamp detection
8.1.0.1 PTS Signal
This signal, PTS, is used to signal the detection of a Presentation Time Stamp in a stream, for audio/video syn-
chronization. When a PTS is detected, the signal PTS goes low during one LRCLK period. It is generated while
the PCM are output, so to enable the use of an external counter to synchronize the STA310 with a video decod-
er.
The signal is activated, even if PTS interrupt is not enabled.
8.1.1 PTS interrupt
When enabled through the INTE register, the interrupt PTS is generated when a PTS is detected. The interrupt
is signalled on the IRQ output, which goes low. The IRQ signal is de-activated once the PTS bit has been
cleared in INT register by reading the PTS Most Significant Bit.
8.1.2 PTS interrupt and signal relative timings
The IRQ configured as PTS interrupt is output before the PTS signal. The PTS signal is activated at last one
period of LRCLK after the IRQ signal.
8.2 Frames skip capability
When the audio decoder is late compared to the video decoder, the decoder is able to skip frames. Writing 1 in
the SKIP_FRAME register makes the decoder ignore the next incoming frame. Once skipping the frame, it con-
tinues to decode the stream, and the SKIP_FRAME register is automatically reset.
8.3 Frames repeat capability
When the audio decoder is ahead of the video decoder, the decoder can repeat frames. Writing 1 in the
REPEAT_FRAME register makes the decoder repeat the current frame. Once repeating the frame, the chip
plays the next incoming frame, and the REPEAT_FRAME register is reset. REGISTER MANUAL
9.1 Introduction
The STA310 device contains 256 registers.
Two types of registers exist: From address 0x00 to 0x3F, the registers are real registers that can be initialized after reset. From address 0x40 to 0x100, they are memory locations. This means that the registers located at the
address 0x40 to 0x100 can have different meanings and usage according to the mode in which the
device operates.
Be careful that they can not be hardware reset: they contain undefined values at reset and require to
be initialized after each hardware reset.
In this document, only the user registers are described.
The undocumented registers are reserved. These registers must never be accessed (neither in Read nor in
Write mode).
The Read only registers must never be written
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9.2 Register map by function
The following tables list the register map by address and function, then each audio decoder register is described
individually
Table 8.
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9.3 VERSION REGISTERS
IDENT
Identify
Address: 0x01
Type: RO
Software Reset: 0x31
Hardware Reset: 0x31
Description:
IDENT is a read-only register and is used to identify the IC on an application board. IDENT always has the value
“0x31”.
SOFTVER
Software version
Address: 0x71
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
This SOFTVER register is the version of the code which is running on the device. This regiter is updated by the
embedded software just after a soft reset of the device: For STA310 cut 1.0 the register contain the value 0x0A For STA310 cut 2.0 the register contain the value 0x14
Loading a patch into the STA310 will automatically change the register content.
Please contact ST to have the correct value according to the patch being used.
This register must be readonly after the STA310 has finished booting, in order to get a correct value (when
INIT_RAM register hold the value 1)
VERSION
Version
Address: 0x00
Type: RO
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Software Reset: NA
Hardware Reset: NA
Description:
This version register is read only and is used to iden-
tify the audio hardware version. The version register
holds a number which refers to the cut number. The
version numbers are defined as below: STA310 cut 1.0, version number is : 0x10 STA310 cut 2.0, version number is : 0x10
9.4 SETUP & INPUT REGISTERS
The STA310 can get receive an input bitstream either
from the I2s input or ffrom the Spdif input, the selec-
tion and the configuration is done through 2 registers
SIN_SETUP @ 12 and CAN_SETUP @ 13.
SIN SETUP
Input data setup
Address: 0x0C
Type: R/W
Software Reset: NC
Hardware Reset: 0
Description:
This register is used to configure the input data inter-
face. The register must be setup before sending data
to the IC. The mapping of the register isescribed be-
low. Remember that the data must be sent to the de-
vice MSB first. SPDIF data frpm SPDIF when set to 1, data
from main I2 S input. POL Polarity of the REQ signal. When set,
the REQ pin is active low: data must be input
when REQ is low. When reset, the REQ pin is
active high and data must be input when REQ
is high. IMODE[1...0] Input mode. Indicates which
data input interface is used.
The configuration of the 3 possible interfaces is
shown below:
When the IC is configured in mode 1 or 3, the
CAN_SETUP register is used to configure the IC with
repect to the data format.
CAN_SETUP
A/D converter setup
Address : 0x0D
Type: R/W
Software Reset: NC
Hardware Reset: 0
Description:
CAN_SETUP is used to configure the data serial in-
terface. The register is only taken into account when
the register sin_setup [1...0] = 3.
Also see SIN_SETUP register./ S16 When set, the slot count is 16. When re-
set, the slot count is 32 but only the first 16
are extracted. SAM When set data is sampled on the falling
edge of the DSTR. When reset, the data is
sampled on the rising edge of DSTR FIR When set the first channel (Left) is input
when Lrclkin=1. When reset, the first channel
is input when Lrclkin=0. PAD When set, data Lrclkin is delayed by one
cycle (padding mode).
When the IC is configured with the S/PDIF input, reg-
ister CAN_SETUP must be set to 2
DATAIN
Data input
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Address : 0x0E
Type: WO
Software Reset: NA
Hardware Reset: NA
Description:
Data can be fed into the STa310 by using this register
instead of the dedicated interface. there is no need to
byte align the bitstream when using this register.
9.5 PCM CONFIGURATION RESISTERS
PCMDIVIDER
Divider for PCM clock
Address : 0x54
Type: R/W
Software Reset: UND
Hardware Reset: UND
Description:
The PCM divider must be set according to the formu-
la below, where DAC_SCLK is the bit clock for the
DAC. When Div is set to 0, DAC_SCLK is equal to
DAC_PCMCLK:
Div = (DAC_PCMCLK/ (2 x DAC_SCLK)) -1
When the internal PLL is used, DAC_PCMCLK=384
x fs or 256 x fs. If DAC_PCMCLK = 384 x fs, the for-
mula becomes:
Div = (192 x Fs/DAC_SCLK) -1
If DAC_SCLK is 32 x Fs (common case with the 16
bit DAC), Div must be set to 5.
PCMCONF
PCM configuration
Address: 0x55
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
PCMCROSS
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Address: 0x56
Type: R/W
Software Reset: NC
Hardware Reset: UND
Description:
The PCMCROSS register only acts if bit PFC of reg-
ister SPDIF_DTDI is set.
9.6 PDAC and PLL configuration registers
SFREQ
Sampling frequency
Address: 0x05
Type: R/WS
Software Reset: NC
Hardware Reset: 0
Description:
This status register holds the code of the current
sampling frequency. If the audio stream is encoded
(Dolby Digital, MPEG) or packetized (DVD_LPCM),
the sampling frequency is automatically read in the
audio stream and written into this register by the au-
dio DSP. The register is automatically updated by the
DSP when it performs a down-sampling (for exam-
ple, 96kHz to 48kHz).
The DSP resets SFREQ to 0.
For PCM stream or CDDA, this register is written to
by the application. The value in SFREQ corresponds
to the following frequencies:.
PLLCTRL
PLL Control
Address: 0x12
Type: R/W
Software Reset: NA
Hardware Reset: 0x19
Description:
PLL_DATA
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PLLData
Address: 0x11
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
Data that must be written (has been read) at (from)
the address specified by PLL_ADD.
PLL_CMD
PLL Command
Address: 0x1D
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
PLL_ADD
PLL Address
Address: 0x12
Type: R/W
Software Reset: NA
Hardware Reset: 0
Description:
ENA_AU_FRACPLL
Audio PLL Enable
Address: 0xB5
Type: R/W
Software Reset: 1
Hardware Reset: 0
Description:
This register is used to enable the audio PLL of the
STA310. This register must be always set to “1” after
either a soft or hardware reset.
AU_PLL_FRACL_192
Frac Low Coefficient
Address: 0xB6
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Type: R/W
Software Reset: 0x34
Hardware Reset: UND
Description:
This register must contain a FRACL value that en-
ables the audio PLL to generate a frequency of
ofact*192KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_FRACH_192
Frac High Coefficient
Address: 0xB7
Type: R/W
Software Reset: 0xEC
Hardware Reset: UND
Description:
This register must contain a FRACH value that en-
ables the audio PLL to generate a frequency of
ofact*192KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_XDIV_192
X Divider Coefficient
Address: 0xB8
Type: R/W
Software Reset: 0x01
Hardware Reset: UND
Description:
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of
ofact*192KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_MDIV_192
M Divider Coefficient
Address: 0xB9
Type: R/W
Software Reset: 0x09
Hardware Reset: UND
Description:
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of
ofact*192KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_NDIV_192
N Divider Coefficient
Address: 0xBA
Type: R/W
Software Reset: 0x01
Hardware Reset: UND
Description:
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of
ofact*192KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
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384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_FRACL_176
Frac Low Coefficient
Address: 0xBB
Type: R/W
Software Reset: 0x3
Hardware Reset: UND
Description:
This register must contain a FRACL value that en-
ables the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_FRACH_176
Frac High Coefficient
Address: 0xBC
Type: R/W
Software Reset: 0x9
Hardware Reset: UND
Description:
This register must contain a FRACH value that en-
ables the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_XDIV_176
X Divider Coefficient
Address: 0xBD
Type: R/W
Software Reset: 0x01
Hardware Reset: UND
Description:
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_MDIV_176
M Divider Coefficient
Address: 0xBE
Type: R/W
Software Reset: 0x09
Hardware Reset: UND
Description:
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
AU_PLL_NDIV_176
N Divider Coefficient
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Address: 0xBF
Type: R/W
Software Reset: 0x01
Hardware Reset: UND
Description:
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of
ofact*176KHz for the PCMCK.
Default value at soft reset assume: Oversampling factor (ofact) = 384. PCMLCK =
384 x SF (where SF is the sampling frequency) External crystal provide a clock running at
27MHz
INIT_RAM
STa310 boot Done
Address: 0xFF
Type: RO
Software Reset: 1
Hardware Reset: 0
Description:
This register is used to signal when the STA310 has
finished to boot. After a soft reset or a hardware re-
set, the host processor must wait until INIT_RAM
hold the value “1”.
The host can then start to configure the STA310 ac-
cording to its application.
PLLMASK
PCMCLK mask for half sampling frequency
Address: 0x18
Type: W
Software Reset: NC
Hardware Reset: 0
9.7 Channel delay set-up registers
The six delay setup registers are used to set the rel-
ative delays to the (up to) six loud speaker channels
in order to give the sound effects of, for example, a
large room or to compensate for the listener not being
in the centre of the loud speaker system. The sum of
the delays on the channels must be less than or
equal to 35ms.
The unit for the register delay contents is a group of
16 samples.
Each register value is chosen using the expression:
desired channel delay’*’sampling frequency’/16 sam-
ples and taking care to ensure that the sum of the ’de-
sired channel delays’ is not more than 35ms.
For example, when the sampling frequency is 48kHz,
the sum of the values programmed in the six delay
registers must be less than or equal to:
35 ms * 48 KHz /16 samples = 105.
When only one surround channel is present (in Pro
Logic or other mode), the right surround delay must
be cleared, and the left delay channel is used for both
surround channels.
LDLY
Left channel delay
Address: 0x57
Type: R/W
Software Reset: NC
Hardware Reset: UND
