STA308A-STA308A13TR Fast Delivery |IC PHOENIX CO.,LIMITED

STA308A13TR ,MULTICHANNEL DIGITAL AUDIO PROCESSOR with DDX"FEATURESFigure 1. Package■ 8 Channels of 24-bit DDX™ ■ >100dB SNR and Dynamic Range■ Selectable 32k ..
STA308A13TR ,MULTICHANNEL DIGITAL AUDIO PROCESSOR with DDX"BLOCK DIAGRAM SA SCL SDA MVO OUT1A/B LRCKI 2OUT2A/B I C BICKI SERIAL OUT3A/B OVERSAMPLING SDI12 ..
STA309A ,3-phase Motor Driver ArrayFeatures® 8 channels of 24-bit DDX (direct digital TQFP64amplification) >100 dB of SNR and dynami ..
STA309A13TR applications the additional 2 channels can be – Preset TV channel/commercial AGC mode used for audi ..
STA309A13TR applications. It provides output capabilities for ® ®DDX . In conjunction with a DDX power device, ..
STA310 ,6+2-CH. MULTISTANDARD AUDIO DECODERAPPLICATIONS■ Downmix for Dolby Prologic compatible.■ High-end audio equipment.❚ A separate (2-ch) ..
STS3402 , N-Channel E nhancement Mode Field Effect Transistor
STS3402 , N-Channel E nhancement Mode Field Effect Transistor
STS3C2F100 ,N-CHANNEL 100VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)jTAB.2 OFFSymbol Parameter Test Co ..
STS3C3F30L ,N-CHANNEL 30VELECTRICAL CHARACTERISTICS (T = 25 °C unless otherwise specified)caseOFFSymbol Parameter Test Condi ..
STS3DNE60L ,DUAL N-CHANNEL 60VSTS3DNE60L®N - CHANNEL 60V - 0.065W - 3A SO-8STripFET

STA308A-STA308A13TR
MULTICHANNEL DIGITAL AUDIO PROCESSOR with DDX"
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STA308A
May 2004 FEATURES 8 Channels of 24-bit DDX™ >100dB SNR and Dynamic Range Selectable 32kHz-192kHz Input Sample Rates 6 Channels of DSD/SACD InputI2 C control with Selectable Device Address Digital Gain/Attenuation +58dB to -100dB in
0.5dB steps Soft Volume Update Individual Channel and Master Gain/
Attenuation plus Channel Trim (-10dB to
+10dB) Up to 10 Independent 32-bit User
Programmable Biquads (EQ) per channel Bass/Treble Tone Control Pre and Post EQ Full 8-Channel Input Mix on all
8 Channels Dual Independent Limiters/Compressors Dynamic Range Compression or Anti-Clipping
Modes AutoModes™: 5-Band Graphic EQ 32 Preset EQ Curves (Rock, Jazz, Pop, etc.) Automatic Volume Controlled Loudness 5.1 to 2 channels Channels Downmix Simultaneous 5.1 and 2 Channel Downmix
Outputs 3 Preset Volume Curves 2 Preset Anti-Clipping Modes Preset Movie Nighttime Listening Mode Preset TV Channel/Commercial AGC Mode 5.1 Bass Management Configurations 2.1 Bass Management AM Frequency Automatic Output PWM Fre-
quency Shifting QSurround5.1 8 preset Crossover filters Individual Channel and Master Soft and Hard
Mute Automatic Zero-Detect Mute Automatic Invalid Input Detect Mute Advanced PopFreeTM Operation Advanced AM Interference Frequency
Switching and Noise Suppression Modes PSCorrectTM Power Supply Ripple Correction 8-Channel I2S Input and Output Data Interface I2S Output Channel Mapping Function Independent Channel Volume and DSP Bypass Channel Mapping of any input to any
processing/DDX channel DC Blocking Selectable High-Pass Filter Selectable per-channel DDX Damped Ternary
or Binary PWM output Selectable De-emphasis Variable Max Power Correction for lower full-
power THD Variable per channel DDX output delay control PWM Half and Double Speed Modes Internal Loop Mode for up to 1 Channel of 80
Programmable Biquads 192kHz Internal Processing Sample Rate, 24-
bit to 36-bit precision 3.3V Single Supply Operation
* Provided only under License from QSound Labs, Inc. DESCRIPTION
The STA308A is a single chip solution for digital au-
dio processing and control in multi-channel applica-
tions. It provides output capabilities for DDXTM (Direct
Digital Amplification). In conjunction with a DDXTM
power device, it provides high-quality, high-efficien-
cy, all digital amplification. The device is extremely
versatile allowing for input of most digital formats in-
cluding 6.1/7.1 channel and 192kHz, 24-bit DVD-Au-
dio, DSD/SACD. In 5.1 application the additional 2
PRODUCT PREVIEW
MULTICHANNEL DIGITAL AUDIO
PROCESSOR WITH DDX™
REV. 1
STA308A
DESCRIPTION (continued)
channels can be used for line-out or loadphone drive
Figure 2. BLOCK DIAGRAM
Figure 3. CHANNEL SIGNAL FLOW
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STA308A
Figure 4. PIN CONNECTION (Top view)
Table 2. PIN FUNCTION
STA308A
Table 3. ABSOLUTE MAXIMUM RATINGS
Table 4. THERMAL DATA
Table 5. RECOMMENDED DC OPERATING CONDITIONS
Table 2. PIN FUNCTION (continued)
5/45
STA308A ELECTRICAL CHARACTERISTCS (VDD3 = 3.3V ± 0.3V; VDDA = 3.3V ± 0.3V; TAMB = 0 TO 70 °C;
UNLESS OTHERWISE SPECIFIED)
Table 6. GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Note 1: The leakage currents are generally very small, < 1na. The values given here are maximum after an electrostatic stress on the pin.
Note 2: Human Body Model
Table 7. DC ELECTRICAL CHARACTERISTICS: 3.3V BUFFERS PIN DESCRIPTION
4.1 MVO: Master Volume Override
This pin enables the user to bypass the Volume Control on all channels. When MVO is pulled High, the Master
Volume Register is set to 00h, which corresponds to its Full Scale setting. The Master Volume Register Setting
offsets the individual Channel Volume Settings, which default to 0dB.
4.2 SDI_12 through 78: Serial Data In
Audio information enters the device here. Six format choices are available including I2S, left- or right-justified,
LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
4.3 RESET
Driving this pin (low) turns off the outputs and returns all settings to their defaults.
4.4I2C
The SA, SDA and SCL pins operate per the Philips I2C specification. See Section 5.
STA308A
4.5 PLL: Phase Locked Loop
The phase locked loop section provides the System Timing Signals and CKOUT.
4.6 CKOUT: Clock Out
System synchronization and master clocks are provided by the CKOUT.
4.7 OUT1 through OUT8: PWM Outputs
The PWM outputs provide the input signal for the power devices.
4.8 EAPD: External Amplifier Power-Down
This signal can be used to control the power-down of DDX power devices.
4.9 SDO_12 through 78: Serial Data Out
Audio information exits the device here. Six different format choices are available including I2S, left- or right-
justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
4.10 PWDN: Device Power-Down
This puts the STA308A into a low-power state via appropriate power-down sequence. Pulling PWDN low begins
power-down sequence, and EAPD goes low ~30ms later.2 C BUS SPECIFICATION
The STA308A supports the I2 C protocol via the input ports SCL and SDA_IN (Master to Slave) and the output
port SDA_OUT (Slave to Master).
This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the
data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave. The master always
starts the transfer and provides the serial clock for synchronization. The STA308A is always a slave device in
all of its communications.
5.1 COMMUNICATION PROTOCOL
5.1.1 Data Transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is
high is used to identify a START or STOP condition.
5.1.2 Start Condition
START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable
in the high state. A START condition must precede any command for data transfer.
5.1.3 Stop Condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the
high state. A STOP condition terminates communication between STA308A and the bus master.
5.1.4 Data Input
During the data input the STA308A samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can
change only when the SCL line is low.
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STA308A
5.2 DEVICE ADDRESSING
To start communication between the master and the Omega DDX core, the master must initiate with a start con-
dition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select
address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2 C bus definition. In the
STA308A the I2 C interface has two device addresses depending on the SA port configuration, 0x40 or
0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode.
After a START condition the STA308A identifies on the bus the device address and if a match is found, it ac-
knowledges the identification on SDA bus during the 9th bit time. The byte following the device identification
byte is the internal space address.
5.3 WRITE OPERATION
Following the START condition the master sends a device select code with the RW bit set to 0. The STA308A
acknowledges this and the writes for the byte of internal address.
After receiving the internal byte address the STA308A again responds with an acknowledgement.
5.3.1 Byte Write
In the byte write mode the master sends one data byte, this is acknowledged by the Omega DDX Core. The
master then terminates the transfer by generating a STOP condition.
5.3.2 Multi-byte Write
The multi-byte write modes can start from any internal address. The master generating a STOP condition ter-
minates the transfer.
Figure 5. Write Mode Sequence
Figure 6. Read Mode Sequence
STA308A REGISTER SUMMARY
Table 8. Register Summary
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STA308A
Table 8. Register Summary (continued)
STA308A
6.1 Configuration Register A (address 00h)
6.1.1 Master Clock Select
The DDX8000 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, 176.4kHz, 192kHz, and
2.8224MHz DSD. Therefore the internal clock will be: 65.536Mhz for 32kHz 90.3168Mhz for 44.1khz, 88.2kHz, 176.4kHz, and DSD 98.304Mhz for 48kHz, 96kHz, and 192kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The
relationship between the input clock and the input sample rate is determined by both the MCSx and the IRx (In-
put Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IRx bits
determine the oversampling ratio used internally.
Table 9.
6.1.2 Interpolation Ratio Select
The STA308A has variable interpolation (oversampling) settings such that internal processing and DDX output
rates remain consistent. The first processing block interpolates by either 4 times, 2 times, or 1 time (pass-
through).
The oversampling ratio of this interpolation is determined by the IR bits.
Table 8. Register Summary (continued)
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STA308A
Table 10. IR bit settings as a function of Input Sample Rate.I
6.1.3 DSP Bypass9
Setting the DSPB bit bypasses the biquad functionality of the Omega DDX Core.
6.1.4 Clock Output Select:
6.2 Serial Input Formats(Address 01h)
6.2.2 Serial Data Interface
The STA308A audio serial input was designed to interface with standard digital audio components and to accept
a number of serial data formats. STA308A always acts a slave when receiving audio input from standard digital
audio components. Serial data for eight channels is provided using 6 input pins: left/right clock LRCKI (pin xx),
serial clock BICKI (pin xx), serial data 1 & 2 SDI12 (pin xx), serial data 3 & 4 SDI34 (pin xx), serial data 5 & 6
SDI56 (pin xx), and serial data 7 & 8 SDI78 (pin xx). The SAI register (Configuration Register x - xxh, Bits Dx-
Dx) and the SAIFB register (Configuration Register x - 0xh, Bit Dx) are used to specify the serial data format.
The default serial data format is I2S, MSB-First. Available formats are shown in the tables and figure that follow.
STA308A
Table 11. Serial Data First Bit
Note: Serial input and output formats (see section 8.2) are specified distinctly
For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First.
Table 4 below lists the serial audio input formats supported by STA308A as related to BICKI = 32/48/64fs, where
sampling rate fs = 32/44.1/48/88.2/96/176.4/192 kHz.
Table 12. Supported Serial Audio Input Formats
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STA308A
6.3.1 DDX Power Output Mode
The DDX Power Output Mode selects how the DDX output timing is configured. Different power devices use
different output modes. The DDX-2060 recommended use is OM = 10.
Table 13. Output Modes
6.3.2 DDX Compensating Pulse Size Register
Table 14. Compensating Pulse Size
6.3.3 Max Power Correction
Setting the MPC bit turns on special processing that corrects the DDX-2060 power device at high power. This
mode should lower the THD+N of a full DDX-2060 DDX system at maximum power output and slightly below.
This mode will only be operational in OM(1,0) = 01.
STA308A
6.4.1 Binary Output Enable Registers
Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel
will be considered the positive output and output B is negative inverse.
6.5.1 High-Pass Filter Bypass
The STA308A features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this
filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage.
If HPB = 1, then the filter that the high-pass filter utilizes is made available as user-programmable biquad#1.
6.5.2 Dynamic Range Compression/Anti-Clipping Bit
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-
clipping mode the limiter threshold values are constant and dependent on the limiter settings.
In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a night-
time listening mode that provides a reduction in the dynamic range regardless of the volume level.
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STA308A
6.5.3 De-Emphasis
By setting this bit to one de-emphasis will implemented on all channels. When this is used it takes the place of
biquad #7 in each channel and any coefficients using biquad #1 will be ignored. DSPB(DSP Bypass) bit must
be set to 0 for De-emphasis to function.
6.5.4 Post-Scale Link
Post-Scale functionality can be used for power-supply error correction. For multi-channel applications running
off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and
update the values faster.
6.5.5 Biquad Coefficient Link
For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space
by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.
6.5.6 PWM Speed Mode
Table 15.
Table 16.
STA308A
6.6.1 Output Signal Disables
6.6.2 AM Mode Enable
The STA308A features a DDX processing mode that minimizes the amount of noise generated in frequency
range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active.
The SNR of the DDX processing is reduced to ~83dB in this mode, which is still greater than the SNR of AM
radio.
6.6.3 AM2 Mode Enable
The STA308A features a 2 DDX processing modes that minimize the amount of noise generated in frequency
range of AM radio. This second mode is intended for use when DDX is operating in a device with an AM tuner
active. This mode eliminates the noise-shaper.
6.6.4 Headphone Enable
Channels 7 and 8 can be configured to be processed and output in such a manner that headphones can be
driven using and appropriate output device. This signal is a fully differential 3-wire drive called DDX Headphone.
6.6.5 Distortion Compensation Variable Enable
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STA308A
6.6.6 Max Power Correction Variable
6.7 Conf H
Table 17.
6.7.1 Noise-Shaper Bandwidth Selection
6.7.2 Zero-Crossing Volume Enable
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no
clicks will be audible.
6.7.3 Soft Volume Update Enable
6.7.4 Zero-Detect Mute Enable
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the input data to
each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value
samples (regardless of fs) then that individual channel is muted if this function is enabled.
6.7.5 Invalid Input Detect Mute Enable
Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the sig-
nals are perceived as invalid.
STA308A
6.7.6
Detects loss of input MCLK in binary mode and will output 50% duty cycle.
6.7.7
Actively prevents double trigger of LRCLK.
6.7.8
When active will issue a power device power down signal(EAPD) on clock loss detection
6.8 Conf
Table 18. I
6.8.1 PSCorrect™ Enable
This feature utilizes an ADC on SDI78 that provides power supply ripple information for correction. Registers
PSC1, PSC2, PSC3 are utilized in this mode.
6.8.2 External Amplifier Power Down
6.8.3 Master Mute Register
6.8.4 Master Volume Register
Note : Value of volume derived from MVOL is dependent on AMV AutoMode Volume settings.
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STA308A
6.8.5 Channels 1,2,3,4,5,6,7,8 Mute
6.8.6 Channel 1 Volume
6.8.7 Channel 2 Volume
6.8.8 Channel 3 Volume
6.8.9 Channel 4 Volume
6.8.10Channel 5 Volume
6.8.11Channel 6 Volume
6.8.12Channel 7 Volume
6.8.13Channel 8 Volume
6.8.14Channel 1 Volume Trim, Mute, Bypass
STA308A
6.8.15Channel 2 Volume Trim, Mute, Bypass
6.8.16Channel 3 Volume Trim, Mute, Bypass
6.8.17Channel 4 Volume Trim, Mute, Bypass
6.8.18Channel 5 Volume Trim, Mute, Bypass
6.8.19Channel 6 Volume Trim, Mute, Bypass
6.8.20Channel 7 Volume Trim, Mute, Bypass
6.8.21Channel 8 Volume Trim, Mute, Bypass
The Volume structure of the STA308A consists of individual volume registers for each channel and a master
volume register that provides an offset to each channels volume setting. There is also an additional offset for
each channel called the channel volume trim. The individual channel volumes are adjustable in 0.5dB steps from
+48dB to -78 dB. As an example if C5V = XXh or +XXXdB and MV = XXh or -XXdB, then the total gain for
channel 5 = XXdB. The Channel Volume Trim is adjustable independently on each channel from -10dB to +10dB
in 1 dB steps. The Master Mute when set to 1 will mute all channels at once, whereas the individual channel
mutes(CxM) will mute only that channel. Both the Master Mute and the Channel Mutes provide a "soft mute"
with the volume ramping down to mute in 8192 samples from the maximum volume setting at the internal pro-
cessing rate(~192kHz). A "hard mute" can be obtained by commanding a value of all 1's(255) to any channel
volume register or the master volume register. When volume offsets are provided via the master volume reg-
ister any channel that whose total volume is less than -91dB will be muted. All changes in volume take place at
zero-crossings when ZCE = 1(configuration register B) on a per channel basis as this creates the smoothest
possible volume transitions. When ZCE=0, volume updates will occur immediately. Each channel also contains
an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register
then only the channel volume setting for that particular channel affects the volume setting, the master volume
setting will not affect that channel. Each channel also contains a channel mute. If CxM = 1 a soft mute is per-
formed on that channel.
21/45
STA308A
Table 19. Master Volume Offset as a function of MV(7..0).
Table 20. Channel Volume as a function of CxV(7..0)
Table 21.
STA308A
6.9 Input Mapping
6.9.1 Channel Input Mapping Channels 1 & 2
6.9.2 Channel Input Mapping Channels 3 & 4
6.9.3 Channel Input Mapping Channels 5 & 6
6.9.4 Channel Input Mapping Channels 7 & 8
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Map-
ping registers. This allows for flexibility in processing, simplifies output stage designs, and enables the ability
to perform crossovers. The default settings of these registers map each I2S input channel to its corresponding
processing channel.
Table 22. Channel mapping as a function of CxIM bits.
6.10 AutoMode™ Registers:
6.10.1Register - AutoModes EQ, Volume, GC
6.10.2AutoMode EQ
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STA308A
By setting AMEQ to any setting other than 00 enables AutoMode EQ, biquads 1-5 are not user programmable.
Any coefficient settings for these biquads will be ignored. Also when AutoMode EQ is used the pre-scale value
for channels 1-6 becomes hard-set to -18dB.
6.10.3AutoMode Volume
6.10.4AutoMode Gain Compression/Limiters
6.10.5AMDM - Automode 5.1 Downmix
Automode downmix setting uses channels 7-8 of Mix#1 engine and therefore these channels of this function are
hard-set and not allowed to be user set when in this mode.
Channels 1-6 must be arranged via Channel Mapping (CxIM) if necessary in the following manner for this op-
eration:
Channel 1 - Left
Channel 2 - Right
Channel 3 - Left Surround
Channel 4 - Right Surround
Channel 5 - Center
Channel 6 - LFE
6.10.6Register - AutoModes Bass Management2
6.10.7

Partno	Mfg	Dc	Qty	Available	Descript
STA308A	ST	N/a	1220	avai	Transistor Array For Source Drive
STA308A13TR	ST,ST	N/a	10000	avai	MULTICHANNEL DIGITAL AUDIO PROCESSOR with DDX"
STA308A13TR	STM	N/a	10000	avai	MULTICHANNEL DIGITAL AUDIO PROCESSOR with DDX"