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STA020D
96KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
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STA020D
96kHz DIGITAL AUDIO INTERFACE TRANSMITTER
n MONOLITHIC DIGITAL AUDIO INTERFACE
TRANSMITTER
3.3V SUPPLY VOLTAGE
n SUPPORTS:
- AES/EBU, IEC 958,
- S/PDIF, & EIAJ CP-340
- Professional and Consumer Formats
n PARITY BITS AND CRC CODES GENERATED
n TRANSPARENT MODE ALLOWS DIRECT
CONNECTION OF STA020D AND STA120
DESCRIPTION
The STA020D is a monolithic CMOS device
which encodes and transmits audio data accord-
ing to the AES/EBU, IEC 958, S/PDIF, & EIAJ
CP-340 interface standards. It supports 96kHz
sample rate operation
The STA020D accepts audio and digital data
which is then multiplexed, encoded and driven
ontoacable.
The audio serial port is double buffered and ca-
BLOCK DIAGRAM
ORDERING NUMBER: STA020D
pable of supporting a wide variety of formats.
The STA020D multiplexes the channel, user, and
validity data directly from serial input pins with
dedicated input pins for the most important chan-
nel status bits.
DEDICATEECHANNEL ch
STATUS BUS
M0 M1 M2 VD+ GND MCK RST
" J" $21 G G p il6
FSYNC 8 SERIAL PORT 20
SDATA -r- -OTXP
MUX - DIFFERENTIAL 17
10 -e- -it)TXN
u 11 REGISTERS
TRNPT D97A U599A
October 2002
STA020D
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VD+ DC Power Supply 4 V
VIND Digital Input Voltage -0.3 to VD+ 0.3 V
Tamb Ambient Operating Temperature (power applied) -20 to +85 "C
Tstg Storage Temperature -40 to 150 °C
RECOMMNDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground)
Symbol Parameter Test Condition Min. Typ. Max. Unit
VD+ DC Voltage 3 3.3 3.6 V
Tamb Ambient Operating Temp. 0 25 70 ''C
PIN CONNECTION
Tnt E 1 V 24 Cl TRNPT/FC1
1% E 2 23 Cl MO
C-1/Fco E 3 22 Cl M1
CRW E 4 21 Cl M2
MCK E 5 20 Cl TXP
SCK E 6 19 Cl VD+
FSYNC E 7 18 Cl GND
SDATA E 8 17 Cl TXN
v E 9 16 Cl 1%
C/SBF E 10 15 Cl CBL/SBC
U E 11 14 Cl EMO/CR)
CE/C-IS E 12 13 Cl EM1/C_8
D97AU608A
PINS DESCRIPTION
N. I Name I Function
Power Supply Connections
18 GND Ground.
19 VD+ Positive Digital Power. Nominally +3.3V.
Audio Input Interface
6 SCK Serial Clock.
Serial clock for SDATA pin which can be configured (via the M0, M1 and M2 pins) as an input
or output and can sample data on the rising or falling edgeAs an output, SCK will contain 32
clocks for every audio sample.
7 FSYNC Frame Sync.
Delineates the serial data and may indicate the particular channel, left or right and may be an
input or output. The format is based on M0, M1 and M2 pins.
2/11 gr,
