STA016T13TR ,MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCMfeatures of the device and allowing the use of only one D/A converter with no external analog switc ..
STA020D ,96KHZ DIGITAL AUDIO INTERFACE TRANSMITTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV DC Power Supply 4 VD+V Digital Input Voltage - ..
STA1050 , CD-Audio one-chip
STA1052 ,CD-MP3 audio SOCFeatures■ CD-R, CD-RW playback■ Audio decoding (MP3,WMA,AAC)■ CLV (1x, 2x, 4x) and CAV mode (6x)LQF ..
STA1052S1 ,CD-MP3 audio SOCblock diagram . . . . . . . 43 Pin description . . . . . 53.1 Pin connection . . . ..
STA120D ,DIGITAL AUDIO INTERFACE RECEIVERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV , V Power Supply Voltage 4 VD+ A+V Input Volta ..
STS10DN3LH5 ,Dual N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET (TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10N3LH5 ,N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET(TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10NF30L ,N-CHANNEL 30VSTS10NF30L®N - CHANNEL 30V - 0.011Ω - 10A SO-8STripFET™ POWER MOSFETPRELIMINARY DATATYPE V R IDSS ..
STS10PF30L ,P-CHANNEL 30VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 30 VDS GSV Drain- ..
STS11N3LLH5 , N-channel 30 V, 0.0117 Ω, 11 A, SO-8 STripFET™ V Power MOSFET
STS11N3LLH5 , N-channel 30 V, 0.0117 Ω, 11 A, SO-8 STripFET™ V Power MOSFET
STA016T13TR
MPEG 2.5 LAYER III AUDIO DECODER SUPPORTING CD-ROM CAPABILITY & ADPCM
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STA016TNovember 2002 SINGLE CHIP MPEG LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio)
- All features specified for Layer III in ISO/IEC
13818-3.2 (MPEG 2 Audio)
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5 DECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2
SAMPLING FREQUENCIES AND THE
EXTENSION TO MPEG 2.5:48, 44.1,32,
24,22.05, 16, 12,11. 025, 8 KHz ACCEPTS MPEG 2.5 LAYER III
ELEMENTARY COMPRESSED BITSTREAM
WITH DATA RATE FROM 8 Kbit/s UP TO 320
Kbit/s BYPASS MODE FOR EXTERNAL AUXILIARY
AUDIO SOURCE ADPCM ENCODING/DECODING
CAPABILITY:
- sample frequency from 8 kHz to 32 kHz
- sample size from 8 bits to 32 bits
- encoding algorithm: DVI, ITU-G726 pack
(G723-24, G721,G723-40) EMBEDDED ISO9660 LAYER FOR FILE-
SYSTEM DECODING (JOLIET) EMBEDDED CD-ROM DECODER BLOCKS
INCLUDING ECC/EDC CAPABILITY FLEXIBLE I2 S INPUT INTERFACE FOR EASY
CONNECTION WITH MOST CD-SERVO
DEVICES EMBEDDED BROWSING COMMAND
INTERPRETER FOR EASY FILE-SYSTEM
BROWSING CUE-SHEET CAPABILITY UP TO 100
ENTRIES BROWSER COMMAND INTERPRETER (BCI)
- Parent Dir
- Enter Dir
- Previous Entry
- Next Entry
- Get Record Infos EASY PROGRAMMABLE GPSO INTERFACE
(MONO/STEREO) FOR ENCODED DATA UP
TO 5Mbit/s DIGITAL VOLUME BASS & TREBLE CONTROL SERIAL BITSTREAM INPUT INTERFACE EASY PROGRAMMABLE ADC INPUT
INTERFACE SERIAL PCM OUTPUT INTERFACE (I2 S AND
OTHER FORMATS) PLL FOR INTERNAL CLOCK AND FOR
OUTPUT PCM CLOCK GENERATION CRC CHECK AND SYNCHRONISATION
ERROR DETECTION WITH SOFTWARE
INDICATORSI2 C CONTROL BUS LOW POWER 2.4V CMOS TECHNOLOGY
WITH 3.3V TOLERANT AND CAPABLE I/O FAST FORWARD AND PAUSE CAPABILITIES
APPLICATIONS AUDIO CD PLAYERS MULTIMEDIA PLAYERS CD-ROM PLAYERS CAR RADIO PLAYERS
PRODUCT PREVIEWMPEG 2.5 LAYER III AUDIO DECODER
SUPPORTING CD-ROM CAPABILITY & ADPCM
STA016T 2/45
DESCRIPTIONThe STA016 is a single chip MPEG 1, 2 and 2.5 Layer III audio decoder with embedded CDROM decoding ca-
pability. It can be easily connected to most existing CDDSP devices via a software configurable serial link. A
tipical application block diagram is show in Figure 1. Besides MPEG decoding the device can also perform AD-
PCM encoding/decoding from different audio sources and the encoded stream, for instance, can be stored on
an external flash memory.
A useful bypass mode allow using this device also as an audio processor for volume and tone controls.
Figure 1. Typical CD-Player application
ABSOLUTE MAXIMUM RATINGS(*) guaranteed by design
THERMAL DATA
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STA016T
1OVERVIEWThe device can decode/process data coming from three possible sources, as showed in Figure 2:
CDDSP serial link: using this input interface, besides MP3 encoded data CD, it's possible to playback also standard Audio CD using the available volume and tone equalizer features of the device and
allowing the use of only one D/A converter with no external analog switch.
SDI input interface: through this input interface it's possible to decode any MP3 bitstream coming, for instance, from an external flash memory. This same interface is also used to decode ADPCM streams.
I2 S input interface: this interface can be used both to encode an external audio source (with variable compression based on 4 different ADPCM algorithm) or to process an external audio source (tuner, for
instance) through the DSP based volume and tone controls:this BYPASS mode can avoid the use of
additional D/A converters or postprocessing units.
1.1 MP3 decoder engineThe MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5
streams are supported.
Decoded audio data goes through a software volume control and a two-band equalizer blocks before feeding
the output I2 S interface. This results in no need for an external audio processor.
Table 1. MPEG Sampling Rates (KHz)
1.2 ADPCM encoder/decoder engineThis device also embeds a multistandard ADPCM encoder/decoder supporting different sample rates (from 8
KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits). During encoding process two different in-
terfaces can be used to feed data: the serial input interface (same interface used also to feed MP3 bitstream)
or the ADC input interface, which provides a seamless connection with an external A/D converter. The currently
used interface is selected via I2C bus.
Also to retrieve encoded data a specific interface is available: the fast GPSO output interface. GPSO interface
is able to output data with a bitrate up to 5 Mbit/s and its control pins (GPSO_SCKR, GPSO_DATA and
GPSO_REQ) can be configured in order to easily fit the target application.
STA016T 4/45
Figure 2. Block DiagramThe basic functions of the device can be fully operated via the I2 C bus. Besides that the GPSO interface can be
used to move huge amount of data this fast and flexible interface can achieve transfer rates up to 5 Mbit/s.
The embedded DSP firmware implements all the layers required to decode a standard data CD, as shown in
the Figure 3:
Figure 3. Layers performed by embedded DSP firmwareThe whole CDROM and file-system decoding task is performed by embedded firmware. The application MCU,
basically, must manage CDDSP device according to STA016 requests. Three basic command flows exist: MCU -> STA016: commands used to handle decoder operation and to ask for specific information like
filename, filelength, sector raw data, etc. This flow will use I2 C (GPSO for special operations) interface. STA016 -> MCU: this channel is used to retrieve inquired information and to inform MCU that a CDDSP
5/45
STA016Tspecific operation must be performed (like pick-up repositioning). This flow is based on I2 C link plus an
additional interrupt signal in order to avoid time consuming polling techniques. MCU -> CDDSP: the CDDSP management is fully up to the application MCU. This architecture allows
maximum flexibility and easy migration from existing CDPlayers to MP3 CDPlayers.
PIN CONNECTION
PIN DESCRIPTION
STA016T 6/45
PIN DESCRIPTION (continued)
7/45
STA016T
PIN DESCRIPTION (continued)
STA016T 8/45
ELECTRICAL CHARACTERISTCS(Tamb = 25°C; Rg = 50Ω unless otherwise specified)
DC OPERATING CONDITIONS
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stresson the pin.
Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Note1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.Note 1: Min. condition: VDD = 2.7V, 125°C Min process Max. condition: VDD = 3.6V, -20°C Max.
POWER DISSIPATION
9/45
STA016T HOST REGISTERSThe following table gives a description of STA016 register list.
The STA016 device includes 256 I2 C registers. In this document, only the user-oriented registers are described.
The undocumented registers are reserved or unused. These registers must never be accessed (in Read or in
Write mode). The Read-Only registers must never be written
We can split the data flux in different time periods (see following diagram) meanwhile host registers can be read
or written : DWT : During Whole Time (at any time during process). DEC : During External Config (period between RUN=2 and RUN=1). DBO : During Boot (period between RUN=0 and RUN=2). ABO : After BOot (period after RUN=1). AEC : After External Config (period after RUN=2). EDF : Every Decoded Frame (each time a frame has been decoded). EDB : Every Decoded Block (each time a block has been decoded).
STA016T 10/45
REGISTER MAP BY FUNCTION
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STA016T
STA016T 12/45
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STA016T
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STA016T REGISTER DESCRIPTION
3.1 VERSION registers description
VERSION : Address : 0x00 (0)
Type : RO - DWT
Software Reset : 0x10
Hardware Reset : 0x10
Description :
The VERSION register is Read-only and it is used to
identify the IC on the application board.
IDENT : Address : 0x01 (1)
Type : RO - DWT
Software Reset : 0xAC
Hardware Reset : 0xAC
Description :
IDENT is a read-only register and it is used to identify
the IC on an application board. IDENT always has the
value 0xAC.
SOFT_VERSION : Address : 0xD3 (211)
Type : RO - DWT
Software Reset : X
Description :
The SOFT_VERSION register is Read-only and it is
used to identify the software running on the IC.
3.2 PLL_AUDIO_CONFIGURATION registers
description
PLL_AUDIO_PEL_192 : Address : 0xDC (220)
Type : RW - DEC
Software Reset : 58
Description :
This register must contain a PEL value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
ofact is the oversampling factor needed by the DAC
(ofac==246 or ofac==384).
Default value at soft reset assume :
–ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_PEH_192 : Address : 0xDD (221)
Type : RW - DEC
Software Reset : 187
Description :
This register must contain a PEH value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume : ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_NDIV_192 : Address : 0xDE (222)
Type : RW - DEC
Software Reset : 0
STA016T 16/45
Description :
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
–ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_XDIV_192 : Address : 0xDF (223)
Type : RW - DEC
Software Reset : 3
Description :
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
–ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_MDIV_192 : Address : 0xE0 (224)
Type : RW - DEC
Software Reset : 12
Description :
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of ofact*192
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
–ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_PEL_176 : Address : 0xE1 (225)
Type : RW - DEC
Software Reset : 54
Description :
This register must contain a PEL value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume : fact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_PEH_176 : Address : 0xE2 (226)
Type : RW - DEC
Software Reset : 118
Description :
This register must contain a PEH value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
–ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_NDIV_176 : Address : 0xE3 (227)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a NDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
–ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
17/45
STA016T
PLL_AUDIO_XDIV_176 : Address : 0xE4 (228)
Type : RW - DEC
Software Reset : 2
Description :
This register must contain a XDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1, 2 & 3.
Default value at soft reset assume :
–ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_AUDIO_MDIV_176 : Address : 0xE5 (229)
Type : RW - DEC
Software Reset : 8
Description :
This register must contain a MDIV value that enables
the audio PLL to generate a frequency of ofact*176
kHz for the PCMCK.See table 1,2 & 3.
Default value at soft reset assume :
–ofact == 256 external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_CONFIGURATION registers de-
scription
PLL_SYSTEM_PEL_50 : Address : 0xE6 (230)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a PEL value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_PEH_50 : Address : 0xE7 (231)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a PEH value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_NDIV_50 : Address : 0xE8 (232)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a NDIV value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_XDIV_50 : Address : 0xE9 (233)
Type : RW - DEC
Software Reset : 1
STA016T 18/45
Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 50 MHZ
for the SYSCK. See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_MDIV_50 : Address : 0xEA (234)
Type : RW - DEC
Software Reset : 13
Description :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 50 MHz
for the SYSCK. See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_PEL_42_5Address : 0xE6 (230)
Type : RW - DEC
Software Reset : 126
Description :
This register must contain a PEL value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_PEH_42_5 : Address : 0xE7 (231)
Type : RW - DEC
Software Reset : 223
Description :
This register must contain a PEH value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_NDIV_42_5 : Address : 0xE8 (232)
Type : RW - DEC
Software Reset : 0
Description :
This register must contain a NDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_XDIV_42_5 :Address : 0xE9 (233)
Type : RW - DEC
Software Reset : 1
Description :
This register must contain a XDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
PLL_SYSTEM_MDIV_42_5 : Address : 0xEA (234)
Type : RW - DEC
Software Reset : 10
19/45
STA016TDescription :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume : external crystal provide a CRYCK running at
14.31818 MHz
3.3 I2Sout_CONFIGURATION registers
description
OUTPUT_CONF : Address : 0x66 (102)
Type : RW - DEC
Software Reset : 0
Description :
If set to 1 enable the configurability of the PCM-
BLOCK Output thanks to following registers, else dis-
able this configurability and take embedded default
configuration for PCM-BLOCK registers.
Note that this embedded default configuration can be
retrieved by user thanks to following setting : PCM_DIV = 3;
–PCM_CONF = 0; PCM_CROSS = 0;
PCM_DIV : Address : 0x67 (103)
Type : RW - DEC
Software Reset : 0
Description :
If OUTPUT_CONF == 1, configure the divider to gen-
erate the bit clock of the I2Sout interface, called
BCK0, from PCMCK. according the following relation
: BCKO = PCMCK / 2 * (PCM_DIV+1)
PCM_CONF : Address : 0x68 (104)
Type : RW - DEC
Software Reset : 0
Description :
If OUTPUT_CONF == 1, configure the I2Sout inter-
face according following table.
PCM_CROSS : Address : 0x69 (105)
Type : RW - DEC
Software Reset : 0
STA016T 20/45
Description :
If OUTPUT_CONF == 1, CR[1:0] is used to configure
the output crossbar according following table.
3.4 GPSO_CONFIGURATION registers
description
OUTPUT_CONF : Address : 0x66 (102)
Type : RW - DEC
Software Reset : 0
Description :
Note that embedded default configuration for GPSO
can be retrieved by user thanks to following setting : GPSO_CONF = b00000011;
Note that embedded default configuration for PCM
block is described at previous chapter.
GPSO_CONF : Address : 0x6A (106)
Type : RW - DEC
Software Reset : 0
Description :
If OUTPUT_CONF == 1, this register configure the
GPSO interface.
3.5 I2Sin_CONFIGURATION registers
description
INPUT_CONF : Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
Description :
If set to 1 enable the configurability of the I2Sin Input
thanks to following registers, else disable this config-
urability and take embedded default configuration for
I2Sin registers.
Note that this embedded default configuration can be
retrieved by user thanks to following setting : I_AUDIO_CONFIG_1 = b00000110; I_AUDIO_CONFIG_2 = b11100000; I_AUDIO_CONFIG_3 = b00000001;
21/45
STA016T
I_AUDIO_CONFIG_1: Address : 0x5B (91)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register configure the
I2Sin interface.
I_AUDIO_CONFIG_2 :Address : 0x5C (92)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_3 register description..
I_AUDIO_CONFIG_3 :
Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
ure the phase of the LRCK of the I2Sin.
3.6 CDBSA_CONFIGURATION registers
description
INPUT_CONF : Address : 0x5A (90)
Type : RW - DEC
Software Reset : 0
STA016T 22/45
Description :
If set to 1 enable the configurability of the CD & BS
input interfaces in audio mode thanks to following
registers, else disable this configurability and take
embedded default configuration.
Note that this embedded default configuration can be
retrieved by user thanks to following setting : I_AUDIO_CONFIG1 = b00010010;
// clocks in input
// & polarity negative I_AUDIO_CONFIG2 = b00110010;
// synchro with first data bit
// data unsigned, MSB first I_AUDIO_CONFIG3 = b11001111;
// LRCK phase length is 1 I_AUDIO_CONFIG4 = b00000011;
// LRCK phase length is 16 I_AUDIO_CONFIG5 = 0xFF;
// received 16 bits I_AUDIO_CONFIG6 = 0xFF;
// received 16 bits I_AUDIO_CONFIG7 = 0x00;
// received 16 bits I_AUDIO_CONFIG8 = 0x00;
// received 16 bits I_AUDIO_CONFIG9 = 16;
// data size is 16 I_AUDIO_CONFIG10 = 0x00;
// no use because clock in input I_AUDIO_CONFIG11 = 0x00;
// no use because clock in input
_AUDIO_CONFIG_1 : Address : 0x5B (91)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate CD & BS input interfaces in audio mode.
I_AUDIO_CONFIG_2 :
Address : 0x5C (92)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate CD & BS input interfaces in audio mode.
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STA016T
I_AUDIO_CONFIG_3 : Address : 0x5D (93)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_4 register description..
I_AUDIO_CONFIG_4 : Address : 0x5E (94)
Type : RW - DEC
Software Reset : 0
Description :
If INPUT_CONF == 1, this register is used to config-
urate LR clocks (CD_LRCK & BS_LRCK) of CD & BS
input interfaces in audio mode.
I_AUDIO_CONFIG_5: Address : 0x5F (95)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description.
I_AUDIO_CONFIG_6 : Address : 0x60 (96)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
I_AUDIO_CONFIG_7 : Address : 0x61 (97)
Type : RW - DEC
Software Reset : 0
Description :
See I_AUDIO_CONFIG_8 register description..
