STA003T Fast Delivery |IC PHOENIX CO.,LIMITED

STA003T ,MPEG 2.5 LAYER III AUDIO DECODERBLOCK DIAGRAM: MPEG 2.5 Layer III Decoder Hardware Partitioning.RESET SDA SCL26 3 42I C CONTROL5 9S ..
STA011 , L-band RF front-end for digital radio
STA013 ,MPEG 2.5 LAYER III AUDIO DECODERELECTRICAL CHARACTERISTICS: specifiedDC OPERATING CONDITIONSSymbol Parameter ValueV Power Supply Vo ..
STA013$ ,MPEG 2.5 LAYER III (MP3) AUDIO DECODERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Power Supply -0.3 to 4 VDDV Voltage on Input p ..
STA013$ ,MPEG 2.5 LAYER III (MP3) AUDIO DECODERELECTRICAL CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit NoteI Low Level Inpu ..
STA013$013TR ,MPEG 2.5 LAYER III (MP3) AUDIO DECODERfeatures specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) SO28- Lower sampling frequenc ..
STS100 , Multifunction Telecommunications Switch
STS10DN3LH5 ,Dual N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET (TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10N3LH5 ,N-channel 30 V, 0.019 Ohm;, 10 A, SO-8 STripFET(TM); V Power MOSFETElectrical characteristics(T = 25 °C unless otherwise specified)CASE Table 4. Static Symbol Paramet ..
STS10NF30L ,N-CHANNEL 30VSTS10NF30L®N - CHANNEL 30V - 0.011Ω - 10A SO-8STripFET™ POWER MOSFETPRELIMINARY DATATYPE V R IDSS ..
STS10PF30L ,P-CHANNEL 30VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V = 0) 30 VDS GSV Drain- ..
STS11N3LLH5 , N-channel 30 V, 0.0117 Ω, 11 A, SO-8 STripFET™ V Power MOSFET

STA003T
MPEG 2.5 LAYER III AUDIO DECODER
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio) except 44.1KHz
Audio
- All features specified for Layer III 2 channels
in ISO/IEC13818-3.2 (MPEG 2 Audio) except
22.05KHz Audio
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
except 11.025KHz Audio
DECODES LAYER III STEREO CHANNELS,
DUAL CHANNEL, SINGLE CHANNEL
(MONO)
SUPPORTING THE MPEG 1 & 2 SAMPLING
FREQUENCIES AND THE EXTENSION TO
MPEG 2.5:
48, 32, 24, 16, 12, 8 KHz
ACCEPTS MPEG 2.5 LAYER III ELEMEN-
TARY COMPRESSED BITSTREAM WITH
DATA RATE FROM 8 Kbit/s UP TO 128 Kbit/s
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
SERIAL BITSTREAM INPUT INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C IN-
TERFACE.
SERIAL PCM OUTPUT INTERFACE (I2S
AND OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR OUT-
PUT PCM CLOCK GENERATION
LOW POWER DATA ELABORATION FOR
POWER CONSUMPTION OPTIMISATION
CRC CHECK AND SYNCHRONISATION ER-
ROR DETECTION WITH SOFTWARE INDI-
CATORS2 C CONTROL BUS
LOW POWER 3.3V CMOS TECHNOLOGY
14.72MHz EXTERNAL INPUT CLOCK OR
BUILT-IN XTAL OSCILLATOR
APPLICATIONS
STARMAN SATELLITE RADIO RECEIVER
DESCRIPTION
The STA003T is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of de-
coding Layer III compressed elementary streams,
as specified in MPEG 1 and MPEG 2 ISO stand-
ards. The device decodes also elementary streams
compressed by using low sampling rates, as speci-
fied by MPEG 2.5.
STA003T receives the input data through a Serial
Input Interface. The decoded signal is a stereo,
mono, or dual channel digital output that can be
sent directly to a D/A converter, by the PCM Out-
put Interface. This interface is software program-
mable to adapt the STA003T digital output to the
most common DACs architectures used on the
market.
The functional STA003T chip partitioning is de-
scribed in Fig.1.
STA003T
MPEG 2.5 LAYER III AUDIO DECODER
Figure 1. BLOCK DIAGRAM: MPEG 2.5 Layer III Decoder Hardware Partitioning.
THERMAL DATA
Figure 2. PIN CONNECTION
Fig. 2 describes the STA003T pinout in SO28 package
STA003T
PIN DESCRIPTION
Note: In functional mode TESTEN must be connected to VDD, SCANEN to ground.
ABSOLUTE MAXIMUM RATINGS
STA003T
1. ELECTRICAL CHARACTERISTICS: VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise
specified
DC OPERATING CONDITIONS
GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress
on the pin.
Note 2: Human Body Model.
DC ELECTRICAL CHARACTERISTICS
Note 1: Takes into account 200mV voltage drop in both supply lines.
Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Note 1: Min. condition: VDD = 2.7V, 125°C Min process
Max. condition: VDD = 3.6V, -20°C Max.
POWER DISSIPATION
STA003T
Figure 3. Test Circuit
Test Load Circuit
Test Load
2. FUNCTIONAL DESCRIPTION
2.1 - Clock Signal
The STA003T input clock is derivated from an ex-
ternal source or from a 14.72 MHz crystal.
XTI is an input Pad with specific levels.
The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical
CMOS pads.
TTL compatibility
The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD =
3V TTL min high level = 2.0V while XTI min high level = 2.2V)
STA003T
Figure 5. Serial Input Interface Clocks
Figure 4. MPEG Decoder Interfaces.
2.2 - Serial Input Interface
STA003T receives the input data thought the Se-
rial Input Interface (Fig.4). It is a serial communi-
cation interface connected to the SDI (Serial Data
Input) and SCKR (Receiver Serial Clock).
The interface can be configured to receive data
sampled on both rising and falling edge of the
SCKR clock.The BIT_EN pin, when set to low,
forces the bitstream input interface to ignore the
incoming data. The possible configurations are
described in Fig. 5.
The bitstream must be sent MSB first to
STA003T.
2.3 - PLL & Clocks Generation System
The STA003T has a clock generation system that
is used by the device core to adjust the core
speed, for power saving, adapting the processing
speed to the needs of the decoded audio pro-
gram. The clocks generation system is even used
to generate all the PCM output interface clocks:
SCKT, LRCKT, and OCLK.
The block diagram in Fig. 6 is a description of
STA003T clocks generation system. The input of
STA003T clocks system is a 14.72MHz input
clock.
Internally it is composed by a PLL loop, and the
VCO output is fed into a divider stage, used to
program the Core speed and the PCM interface
clocks. Several registers are programmed by the
Layer III decoder core, and by the user, when a
specific interface configuration is required.
The PLL can be programmed by a set of regis-
ters, as described in the I2C Registers section,
The particularity of the STA003T clocks genera-
tion system is the possibility to modify the Audio
Sampling Frequency (LRCKT) in steps of few
ppm to compensate dynamically the audio sam-
pling rate offset between the receiver and the
broadcasting station.
The compensation is done by the STA003T core
without requiring interaction with the application
controller and the sampling rate compensation
produces a jittering effect outside the audible
range.
The device implements a sampling rate offset
control receiving by STA002 (WorldSpace Chan-
nel Decoder) a dedicated signal every decoded
Broadcast Channel Frame (432ms).
STA003T
This signal is used as interrupt signal inside
STA003T.
Within a WorldSpace Broadcast Frame, there are
a fixed number of PCM samples, depending on
the nominal audio sampling rate (Fig. 7).
Using this information, with the SRC_INT signal
as external timer source, STA003T performs the
compensation of the audio sampling rate.
The sampling rate control is done by the
STA003T core, by setting PLLFRAC internal reg-
ister. The PLLFRAC value is updated, in steps of
few ppms, by Update PLLFRAC signal.
Figure 6. PLL and Clocks Generation System
MPEG Frames into 1 BC Frame: 18 for 48 & 24 KHz 12 for 32 & 16 KHz 9 for 12 KHz 6 for 8 KHz 10368 for 24 KHz 13824 for 32 KHz 6912 for 16 KHz 5184 for 12 KHz 3456 for 8 KHz
SRC_INT
Figure 7. WorldSpace BC Framing
STA003T
2.4 - PCM Output Interface
The decoded audio data are output in serial PCM
format. The interface consists of the following sig-
nals:
SDO PCM Serial Data Output
SCKT PCM Serial Clock Output
LRCLK Left/Right Channel Selection Clock
The output samples precision is selectable from
16 to 24 bits/word, by setting the output precision
(16, 18, 20 and 24 bits) with PCMCONF register.
Data can be output either with the most signifi-
cant bit first (MS) or least significant bit first (LS),
selected by writing into a flag of the PCMCONF
register.
Figure 8 gives a description of the STA003T PCM
Output Formats.
The sample rates set decoded by STA003T is de-
scribed in Table 1.
Figure 8. PCM Output Formats
Table 1: MPEG Sampling Rates (KHz)
2.5 - STA003T Decoding States
There are three different decoder states: Idle,
Init, and Decode. Commands to change the de-
coding states are described in the STA003T I2C
registers description.
Idle Mode
In this mode the decoder is waiting for the RUN
command. This mode should be used to initialise
the configuration register of the device. The DAC
connected to STA003T can be initialised during
this mode (set MUTE to 1).
Init Mode
"PLAY" and "MUTE" changes are ignored in this
mode. The internal state of the decoder will be
updated only when the decoder changes from the
state "init" to the state "decode". The "init" phase
ends when the first decoded samples are at the
output stage of the device.
Decode Mode
This mode is completely described by the follow-
ing table:
STA003T
3 - I2 C BUS SPECIFICATION
The STA003T supports the I2 C protocol. This pro-
tocol defines any device that sends data on to the
bus as a transmitter and any device that reads
the data as a receiver. The device that controls
the data transfer is known as the master and the
others as the slave. The master always starts the
transfer and provides the serial clock for synchro-
nisation. The STA003T is always a slave device
in all its communications.
3. 1 - COMMUNICATION PROTOCOL
3.1.0 - Data transition or change
Data changes on the SDA line must only occur
when the SCL clock is low. SDA transition while
the clock is high are used to identify START or
STOP condition.
3.1.1 - Start condition
START is identified by a high to low transition of
the data bus SDA signal while the clock signal
SCL is stable in the high state. A START condi-
tion must precede any command for data transfer.
3.1.2 - Stop condition
STOP is identified by low to high transition of the
data bus SDA signal while the clock signal SCL is
stable in the high state. A STOP condition termi-
nates communications between STA003T and
the bus master.
3.1.3 - Acknowledge bit
An acknowledge bit is used to indicate a success-
ful data transfer. The bus transmitter, either mas-
ter or slave, releases the SDA bus after sending
8 bit of data.
During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.
3.1.4 - Data input
During the data input the STA003T samples the
SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can change only when the SCL line
is low.
3.2 - DEVICE ADDRESSING
To start communication between the master and
the STA003T, the master must initiate with a start
condition. Following this, the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.
The 7 most significant bits are the device address
identifier, corresponding to the I2 C bus definition.
For the STA003T these are fixed as 1000011.
The 8th bit (LSB) is the read or write operation
RW, this bit is set to 1 in read mode and 0 for
write mode. After a START condition the
STA003T identifies on the bus the device ad-
dress and, if a match is found, it acknowledges
the identification on SDA bus during the 9th bit
time. The following byte after the device identifi-
cation byte is the internal space address.
3.3 - WRITE OPERATION (see fig. 9)
Following a START condition the master sends a
device select code with the RW bit set to 0.
The STA003T acknowledges this and waits for
the byte of internal address.
After receiving the internal bytes address the
STA003T again responds with an acknowledge.
3.3.1 - Byte write
In the byte write mode the master sends one data
byte, this is acknowledged by STA003T. The
master then terminates the transfer by generating
a STOP condition.
3.3.2 - Multibyte write
The multibyte write mode can start from any inter-
nal address. The transfer is terminated by the
master generating a STOP condition.
Figure 9. Write Mode Sequence
STA003T
3.4 - READ OPERATION (see Fig. 10)
3.4.1 - Current byte address read
The STA003T has an internal byte address
counter. Each time a byte is written or read, this
counter is incremented.
For the current byte address read mode, follow-
ing a START condition the master sends the de-
vice address with the RW bit set to 1.
The STA003T acknowledges this and outputs the
byte addressed by the internal byte address
counter. The master does not acknowledge the
received byte, but terminates the transfer with a
STOP condition.
3.4.2 - Sequential address read
This mode can be initiated with either a current
address read or a random address read. How-
ever in this case the master does acknowledge
the data byte output and the STA003T continues
to output the next byte in sequence.
To terminate the streams of bytes the master
does not acknowledge the last received byte, but
terminates the transfer with a STOP condition.
The output data stream is from consecutive byte
addresses, with the internal byte address counter
automatically incremented after one byte output.
4 - I2 C REGISTERS
The following table gives a description of the
MPEG Source Decoder (STA003T) register list.
The first column (HEX_COD) is the hexadecimal
code for the sub-address.
The second column (DEC_COD) is the decimal
code.
The third column (DESCRIPTION) is the descrip-
tion of the information contained in the register.
The fourth column (RESET) inidicate the reset
value if any. When no reset value is specifyed,
the default is "undefined".
The fifth column (R/W) is the flag to distinguish
register "read only" and "read and write", and the
useful size of the register itself.
Each register is 8 bit wide. The master shall oper-
ate reading or writing on 8 bits only.2 C REGISTERS
Figure 10. Read Mode Sequence
STA003T
2 C REGISTERS (continued)Note:
1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information.
2) RESERVED: register used for production test only, or for future use.
STA003T
4.1 - STA003T REGISTERS DESCRIPTION
The STA003T device includes 128 I2 C registers.
In this document, only the user-oriented registers
are described. The undocumented registers are
reserved. These registers must never be ac-
cessed (in Read or in Write mode). The Read-
Only registers must never be written.
The following table describes the meaning of the
abbreviations used in the I2C registers descrip-
tion:
VERSION
Address: 0x00
Type: RO
MSB LSB
The VERSION register is read-only and it is used
to identify the IC on the application board.
IDENT
Address: 0x01
Type: RO
Software Reset: 0xAC
Hardware Reset: 0xAC
MSB LSB
IDENT is a read-only register and is used to iden-
tify the IC on an application board. IDENT always
has the value "0xAC"
PLLCTL
Address: 0x05
Type: R/W
Software Reset: 0x21
Hardware Reset: 0x21
MSB LSB
UPD_FRAC: when is set to 1, updates FRAC in
the switching circuit. It is set to 1 after autoboot.
XTI2OCLK: when is set to 1, uses the XTI as in-
put of the divider X instead of VCO output. It is
set to 0 on HW reset.
XTI2DSPCLK: when is set to 1, uses the XTI as
input of the divider S instead of VCO output. It is
set to 0 on HW reset.
PLLDIS: when set to 1, the VCO output is dis-
abled. It is set to 0 on HW reset.
SYS2OCLK: when is set to 1, the OCLK fre-
quency is equal to the system frequency. It is
useful for testing. It is set to 0 on HW reset.
OCLKEN: when is set to 1, the OCLK pad is en-
able as output pad. It is set to 1 on HW reset.
XTODIS: when is set to 1, the XTO pad is dis-
abled. It is set to 0 on HW reset.
XTO_BUF: when this bit is set, the pin nr. 28
(VDD_5/CLK_OUT) is enabled as buffered (4mA)
master clock output (CLK_OUT). It is set to 0 af-
ter autoboot.
PLLCTL_M
Address: 0x06
Type: R/W
Software Reset: 0x0C
Hardware Reset: 0x0C
PLLCTL_N
Address: 0x07
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The M and N registers are used to configure the
STA003T PLL by DSP embedded software.
M and N registers are R/W type but they are
completely controlled, on STA003T, by DSP soft-
ware.
STA003T
SCKL_POL
Address: 0x0D
Type: R/W
Software Reset: 0x04
Hardware Reset: 0x04
MSB LSB (1) (2)
X = don’t care
SCKL_POL is used to select the working polarity
of the Input Serial Clock (SCKR).
(1) If SCKL_POL is set to 0x00, the data (SDI)
are sent with the falling edge of SCKR
and sampled on the rising edge.
(2) If SCKL_POL is set to 0x04, the data (SDI)
are sent with the rising edge of SCKR and
sampled on the falling edge.
ERROR_CODE
Address: 0x0F
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB (1) (2) (3)
X = don’t care
ERROR_CODE register contains the last error
occourred if any. The codes can be as follows:
SOFT_RESET
Address: 0x10
Type: WO
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
X = don’t care; 0 = normal operation; 1 = reset
When this register is written, a soft reset occours.
The STA003T core command register and the in-
terrupt register are cleared. The decoder goes in
to idle mode.
PLAY
Address: 0x13
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
X = don’t care; 0 = normal operation; 1 = play
The PLAY command is handled according to the
state of the decoder, as described in section 2.5.
PLAY only becomes active when the decoder is
in DECODE mode.
STA003T
MUTE
Address: 0x14
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
X = don’t care; 0 = normal operation; 1 = mute
The MUTE command is handled according to the
state of the decoder, as described in section 2.5.
MUTE sets the clock running.
CMD_INTERRUPT
Address: 0x16
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
X = don’t care;
0 = normal operation;
1 = write into I2 C/Ancillary Data
The INTERRUPT is used to give STA003T the
command to write into the I2C/Ancillary Data
Buffer (Registers: 0x59 ... 0x5D). Every time the
Master has to extract the new buffer content (5
bytes) it writes into this register, setting it to a
non-zero value.
SYNCSTATUS
Address: 0x40
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
STA003T
ANCCOUNT_L
Address: 0x41
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB LSB
ANCCOUNT_H
Address: 0x42
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
ANCCOUNT_H
MSB LSB
ANCCOUNT registers are logically concatenated
and indicate the number of Ancillary Data bits
available at every correctly decoded MPEG
frame.
HEAD_H[23:16]
MSB LSB
x = don’t care
HEAD_M[15:8]
MSB LSB
HEAD_L[7:0]
MSB LSB
Address: 0x43, 0x44, 0x45
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
Head[1:0] emphasis
Head[2] original/copy
Head[3] copyrightHead
[5:4] mode extension
Head[7:6] mode
Head[8] private bit
Head[9] padding bit
Head[11:10] sampling frequency index
Head[15:12] bitrate index
Head[16] protection bit
Head[18:17] layer
Head[19] ID
Head[20] ID_ex
The HEAD registers can be viewed as logically
concatenated to store the MPEG Layer III Header
content. The set of three registers is updated
every time the synchronisation to the new MPEG
frame is achieved .
STA003T
The meaning of the flags are shown in the follow-
ing tables:
MPEG IDs
Layer
in Layer III these two flags must be set always to
"01".
Protection_bit
It equals "1" if no redundancy has been added
and "0" if redundancy has been added.
Bitrate_index
indicates the bitrate (Kbit/sec) depending on the
MPEG ID.
Sampling Frequency
indicates the sampling frequency of the encoded
audio signal (KHz) depending on the MPEG ID
Padding bit
if this bit equals ’1’, the frame contains an addi-
tional slot to adjust the mean bitrate to the sam-
pling frequency, otherwise this bit is set to ’0’.
Private bit
Bit for private use. This bit will not be used in the
future by ISO/IEC.
Mode
Indicates the mode according to the following ta-
ble. The joint stereo mode is intensity_stereo
and/or ms_stereo.
Mode extension
These bits are used in joint stereo mode. They in-
dicates which type of joint stereo coding method
is applied. The frequency ranges, over which the
intensity_stereo and ms_stereo modes are ap-
plied, are implicit in the algorithm.
Copyright
If this bit is equal to ’0’, there is no copyright on
the bitstream, ’1’ means copyright protected.
Original/Copy
This bit equals ’0’ if the bitstream is a copy, ’1’ if it
is original.
Emphasis
Indicates the type of de-emphasis that shall be
used.
STA003T

Partno	Mfg	Dc	Qty	Available	Descript
STA003T	ST	N/a	1100	avai	MPEG 2.5 LAYER III AUDIO DECODER