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ST92195B5B1
32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
January 2000 1/22
Rev. 2.5
ST92195B
32-64K ROM HCMOS MCU WITH
ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER
DATA BRIEFING Register File based 8/16bit Core Architecture
with RUN, WFI, SLOW and HALT modes 0°Cto +70°C operating temperature range Upto24 MHz. operation@ 5V±10% Min. instruction cycle time: 165nsat24 MHz. 32, 48, 56or64 Kbytes ROM 256 bytes RAMof Register file (accumulatorsor
index registers) 256 bytesof on-chip static RAM 2,6or8 Kbytesof TDSRAM (Teletext and
Display Storage RAM) 28 fully programmable I/O pins Serial Peripheral Interface Flexible Clock controller for OSD, Data Slicer
and Core clocks running froma single low
frequency external crystal. Enhanced display controller with26 rowsof
40/80 characters Serial and Parallel attributes 10x10 dot matrix, 512 ROM characters, defin-
ableby user 4/3 and 16/9 supportedin 50/60Hz and 100/
120 Hz mode Rounding, fringe, double width, double height,
scrolling, cursor, full background color, half-
intensity color, translucency and half-tone
modes Teletext unit, including Data Slicer, Acquisition
Unit andupto8 Kbytes RAMfor data storage VPS and Wide Screen Signalling slicer (on
some devices) Integrated Sync Extractor and Sync Controller 14-bit Voltage Synthesis for tuning reference
voltage Up to6 external interrupts plus one Non-
Maskable Interrupt 8x 8-bit programmable PWM outputs with 5V
open-drainor push-pull capability 16-bit watchdog timer with 8-bit prescaler One 16-bit standard timer with 8-bit prescaler 4-channel A/D converter; 5-bit guaranteed Rich instruction set and14 addressing modes Versatile development tools, including
Assembler, Linker, C-compiler, Archiver,
Source Level Debugger and hardware
emulators with Real-Time Operating System
available from third parties Pin-compatible EPROM and OTP devices
available
Device Summary
Device Program
Memory
TDS
RAM
VPS/
WSS Package
ST92195B1 32K ROM 2K Yes
PSDIP56/
TQFP64
ST92195B2 32K ROM 6K No
ST92195B3 32K ROM 6K Yes
ST92195B4 48K ROM 6K Yes
ST92195B5 48K ROM 8K Yes
ST92195B6 56K ROM 8K Yes
ST92195B7 64K ROM 8K Yes
ST92T195B7 64K OTP 8K Yes
ST92E195B7 64K EPROM 8K Yes CSDIP56
/CQFP64
TQFP64
PSDIP56
See endof documentfor ordering information
2/22
ST92195B- GENERAL DESCRIPTION GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92195B microcontrolleris developed and
manufacturedby STMicroelectronics usinga pro-
prietary n-well HCMOS process. Its performance
derives from the useofa flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasksto get the maximum useof
core resources. The ST92195B MCU supports low
power consumption and low voltage operation for
power-efficient and low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File and the
Interrupt controller.
The general-purpose registers canbe usedas ac-
cumulators, index registers,or address pointers.
Adjacent register pairs makeup 16-bit registersfor
addressingor 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
Two basic addressable spaces are available: the
Memory space and the Register File, which in-
cludes the control and status registersof the on-
chip peripherals.
1.1.2 Power Saving Modes optimize performance versus power consump-
tion,a rangeof operating modes canbe dynami-
cally selected.
Run Mode. Thisis the full speed execution mode
with CPU and peripherals runningat the maximum
clock speed deliveredby the Phase Locked Loop
(PLL)of the Clock Control Unit (CCU).
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt requestis acknowledged. During
WFI, the CPU clockis halted while the peripheral
and interrupt controller keep runningata frequen- programmable via the CCU.In this mode, the
power consumptionof the device canbe reduced more than 95% (Low power WFI).
Halt Mode. When executing the HALT instruction,
andif the Watchdogis not enabled, the CPU and
its peripherals stop operating and the statusof the
machine remains frozen (the clock is also
stopped).A resetis necessaryto exit from Halt
mode.
1.1.3 I/O Portsto 28 I/O lines are dedicatedto digital Input/
Output. These lines are grouped intoupto five I/O
Ports and canbe configured onabit basis under
software controlto provide timing, status signals,
timer and output, analog inputs, external interrupts
and serialor parallel I/O.
1.1.4 TV Peripherals setof on-chip peripherals forma complete sys-
temfor TV set and VCR applications: Voltage Synthesis VPS/WSS Slicer Teletext Slicer Teletext Display RAM OSD
1.1.5 On Screen Display
The human interfaceis providedby the On Screen
Display module, this can produceupto26 linesofto80 characters froma ROM defined 512 char-
acter set. The character resolutionis 10x10 dot.
Four character sizes are supported. Serial at-
tributes allow the userto select foreground and
background colors, character size and fringe back-
ground. Parallel attributes can be usedto select
additional foreground and background colors and
underlineona characterby character basis.
1.1.6 Teletext and Display Storage RAM
The internal Teletext and Display storage RAM
canbe usedto store Teletext pagesas wellas Dis-
play parameters.
3/22
ST92195B- GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
1.1.7 Teletext, VPS and WSS Data Slicers
The three on-board data slicers usinga single ex-
ternal crystal are usedto extract the Teletext, VPS
and WSS information from the video signal. Hard-
ware Hamming decodingis provided.
1.1.8 Voltage Synthesis Tuning Control
14-bit Voltage Synthesis using the PWM (Pulse
Width Modulation)/BRM (Bit Rate Modulation)
technique canbe usedto generate tuning voltages
for TV set applications. The tuning voltageis out-
puton oneof two separate output pins.
1.1.9 PWM Output
Controlof TV settings can be made with upto
eight 8-bit PWM outputs, witha maximum frequen-of 23,437Hzat 8-bit resolution (INTCLK= 12
MHz). Low resolutions with higher frequency oper-
ation canbe programmed.
1.1.10 Serial Peripheral Interface (SPI)
The SPI busis usedto communicate with external
devices via the SPI,or I C bus communication
standards. The SPI usesa single data linefor data
input and output.A second lineis used fora syn-
chronous clock signal.
1.1.11 Standard Timer (STIM)
The ST92195B has one Standard Timer (STIM0)
that includesa programmable 16-bit down counter
andan associated 8-bit prescaler with Single and
Continuous counting modes.
1.1.12 Analog/Digital Converter (ADC) addition thereisa 4-channel Analogto Digital
Converter with integral sample and hold, fast
5.75μs conversion time and 6-bit guaranteed reso-
lution.
4/22
ST92195B- GENERAL DESCRIPTION
INTRODUCTION (Cont’d)
Figure1. ST92195B Block Diagram
MEMORY
BUS
I/O
PORT0
REGISTER
BUS
VOLTAGE
SYNTHESIS
PWM
D/A CON-
VERTER
SPI
I/O
PORT4
I/O
PORT5to64
Kbytes ROM
DATA
SLICER ACQUI-
SITION
UNIT
SYNC.
EXTRAC-
TIONto8
Kbytes
TDSRAM TRI
256 bytes
RAM
STANDARD
TIMER
TIMING AND
CLOCK CTRL
16-BIT
TIMER/
WATCHDOG
VPS/WSS
DATA
SLICER
I/O
PORT2
ADC
CVBS1
I/O
PORT3
SYNC
CONTROL
VSYNC
HSYNC/CSYNC
SCREEN
DISPLAY
FREQ.
MULTIP. PXFM
NMI
INT[7:4]
INT2
256 bytes
Register File
ST9+ CORE
8/16-bit
CPU
Interrupt
Management
RCCU
OSCIN
OSCOUT
RESET
RESETO
P0[7:0]
WSCR
WSCF
CVBS2
R/G/B/FB
PWM[7:0]
SDO/SDI
SCK
INT0
STOUT
MMU
MCFM
TXCF
TSLU
AIN[4:1]
VSO[2:1]
EXTRG
P2[5:0]
P4[7:0]
P5[1:0]
P3[7:4]
CSO
All alternate functions (Italic characters) are mappedon Ports0,2,3,4 and5
5/22
ST92195B- GENERAL DESCRIPTION
1.2 PIN DESCRIPTION
Figure2. 64-Pin Package Pin-Out
N.C.= Not connected
GND
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
SDO/SDI/P5.1
INT2/SCK/P5.0
VDD
JTDO
P0.3P0.4P0.5P0.6P0.7RESETP2.0/INT7P2.1/INT5/AIN1P2.2/INT0/AIN2P2.3/INT6/VS01P2.4/NMIP2.5/AIN3/INT4/VS02OSCINOSCOUTVSS
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRST0
GND
N.C.
N.C.N.C.
WSCF
/WSCRAVDD3
TEST0
MCFM
JTCK
TXCF
CVBSO
AVDD2
JTMS
CVBS2CVBS1
AGND
N.C.64 32
6/22
ST92195B- GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
RESET Reset (input, active low). The ST9+is ini-
tialisedby the Reset signal. With the deactivation RESET, program execution begins from the
Program memory location pointedtoby the vector
containedin program memory locations 00h and
01h.
R/G/B Red/Green/Blue. Video color analog DAC
outputs. Fast Blanking. Video analog DAC output.DD Main power supply voltage (5V±10%, digital)
WSCF, WSCR Analog pins for the VPS/WSS slic-. These pins mustbe tiedto groundor not con-
nected.
VPP: On EPROM/OTP devices, the WSCR pinis
replacedbyVPP whichis the programming voltage
pin. VPP shouldbe tiedto GNDin user mode.
MCFM Analog pin for the display pixel frequency
multiplier.
OSCIN, OSCOUT Oscillator (input and output).
These pins connecta parallel-resonant crystal
(24MHz maximum),or an external sourceto the
on-chip clock oscillator and buffer. OSCINis the
inputof the oscillator inverter and internal clock
generator; OSCOUTis the outputof the oscillator
inverter.
VSYNC Vertical Sync. Vertical video synchronisa-
tion inputto OSD. Positiveor negative polarity.
HSYNC/CSYNC Horizontal/Composite sync. Hori-
zontalor composite video synchronisation inputto
OSD. Positiveor negative polarity.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
AVDD3 Analog VDDof PLL. This pin mustbe tiedVDD externally.
GND Digital circuit ground.
AGND Analog circuit ground (mustbe tied exter-
nallyto digital GND).
CVBS1 Composite video input signalfor the Tele-
text slicer and sync extraction.
CVBS2 Composite video input signalfor the VPS/
WSS slicer. Pin AC coupled.
AVDD1, AVDD2 Analog power supplies (must be
tied externallyto AVDD3).
TXCF Analog pinfor the Teletext slicer line PLL.
CVBSO, JTDO, JTCK Test pins: leave floating.
TEST0 Test pins: mustbe tiedto AVDD2.
JTRST0 Test pin: must be tiedto GND.
Figure3. 56-Pin Package Pin-Out
INT7/P2.0
RESET
P0.7
P0.6
P0.5
P0.4
P0.3
AIN4/P0.2
P0.1
P0.0
CSO/RESET0/P3.7
P3.6
P3.5
P3.4
SDI/SDO/P5.1
SCK/INT2/P5.0
VDD
JTDO
WSCFVPP /WSCR
AVDD3
TEST0
MCFM
JTCK
P2.1/INT5/AIN1
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRSTO
GND
AGND
CVBS1
CVBS2
JTMS
AVDD2
CVBSO
TXCF
7/22
ST92195B- GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure4. ST92195B Required External components (56-pin package)
+5V
+5V
P20
P24
P05
P50
P46
P37
P47
P04
P45
P03
P01
P44
P07
P36
P51
P21
P02
P00
P43
P41
P22
P35
P34
P25
P42
P40
P23
P06
C16 2.2nFR415k
C13 4.7nF
C10 4.7nF 82pF 82pF5.6k5.6k C14 82pF
C11 22pF
1μF
RST
1N4148
C12 470nF 22pF 10μF 100nF
100nF
C15 100nF 100nF 10μF
10uH10k
10uH
4Mhz
SDIP56
ST92195B 56
P2.0/INT7 P2.1/INT5/AIN1
RESETN
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2/AIN4
P0.1
P0.0
P3.7/RESET0/CSO
P3.6
P3.5
P3.4
P5.1/SDI/SDO
P5.0/SCK/INT2
VDD
JTDO
WSCF
WSCR
AVDD3
TEST0
MCFM
JTCK
P2.2/INT0/AIN2
P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
P4.7/PWM7/EXTRG/STOUT
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
P4.3/PWM3/TSLU/HT
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
HSYNC/CSYNC
AVDD1
PXFM
JTRST0
GND
AGND
CVBS1
CVBS2
JTMS
AVDD2
CVBSO
TXCF
CVBS
VSYNC
HSYNC
8/22
ST92195B- GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
Figure5. ST92195B Required External Components (64-pin package)
+5V
+5V
P20 P25
P36
P05
P46
P03
P35
P40
P06
P45
P34
P42
P07
P44
P5.1
P37
P43
P21
P47
P24
P01
P41
P22
P00
P04
P02
P23
P5.0
5.6k
4Mhz
5.6k 10k
1N4148
10uH
10uH
C12
100nF 82pF
RST
C13
10uF 82pF
C15 4.7nF 1μF
10uF
100nF
C14 22pF 22pF
100nF 100nF 100nF
C10
4.7nF
C11
100nF
QFP64
ST92195B54535251504931302923181920212224252627281758596061626364
VSS
P2.1/INT5/AIN1
P0.2/AIN4
P0.1
P0.0
P3.7/RESET0/CSO
P3.6
P3.5
P3.4
P5.1/SDI/SDO
P5.0/SCK/INT2
VDD
P2.2/INT0/AIN2P2.3/INT6/VS01
P2.4/NMI
P2.5/AIN3/INT4/VS02
OSCIN
OSCOUT
VDD
GND
EXTRG/SLOUT/P4.7/PWM7
P4.6/PWM6
P4.5/PWM5
P4.4/PWM4
HT/TSLU/P4.3/PWM3
P4.2/PWM2
P4.1/PWM1
P4.0/PWM0
VSYNC
CSYNC/HSYNC
AVDD1
PXFM
JTRST0
GNDAGNDCVBS1CVBS2MCFMNCWSCFWSCRAVDD3TEST0JTCKTXCFCVBSOAVDD2JTMSNC
JTDO
INT7/P2.0
RESETN
P0.7P0.6P0.5P0.4P0.3VDD
HSYNC
VSYNC
9/22
ST92195B- GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
P0[7:0], P2[5:0], P3[7:4], P4[7:0], P5[1:0]
I/O Port Lines (Input/Output, TTLor CMOS com-
patible). lines grouped into I/O ports,bit programmable general purpose I/Oor as Alternate functions
(see I/O section).
Important: Note that open-drain outputs are for
logic levels only and are not true open drain.
1.2.1 I/O Port Alternate Functions.
Each pinof the I/Oportsof the ST92195B may as-
sume software programmable Alternate Functions
(see Table 1).
Table1. ST92195B I/O Port Alternate Function Summary
Port
Name
General
PurposeI/O
Pin No. Alternate Functions
TQFP64 SDIP56
P0.0
Allports useable
for general pur-
poseI/O (input,
outputor bidi-
rectional) 10 I/O
P0.1 3 9 I/O
P0.2 2 8 AIN4 I A/D Analog Data Input4
P0.3 63 7 I/O
P0.4 62 6 I/O
P0.5 61 5 I/O
P0.6 60 4 I/O
P0.7 59 3 I/O
P2.0 57 1 INT7 I External Interrupt7
P2.1 56 56 AIN1 I A/D Analog Data Input1
INT5 I External Interrupt5
P2.2 55 55 INT0 I External Interrupt0
AIN2 I A/D Analog Data Input2
P2.3 54 54 INT6 I External Interrupt6
VSO1 O Voltage Synthesis Output1
P2.4 53 53 NMI I Non Maskable Interrupt Input
P2.5 52 52
AIN3 I A/D Analog Data Input3
INT4 I External Interrupt4
VSO2 O Voltage Synthesis Output2
P3.4 8 14 I/O
P3.5 7 13 I/O
P3.6 6 12 I/O
P3.7 5 11 RESET0 O Internal Reset Output
CSO O Composite Sync output
P4.0 40 42 PWM0 O PWM Output0
P4.1 41 43 PWM1 O PWM Output1
P4.2 42 44 PWM2 O PWM Output2
P4.3 43 45
PWM3 O PWM Output3
TSLU O Translucency Digital Output O Half-tone Output
P4.4 44 46 PWM4 O PWM Output4
10/22
ST92195B- GENERAL DESCRIPTION
1.2.2 I/O Port Styles
Legend:
AF= Alternate Function, BID= Bidirectional, OD= Open Drain= Push-Pull, TTL= TTL Standard Input Levels
Howto Read this Table configure the I/O ports, use the informationin
this table and the Port Bit Configuration Tablein
the I/O Ports Chapterof the datasheet.
Port Style= the hardware characteristics fixed for
each port line.
Inputs:If port style= Standard I/O, either TTLor CMOS
input level canbe selectedby software.If port style= Schmitt trigger, selecting CMOSor
TTL inputby software hasno effect, the input will
alwaysbe Schmitt Trigger.
Weak Pull-Up= This column indicatesifa weak
pull-upis presentor not.If WPU= yes, then the WPU canbe enabled/dis-
ableby softwareIf WPU= no, then enabling theWPUby software
has no effect
Alternate Functions (AF)= More than one AF
cannotbe assignedtoan external pinat the same
time: alternate function canbe selectedas follows. Inputs: AFis selected implicitlyby enabling the corre-
sponding peripheral. Exceptionto this are ADC
analog inputs which mustbe explicitly selected AFby software.
P4.5
Allports useable
for general pur-
poseI/O (input,
outputor bidi-
rectional) 47 PWM5 O PWM Output5
P4.6 46 48 PWM6 O PWM Output6
P4.7 47 49
EXTRG I A/D Converter External Trigger Input
PWM7 O PWM Output7
STOUT O Standard Timer Output
P5.0 14 20
INT2 I External Interrupt2
SCK O SPI Serial Clock
P5.1 13 19
SDO O SPI Serial Data Out
SDI I SPI Serial DataIn
Port
Name
General
PurposeI/O
Pin No.
Alternate FunctionsTQFP64 SDIP56
Pins Weak Pull-Up Port Style Reset Values
P0[7:0] no StandardI/O BID/ OD/ TTL
P2[5,4,3,2] no StandardI/O BID/ OD/ TTL
P2[1,0] no Schmitt trigger BID/ OD/ TTL
P3.7 yes StandardI/O AF/PP/ TTL
P3[6,5,4] no StandardI/O BID/ OD/ TTL
P4[7:0] no StandardI/O BID/ OD/ TTL
P5[1:0] no StandardI/O BID/ OD/ TTL
11/22
ST92195B- GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d) Outputsor Bidirectional Lines:In the caseof Outputsor I/Os, AFis selected
explicitlyby software.
Example1: ADC trigger digital input
AF: EXTRG, Port: P4.7, Port Style: Standard I/O.
Write the port configuration bits (for TTL level):
P4C2.7=1
P4C1.7=0
P4C0.7=1
Enable the ADC triggerby softwareas described the ADC chapter.
Example2: PWM0 output
AF: PWM0, Port: P4.0
Write the port configuration bits (for output push-
pull):
P4C2.0=0
P4C1.0=1
P4C0.0=1
Example3: ADC analog input
AF: AIN1, Port: P2.1, Port style: does not applyto
analog inputs
Write the port configuration bits:
P2C2.1=1
P2C1.1=1
P2C0.1=1

Partno	Mfg	Dc	Qty	Available	Descript
ST92195B5B1	ST	N/a	13	avai	32-64K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY AND TELETEXT DATA SLICER