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ST8024-ST8024CD
SMARTCARD INTERFACE
1/23January 2005 IC CARD INTERFACE 3 OR 5 V SUPPLY FOR THE IC (VDD AND
GND)
� THREE SPECIFICALLY PROTECTED
HALF-DUPLEX BI-DIRECTIONAL
BUFFERED I/O LINES TO CARD
CONTACTS C4, C7 AND C8 DC/DC CONVERTER FOR VCC
GENERATION SEPARATELY POWERED
FROM A 5 V ± 20% SUPPLY (VDDP AND
PGND) 3 OR 5 V ±5% REGULATED CARD SUPPLY
VOLTAGE (VCC ) WITH APPROPRIATE
DECOUPLING HAS THE FOLLOWING
CAPABILITIES:
– ICC < 80 mA at VDDP = 4 to 6.5 V
– HANDLES CURRENT SPIKES OF 40 nAs
UP TO 20MHz
– CONTROLS RISE AND FALL TIMES
– FILTERED OVERLOAD DETECTION AT
APPROXIMATELY 120 mA THERMAL AND SHORT-CIRCUIT
PROTECTION ON ALL CARD CONTACTS AUTOMATIC ACTIVATION AND
DEACTIVATION SEQUENCES; INITIATED
BY SOFTWARE OR BY HARDWARE IN THE
EVENT OF A SHORT-CIRCUIT, CARD
TAKE-OFF, OVERHEATING, VDD OR VDDP
DROP-OUT ENHANCED ESD PROTECTION ON CARD
SIDE (>6 kV) 26 MHz INTEGRATED CRYSTAL
OSCILLATOR CLOCK GENERATION FOR CARDS UP TO
20 MHz (DIVIDED BY 1, 2, 4 OR 8
THROUGH CLKDIV1 AND CLKDIV2
SIGNALS) WITH SYNCHRONOUS
FREQUENCY CHANGES NON-INVERTED CONTROL OF RST VIA PIN
RSTIN ISO 7816, GSM11.11 AND EMV (PAYMENT
SYSTEMS) COMPATIBILITY SUPPLY SUPERVISOR FOR SPIKE-KILLING
DURING POWER-ON AND POWER-OFF
AND POWER-ON RESET (THRESHOLD
FIXED INTERNALLY OR EXTERNALLY BY A
RESISTOR BRIDGE) BUILT-IN DEBOUNCE ON CARD
PRESENCE CONTACTS ONE MULTIPLEXED STATUS SIGNAL OFF
DESCRIPTIONThe ST8024 is a complete low cost analog
interface for asynchronous 3V and 5V smart
cards. It can be placed between the card and the
microcontroller with few external components to
perform all supply protection and control
functions. ST8024 is a direct replacement of
ST8004.
Main applications are: smartcard readers for Set
Top Box, IC card readers for banking,
identification, Pay TV.
Table 1: Order Codes (*) Available on Request.
ST8024SMARTCARD INTERFACE
PRODUCT PREVIEWRev. 1
ST80242/23
Figure 1: Block Diagram
ST80243/23
Figure 2: Pin Configuration
Table 2: Pin Description
ST80244/23
Table 3: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Note 1: All card contacts are protected against any short with any other card contact.
Note 2: Method 3015 (HBM, 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground.
Table 4: Thermal Data
RECOMMENDED OPERATING CONDITIONS
ST80245/23
Table 5: Electrical Characteristics Over Recommended Operating Conditions (VDD = 3.3V, VDDP =
5V, f XTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C)
Table 6: Step-up Converter (VDD = 3.3V, VDDP = 5V, f XTAL = 10MHz, unless otherwise noted. Typical
values are to Ta = 25°C)
ST80246/23
Table 7: Card Supply Voltage Characteristics (VDD = 3.3V, VDDP = 5V, f XTAL = 10MHz,
unless otherwise noted. Typical values are to Ta = 25°C) (Note 1)
Table 8: Crystal Connection (PINS XTAL1 AND XTAL2) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz,unless otherwise noted. Typical values are to Ta = 25°C)
Table 9: Data Lines (PINS I/O, I/OUC, AUX1, AUX2, AUX1UC AND AUX2UC) (VDD = 3.3V, VDDP = 5V, XTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C)
ST80247/23
Table 10: Data Lines To Card Reader
(PINS I/O, AUX1 AND AUX2 With Integrated 11 kΩ PULL-UP Resistor To VCC (VDD = 3.3V, VDDP =
5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C)
Table 11: Data Lines To Microcontroller (PINS I/OUC, AUX1UC AND AUX2UC; With Integrated
11 kΩ PULL-UP Resistor To VDD) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted.Typical values are to Ta = 25°C)
ST80248/23
Table 12: Internal Oscillator (VDD = 3.3V, VDDP = 5V, f XTAL = 10MHz, unless otherwise noted.
Typical values are to Ta = 25°C)
Table 13: Reset Output To Card Reader (PIN RST) (VDD = 3.3V, VDDP = 5V, f XTAL = 10MHz, unless
otherwise noted. Typical values are to Ta = 25°C)
Table 14: Clock Output To Card Reader (PIN CLK) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C)
Table 15: Control Inputs (PINS CLKDIV1, CLKDIV2, CMDVCC, RSTIN AND 5V/3V(VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) (Note
5)
ST80249/23
Table 16: Card Presence Inputs (PINS PRES AND PRES)DD = 3.3V, VDDP = 5V, f XTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) (Note
6)
Table 17: Interrupt Output (PIN OFF NMOS Drain With Integrated 20 kΩ PULL-UP Resistor To DD ); (VDD = 3.3V, VDDP = 5V, f XTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C)
Table 18: Protection And Limitation (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C)
Table 19: Timing (VDD = 3.3V, VDDP = 5V, f XTAL = 10MHz, unless otherwise noted. Typical values
are to Ta = 25°C) Note 1: All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is specified as a
function of VDD or VCC it means their actual value at the moment of measurement.
Note 2: To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR both with
values of 100 nF and 100 nF (see Fig.10).
Note 3: Permitted capacitor values are 100 + 100 nF, or 220 nF.
Note 4: Transition time and duty factor definitions are shown in Fig.3; δ = t1/(t1+ t2).
Note 5: Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 20.
Note 6: Pin PRES is active LOW; pin PRES is active HIGH see Figs. 8 and 9; PRES has an integrated 1.25 µA current source to GND
(PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active.
ST802410/23
Figure 3: Definition of output and input transition times
FUNCTIONAL DESCRIPTIONThroughout this document it is assumed that the reader is familiar with ISO7816 terminology.
POWER SUPPLYThe supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All signals
interfacing with the system controller are referred to VDD , therefore VDD should also supply the system
controller. All card reader contacts remain inactive during power-on or power-off.
The internal circuits are maintained in the reset state until VDD reaches Vth2 +Vhys2 and for the duration of
the internal Power-on reset pulse, tW (see Fig.4). When VDD falls below Vth2, an automatic deactivation of
the contacts is performed.
A DC/DC converter is incorporated to generate the 5 or 3 V card supply voltage (VCC). The DC/DC
converter should be supplied separately by VDDP and PGND. Due to the possibility of large transient
currents, the two 100 nF capacitors of the DC/DC converter should be located as near as possible to the
IC and have an ESR less than 100 mΩ.
The DC/DC converter functions as a voltage doubler or a voltage follower according to the respective
values of VCC and VDDP (both have thresholds with a hysteresis of 100 mV).
The DC/DC converter function changes as follows:
VCC = 5 V and VDDP > 5.8 V; voltage followerCC = 5 V and VDDP < 5.7 V; voltage doubler
VCC = 3 V and VDDP > 4.1 V; voltage follower
VCC = 3 V and VDDP < 4.0 V; voltage doubler.
Supply voltages VDD and V may be applied to the IC in any sequence.
After powering the device, OFF remains LOW until CMDVCC is set HIGH.
During power off, OFF falls LOW when VDD is below the falling threshold voltage.
VOLTAGE SUPERVISOR- WITHOUT EXTERNAL DIVIDER ON PIN PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8ms (tW ) is used
internally to keep the IC inactive during power-on or power-off of the VDD supply (see Fig.4).
As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the command
lines. This state also lasts for the duration of tW after VDD has reached a level higher than Vth2 + Vhys2.
When VDD falls below Vth2 , a deactivation sequence of the contacts is performed.
ST802411/23
Figure 4: Voltage supervisor WITH AN EXTERNAL DIVIDER ON PIN PORADJ
If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Fig.1), then the following occurs:
- The internal threshold voltage Vth2 is overridden by the external voltage and by the hysteresis, therefore: th2(ext)(rise) = (1 + R1/R2) x (V bridge + V hys(ext)/2)
Vth2(ext)(fall) = (1 + R1/R2) x (Vbridge - Vhys(ext)/2)
where Vbridge = 1.18 V typ. and Vhys(ext) = 60 mV typ.
- The reset pulse width tW is doubled to approximately 16 ms.
Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed when the
voltage on pin PORADJ exceeds 1 V.
This ensures that after detection of the external bridge by the IC during power-on, the input current on pin
PORADJ does not cause inaccuracy of the bridge voltage.
The minimum threshold voltage should be higher than 2 V. The maximum threshold voltage may be up to
VDD.
APPLICATION EXAMPLES
The voltage supervisor is used as Power-on reset and as supply dropout detection during a card session.
Supply dropout detection is to ensure that a proper deactivation sequence is followed before the voltage
is too low. For the internal voltage supervisor to function, the system microcontroller should operate down
to 2.35 V to ensure a proper deactivation sequence. If this is not possible, external resistor values can be
chosen to overcome the problem.
CLOCK CIRCUITRYThe card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a crystal operating
at up to 26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be f XTAL , 1 /2 x f XTAL , 1 /4 x f XTAL or 1 /8 x f XTAL . Frequency selection is made
via inputs CLKDIV1 and CLKDIV2 (see Table 20).
ST802412/23
Table 20: Clock frequency selection; (note 1) NOTE 1: The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum between changes is
needed; the minimum duration of any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that during transition no pulse is shorter than 45% of
the smallest period, and that the first and last clock pulses about the instant of change have the correct
width.
When changing the frequency dynamically, the change is effective for only eight periods of XTAL1 after
the command. The duty factor of f XTAL depends on the signal present at pin XTAL1. In order to reach a 45
to 55% duty factor on pin CLK, the input signal on pin XTAL1 should have a duty factor of 48 to 52% and
transition times of less than 5% of the input signal period.
If a crystal is used, the duty factor on pin CLK may be 45 to 55% depending on the circuit layout and on
the crystal characteristics and frequency. In other cases, the duty factor on pin CLK is guaranteed
between 45 and 55% of the clock period.
The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used, or if the clock
pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as shown in the activation
sequences shown in Figs 5 and 6.
If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse will be applied
to the card when it is sent by the system microcontroller (after completion of the activation sequence).
I/O TRANSCEIVERSThe three data lines I/O, AUX1 and AUX2 are identical.The idle state is realized by both I/O and I/OUC
lines being pulled HIGH via a 11 kΩ resistor (I/O to VCC and I/OUC to VDD). Pin I/O is referenced to VCC,
and pin I/OUC to VDD, thus allowing operation when VCC is not equal to VDD. The first side of the
transceiver to receive a falling edge becomes the master. An anti-latch circuit disables the detection of
falling edges on the line of the other side, which then becomes a slave. After a time delay td(edge), an N
transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side. When the
master side returns to logic 1, a P transistor on the slave side is turned on during the time delay tpu and
then both sides return to their idle states. This active pull-up feature ensures fast LOW-to-HIGH
transitions; it is able to deliver more than 1 mA at an output voltage of up to 0.9 VCC into an 80 pF load.
At the end of the active pull-up pulse, the output voltage depends only on the internal pull-up resistor and
the load current. The current to and from the card I/O lines is limited internally to 15 mA and the maximum
frequency on these lines is 1 MHz.
INACTIVE MODEAfter a Power-on reset, the circuit enters the inactive mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session:
- All card contacts are inactive (approximately 200 Ω to GND)
- Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 kΩ pull-up resistor to VDD)
- Voltage generators are stopped
- XTAL oscillator is running
- Voltage supervisor is active
- The internal oscillator is running at its low frequency.
ACTIVATION SEQUENCEAfter power-on and after the internal pulse width delay, the system microcontroller can check the
presence of a card using the signals OFF and CMDVCC as shown in Table 21.
