ST7FLCD1G9M1 ,60 KBYTE FLASH 8-BIT MCU FOR LCD MONITORS WITH 2K RAM, 8-BIT ADC, TIMER, PWMS, 2 DDC, I2C, IFRfeatures also include true bit manipulation, 8x8 unsigned multiplication and indirect addressing ■ ..
ST7FLI49MK1T6 ,8-bit MCUfeatures . . . . . . 286.3 CPU registers . . . . . . 286.3.1 Accumulator (A) . . . ..
ST7FLIT15BF1B6 ,8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPIfeatures FLASH memory withmodes.byte-by-byte In-Circuit Programming (ICP) and In-Application Progra ..
ST7FLIT15BF1B6 ,8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPIST7LITE1xB8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,DATA EEPROM, ADC, 5 TIMERS, SPI■ Memories– up ..
ST7FLIT15BF1M6 ,8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPIFeatures ST7LITE10B ST7LITE15B ST7LITE19BProgram memory - bytes 2K/4KRAM (stack) - bytes 256 (128)D ..
ST7FLIT15BY0M6 ,8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPITable of Contents1 INTRODUCTION . . . . . . 42 PIN DESCRIPTION . . . . 53 REGISTER & ..
STR-F6514 , SMPS PRIMARY IC
STR-F6514 , SMPS PRIMARY IC
STR-F6523 , SMPS PRIMARY IC
STR-F6616 , SMPS PRIMARY IC
STRF6626 , OFF-LINE QUASI-RESONANT FLYBACK SWITCHING REGULATORS
STRF6626 , OFF-LINE QUASI-RESONANT FLYBACK SWITCHING REGULATORS
ST7FLCD1G9M1
60 KBYTE FLASH 8-BIT MCU FOR LCD MONITORS WITH 2K RAM, 8-BIT ADC, TIMER, PWMS, 2 DDC, I2C, IFR
ST7FLCD18-bit MCU for LCD Monitors with 60 KBytes Flash,
2 KBytes RAM, 2 DDC Ports and Infrared Controller
Key Features 60 KBytes Flash Program Memory In-Circuit Debugging and Programming In-Application Programming Data RAM: up to 2 KBytes (256 bytes stack, x 256 bytes for DDCs)8 MHz, up to 9 MHz Internal Clock Frequency True Bit Manipulation Run and Wait CPU Modes Programmable Watchdog for System
Reliability Protection against Illegal Opcode Execution 2 DDC Bus Interfaces with: DDC 2B protocol implemented in hardware Programmable DDC CI modes Enhanced DDC (EDDC) address decoding HDCP Encryption keys
Fast I²C Single Master Interface 8-bit Timer with Programmable Pre-scaler,
Auto-reload and independent Buzzer Output 8-bit Timer with External Trigger 4-channel, 8-bit Analog to Digital Converter 4 + 2 8-bit PWM Digital to Analog Outputs
with Frequency Adjustment Infrared Controller (IFR) Up to 22 I/O Lines in 28-pin Package 2 Lines Programmable as Interrupt Inputs Master Reset and Low Voltage Detector (LVD)
Reset Complete Development Support on PC-
Windows Full Software Package (Assembler, Linker,
C-compiler and Source Level Debugger)
General DescriptionThe ST7FLCD1 is a microcontroller (MCU) from the
ST7 family with dedicated peripherals for LCD
monitor applications. The ST7FLCD1 is an industry
standard 8-bit core that offers an enhanced
instruction set. The 5V supplied processor runs
with an external clock at 24 MHz (27 MHz
maximum). Under software control, the MCU mode
changes to Wait mode thus reducing power
consumption. The enhanced instruction set and
addressing modes offer real programming
potential.
In addition to standard 8-bit data management, the
MCU features also include true bit manipulation,
8x8 unsigned multiplication and indirect addressing
modes.
The device gathers the on-chip oscillator, CPU,
60-Kbyte Flash, 2-KByte RAM, I/Os, two 8-bit
timers, infrared preprocessor, 4-channel Analog-to-
Digital Converter, 2 DDCs, I²C single master,
watchdog, reset and six 8-bit PWM outputs for
analog DC control of external functions.
ST7FLCD1
Table of Contents
Chapter 1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61.1 Block Diagram .....................................................................................................................6
1.2 Abbreviations .......................................................................................................................6
1.3 Reference Documents .........................................................................................................7
1.4 Pin Description ....................................................................................................................8
1.5 External Connections .........................................................................................................10
1.6 Memory Map .....................................................................................................................11
Chapter 2 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152.1 Main Features ....................................................................................................................15
2.1.1 CPU Registers ...................................................................................................................................15
Chapter 3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223.1 Low Voltage Detector and Watchdog Reset ......................................................................22
3.2 Watchdog or Illegal Opcode Access Reset ........................................................................23
3.3 External Reset ....................................................................................................................23
3.4 Reset Procedure ................................................................................................................23
Chapter 4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244.1 Software .............................................................................................................................24
4.2 External Interrupts (ITA, ITB) .............................................................................................24
4.3 Peripheral Interrupts ...........................................................................................................24
4.4 Processing .........................................................................................................................24
4.5 Register Description ..........................................................................................................26
Chapter 5 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285.1 Introduction ........................................................................................................................28
5.2 Main Features ....................................................................................................................28
5.3 Structure .............................................................................................................................28
5.4 Program Memory Read-out Protection ..............................................................................28
5.5 In-Circuit Programming (ICP) .............................................................................................29
5.6 In-Application Programming (IAP) ......................................................................................30
5.7 Register Description ...........................................................................................................30
5.8 Flash Option Bytes .............................................................................................................31
ST7FLCD1
Chapter 6 Clocks & Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326.1 Clock System .....................................................................................................................32
6.1.1 General Description ...........................................................................................................................32
6.1.2 Crystal Oscillator Mode ......................................................................................................................32
6.1.3 External Clock Mode ..........................................................................................................................32
6.1.4 Clock Signals .....................................................................................................................................33
6.2 Power Saving Modes .........................................................................................................33
6.2.1 HALT Mode ........................................................................................................................................33
6.2.2 WAIT Mode ........................................................................................................................................33
6.2.3 Exit from HALT and WAIT Modes ......................................................................................................33
6.2.4 Selected Peripherals Mode ................................................................................................................34
Chapter 7 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357.1 Introduction ........................................................................................................................35
7.2 Common Functional Description ........................................................................................36
7.3 Port A .................................................................................................................................37
7.4 Port B .................................................................................................................................39
7.5 Port C .................................................................................................................................40
7.6 Port D .................................................................................................................................41
7.7 Register Description ...........................................................................................................42
Chapter 8 PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438.1 Introduction ........................................................................................................................43
8.2 Main Features ....................................................................................................................43
8.3 Functional Description ........................................................................................................43
8.4 Register Description ...........................................................................................................46
Chapter 9 8-bit Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .499.1 Introduction ........................................................................................................................49
9.2 Main Features ....................................................................................................................49
9.3 Functional Description ........................................................................................................49
9.4 Register Description ...........................................................................................................50
Chapter 10 I²C Single-Master Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5210.1 Introduction ........................................................................................................................52
10.2 Main Features ....................................................................................................................52
10.3 General Description ...........................................................................................................52
10.4 Functional Description (Master Mode) ...............................................................................54
10.5 Transfer Sequencing ..........................................................................................................54
ST7FLCD110.5.1 Master Receiver .................................................................................................................................54
10.5.2 Master Transmitter .............................................................................................................................54
10.6 Register Description ...........................................................................................................56
Chapter 11 Display Data Channel Interfaces (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6011.1 Introduction ........................................................................................................................60
11.2 DDC Interface Features .....................................................................................................60
11.2.1 Hardware DDC2B Interface Features ................................................................................................60
11.2.2 DDC/CI Factory Interface Features ....................................................................................................60
11.3 Signal Description ..............................................................................................................62
11.3.1 Serial Data (SDA) ..............................................................................................................................62
11.3.2 Serial Clock (SCL) .............................................................................................................................62
11.4 DDC Standard ....................................................................................................................62
11.4.1 DDC2B Interface ................................................................................................................................62
11.4.2 Mode Description ...............................................................................................................................63
11.5 DDC/CI Factory Alignment Interface ..................................................................................66
11.5.1 I²C Modes ..........................................................................................................................................66
11.6 Transfer Sequencing ..........................................................................................................68
11.7 Register Description ...........................................................................................................69
Chapter 12 Watchdog Timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7512.1 Introduction ........................................................................................................................75
12.2 Main Features ....................................................................................................................75
12.3 Main Watchdog Counter ....................................................................................................75
12.4 Lock-up Counter .................................................................................................................76
12.5 Interrupts ............................................................................................................................76
12.6 Register Description ...........................................................................................................76
Chapter 13 8-bit Timer (TIMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7713.1 Introduction ........................................................................................................................77
13.2 Main Features ....................................................................................................................77
13.3 Functional Description ........................................................................................................77
13.4 Register Description ...........................................................................................................78
Chapter 14 8-bit Timer with External Trigger (TIMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8014.1 Introduction ........................................................................................................................80
14.2 Main Features ....................................................................................................................80
14.3 Functional Description ........................................................................................................80
ST7FLCD1
Chapter 15 Infrared Preprocessor (IFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8315.1 Main Features ....................................................................................................................83
15.2 Functional Description ........................................................................................................83
15.3 Register Description ...........................................................................................................84
Chapter 16 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8516.1 Register Description ...........................................................................................................85
Chapter 17 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8717.1 Absolute Maximum Ratings ..............................................................................................87
17.2 Power Considerations ........................................................................................................87
17.3 Thermal Characteristics ....................................................................................................88
17.4 AC/DC Electrical Characteristics ........................................................................................88
17.5 Power On/Off Electrical Specifications ...............................................................................90
17.6 8-bit Analog-to-Digital Converter .......................................................................................90
17.7 I2C/DDC Bus Electrical Specifications ..............................................................................91
17.8 I2C/DDC Bus Timings .......................................................................................................91
Chapter 18 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Chapter 19 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
General Information ST7FLCD1 General Information
1.1 Block Diagram
1.2 Abbreviations
Figure 1: ST7FLCD1 Functional Diagram
ST7FLCD1 General Information
1.3 Reference DocumentsBook: ST7 MCU Family Manual
CD: MCU on CD
Many libraries, software and applications notes are available.
Ask your STMicroelectronics sales office, your local support or search the company web site at
General Information ST7FLCD1
1.4 Pin Description
Figure 2: 28-pin Small Outline Package (SO28) Pinout
Table 1: 28-pin Small Outline Package (SO28) Pin Description (Sheet 1 of 2)
ST7FLCD1 General Information This pin must be connected to a 10K pulldown resistor (refer to Section 1.5).
Table 1: 28-pin Small Outline Package (SO28) Pin Description (Sheet 2 of 2)
General Information ST7FLCD1
1.5 External ConnectionsFigure 3 shows the recommended external connections for the device.
The VPP pin is only used for programming or erasing the Flash memory array, and must be
tied to a 10 K pulldown resistor for normal operation.The 10 nF and 0.1 µF decoupling capacitors on the power supply lines are a suggested EMC
performance/cost tradeoff.
The external RC reset network (including the mandatory 1K serial resistor) is intended to protect the
device against parasitic resets, especially in noisy environments.
Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An
alternative solution is to program the unused ports as inputs with pull-up.
Figure 3: Recommended External Connections
ST7FLCD1 General Information
1.6 Memory Map Note:1. Refer to Table 2: Hardware Register Memory Map. Area FF00h to FFDFh is reserved in the event of ICD use. (For more information, refer to
Application Note 1581.) Refer to Table 3: Interrupt Vector Map.
Figure 4: Program Memory Map
Table 2: Hardware Register Memory Map (Sheet 1 of 3)
General Information ST7FLCD1
Table 2: Hardware Register Memory Map (Sheet 2 of 3)
ST7FLCD1 General Information
Table 3: Interrupt Vector Map
Table 2: Hardware Register Memory Map (Sheet 3 of 3)
General Information ST7FLCD1
Table 3: Interrupt Vector Map
ST7FLCD1 Central Processing Unit (CPU) Central Processing Unit (CPU)This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data
manipulation.
2.1 Main Features Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer8 MHz CPU internal frequency (9 MHz maximum) Wait and Halt Low Power modes Maskable hardware interrupts Non-maskable software interrupt
2.1.1 CPU RegistersThe 6 CPU registers shown in Figure 5 are not present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)The Accumulator is an 8-bit general purpose register that holds operands and results of arithmetic
and logic calculations. It also manipulates data.
Index Registers (X and Y)In indexed addressing modes, these 8-bit registers are used to create either effective addresses or
temporary storage areas for data manipulation. (The Cross-Assembler generates a previous
instruction (PRE) to indicate that next instruction refers to the Y register.)
The Y register is not affected by interrupt automatic procedures (not pushed to and popped from the
stack).
Program Counter (PC) The program counter is a 16-bit register containing the address of next instruction the CPU
executes. The program counter consists of two 8-bit registers:
PCL (Program Counter Low which is the LSB)
PCH (Program Counter High which is the MSB).
Central Processing Unit (CPU) ST7FLCD1
CONDITION CODE REGISTER (CC) Read/Write
Reset Value: 111x1XXX
The 8-bit Condition Code register contains the interrupt mask and four flags resulting from the
instruction just executed. This register can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 4 = H Half carry.This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the same instructions. No half carry has occurred. A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic
subroutines.
Note: Instruction Groups are defined in Table5.
Figure 5: CPU Registers 0
ST7FLCD1 Central Processing Unit (CPU)
Bit 3 = I Interrupt mask.This bit is set by hardware by an interrupt or by software that disables all interrupts except the TRAP
software interrupt. This bit is cleared by software. Interrupts are enabled. Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM
instructions.
Interrupts requested when the I bit is set are latched and processed when the I bit is cleared. By
default an interrupt routine is not interruptible as the I bit is set by hardware when you enter it and
reset by the IRET instruction at the end of interrupt routine. In case the I bit is cleared by software
during the interrupt routine, pending interrupts are serviced regardless of the priority level of the
current interrupt routine.
Bit 2 = N Negative.This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7th bit of the result. The last operation result is positive or null. The last operation result is negative (i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical
or data manipulation is zero. The result of the last operation is different from zero. The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow.This bit is set and cleared by hardware and software. Informs if an overflow or underflow occurred
during the last arithmetic operation. No overflow or underflow has occurred. An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It
is also affected by the “bit test and branch”, shift and rotate instructions.
STACK POINTER (SP)Read/Write
Reset Value: 01 FFh 8 0
Central Processing Unit (CPU) ST7FLCD1The Stack Pointer is a 16-bit register always pointing to the next free location in the stack. The
pointer value increments when data is taken from the stack, it decrements once data is transferred
into the stack (see Figure6).
Since the stack is 256 bytes deep, the most significant byte is forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset
value (the SP7 to SP0 bits are set) which is the stack highest address.
The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD
instruction.
Note: When the lower limit is exceeded, the Stack Pointer wraps around the stack upper limit, without
indicating a stack overflow. The previously stored information is then overwritten and therefore lost.
The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an
interrupt. You can directly manipulate the stack using PUSH and POP instructions. In case of
interrupt, the PCL is stored at the first location pointed to by the SP . Other registers are then stored
in the next locations as shown in Figure6.
When interrupt is received, the SP value decrements and the context is pushed to the stack.
On return from interrupt, the SP value increments and the context is popped from the stack.
A subroutine call and interrupt occupy two and five locations in the stack area respectively.
Figure 6: Stack Manipulation Example
Table 4: Instruction Set (Sheet 1 of 2)
ST7FLCD1 Central Processing Unit (CPU)
Table 5: Instruction Groups (Sheet 1 of 3)
Table 4: Instruction Set (Sheet 2 of 2)
Central Processing Unit (CPU) ST7FLCD1
Table 5: Instruction Groups (Sheet 2 of 3)
ST7FLCD1 Central Processing Unit (CPU)
Table 5: Instruction Groups (Sheet 3 of 3)
Reset ST7FLCD1 ResetThe Reset procedure provides an orderly software start-up or is used to exit Low Power modes.
Three reset modes are provided: Low Voltage Detector reset, Watchdog or Illegal Opcode Access reset, External Reset using the RESET pin.
At reset, the reset vector is fetched from addresses FFFEh and FFFFh and loaded into the PC (the
program is executed starting at this point).
Internal circuitry provides a 4096 CPU clock cycle delay as soon as the oscillator becomes active.
3.1 Low Voltage Detector and Watchdog ResetThe Low Voltage Detector generates a reset when: VDD is above VTRM, VDD is below V TRH when VDD is rising,VDD is below VTRL when VDD is falling (Figure7)
Note: Typical hysteresis (VTRH-VTRL) of 50 mV.
This circuitry is active only when VDD is higher than VTRM.
During the Low Voltage Detector reset, the RESET pin is held low, permitting the MCU to reset
other devices.
During a Watchdog reset, the RESET pin is pulled low permitting the MCU to reset other devices as
during a Low Voltage reset (Figure 8). The reset cycle is pulled low for 500 ns (typical).
Figure 7: Low Voltage Detector
ST7FLCD1 Reset
3.2 Watchdog or Illegal Opcode Access ResetFor more information about the Watchdog, please refer to Section 12: Watchdog Timer (WDG)
An Illegal Opcode reset occurs if the MCU attempts to execute a code that does not match a valid
ST7 instruction.
3.3 External ResetThe external reset is an active low input signal applied to the RESET pin of the MCU.
As shown in Figure 9, the RESET signal must remain low for a minimum of 1 µs.
An internal Schmitt trigger and filter provided at the RESET pin improve noise immunity.
3.4 Reset Procedure At power-up, the MCU follows the sequence described in Figure9.
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV, VTRH, VTRL and VTRM.
Figure 8: Reset Generation Diagram
Figure 9: Reset Timing Diagram
Interrupts ST7FLCD1 InterruptsThere are two different methods to interrupt the ST7: a maskable hardware interrupt as listed in Table7 a non-maskable software interrupt (TRAP).
The Interrupt Processing flowchart is shown in Figure10.
Only enabled maskable interrupts are serviced. However, disabled interrupts are latched and
processed. For an interrupt to be serviced, the PC, X, A and CC registers are saved onto the stack,
the interrupt mask (bit I of the Condition Code Register) is set to prevent additional interrupts. The
Y register is not automatically saved.
The PC is then loaded with the interrupt vector and the interrupt service routine runs (refer to
Table 7 for vector addresses) and ends with the IRET instruction. At the IRET instruction, the
contents of the registers are recovered from the stack and normal processing resumes. Note that
the I bit is then cleared if the corresponding bit stored in the stack is zero.
Though many interrupts can be run simultaneously, an order of priority is defined (see Table 7). The
RESET pin has the highest priority. If the I bit is set, only the TRAP interrupt is enabled. All
interrupts allow the processor to exit the WAIT Low Power mode.
4.1 Software The software interrupt is the executable TRAP instruction. The interrupt is recognized when the
TRAP instruction is executed, regardless of the state of the I bit. When an interrupt is recognized, it
is serviced according to flowchart described in Figure10.
Note: During ICC communication, the TRAP interrupt is reserved.
4.2 External Interrupts (ITA, ITB)The ITA (PA6), ITB (P A7) pins generate an interrupt when a falling or rising edge occurs on these
pins. These interrupts are enabled by the ITAITE and ITBITE bits (respectively) in the ITRFRE
register, provided that the I bit from the CC register is reset. Each external interrupt has its own
interrupt vector.
4.3 Peripheral Interrupts The various peripheral devices with interrupts include both Display Data Channels (DDC A and
DDC B), the Infrared Controller (IFR), two 8-bit timers (Timer A and Timer B) and the I²C interface.
Different peripheral interrupt flags fetch an interrupt if the I bit from the CC register is reset and the
corresponding Enable bit is set. If any of these conditions is not fulfilled, the interrupt is latched but
not serviced, thus remaining pending.
4.4 Processing Interrupt flags are located in the status register. The Enable bits are in the control register. When an
enabled interrupt occurs, normal processing is suspended at the end of the current instruction
execution. It is then serviced according to the flowchart shown in Figure 10.
ST7FLCD1 InterruptsThe general sequence for clearing an interrupt is an access to the status register when the flag is
set followed by a read or write of the associated register. Note that the clearing sequence resets the
internal latch. A pending interrupt (i.e. waiting to be enabled) will therefore be lost if the Clear
sequence is executed.
Figure 10: Interrupt Processing Flowchart
Interrupts ST7FLCD1
4.5 Register Description
EXTERNAL INTERRUPT REGISTER (ITRFRE)Read/Write
Reset value:00h
Bits [7:6] = Reserved. Forced by hardware to 0.
Bit 5 = ITBEDGE Interrupt B Edge Selection.This bit is set and cleared by software. Falling edge selected on ITB (default) Rising edge selected on ITB
Bit 4 = ITBLAT Falling or Rising Edge Detector Latch.This bit is set by hardware, when a falling or rising edge, depending on the sensitivity, occurs on the
ITB/PA7 pin. An interrupt is generated if ITBITE = 1. It must be cleared by software. No edge detected on ITB (default) Edge detected on ITB
Bit 3 = ITBITE ITB Interrupt Enable.This bit is set and cleared by software. ITB interrupt disabled (default) ITB interrupt enabled
Bit 2 = ITAEDGE Interrupt A Edge Selection.This bit is set and cleared by software. Falling edge selected on ITA (default) Rising edge selected on ITA
Bit 1 = ITALAT Falling or Rising Edge Detector Latch.This bit is set by hardware when a falling or a rising edge, depending on the sensitivity, occurs on
the IT A/PA6 pin. An interrupt is generated if ITAITE = 1. It must be cleared by software. No edge detected on ITA (default) Edge detected on ITA
Bit 0 = ITAITE ITA Interrupt Enable.This bit is set and cleared by software. ITA interrupt disabled (default) ITA interrupt enabled
Table 6: External Interrupt Register Map
765 432 10
ST7FLCD1 Interrupts** Many flags can cause an interrupt, see peripheral interrupt status register description.
Table 7: Interrupt Mapping
Flash Program Memory ST7FLCD1 Flash Program Memory
5.1 IntroductionThe ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a byte-by-byte
basis using an external Vpp supply.
HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-
board using In-Circuit Programming (ICP) and In-Application Programming (IAP).
The array matrix organization allows each sector to be erased and reprogrammed without affecting
other sectors.
5.2 Main Features Three Flash programming modes:
- Insertion in a programming tool. In this mode, all sectors including option bytes can be
programmed or erased.
- ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be
programmed or erased without removing the device from the application board.
- IAP (In-Application programming). In this mode, all sectors except Sector 0 can be
programmed or erased without removing the device from the application board and when the
application is running. ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Read-out protection against piracy Register Access Security System (RASS) to prevent accidental programming or erasing.
5.3 StructureThe Flash memory is organized in sectors and can be used for both code and data storage.
Depending on the overall size of the Flash memory in the microcontroller device, three user sectors
are available. Each sector is independently erasable. Thus, having to completely erase the entire
Flash memory is not necessary when only partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes (see Figure 11). They are mapped in the upper
part of the ST7 addressing space. The reset and interrupt vectors are located in Sector 0 (F000h to
FFFFh).
5.4 Program Memory Read-out ProtectionThe read-out protection is enabled through an option bit.
When this option is selected, the programs and data stored in the program memory (Flash or ROM)
are protected against read-out piracy (including a re-write protection). In Flash devices, when this
protection is removed by reprogramming the Option Byte, the entire program memory is first
automatically erased. Refer to the Section 5.8 for more details.
ST7FLCD1 Flash Program Memory
5.5 In-Circuit Programming (ICP)To perform In-Circuit Programming (ICP), the microcontroller must be switched to ICC (In-Circuit
Communication) mode by an external controller or programming tool.
Depending on the ICP code downloaded in RAM, Flash memory programming can be fully
customized (number of bytes to program, program locations or selection of serial communication
interface for downloading).
When using a STMicroelectronics or third-party programming tool that supports ICP and the
specific microcontroller device, the user only needs to implement the ICP hardware interface on the
application board (see Figure 12). For more details on the pin locations, refer to the device pin
description.
ICP needs between 4 and 6 pins to be connected to the programming tool. Depending on the
desired type of programming, these pins are: RESET: device reset VSS: device power supply ground ICC_CLK: ICC output serial clock pin ICC_DATA: ICC input serial data pin VPP: programming voltage VDD: application board power supply
CAUTION: If the ICC_CLK or ICC_DATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the programming tool is plugged to the board, even if an ICC
session is not in progress, the ICC_CLK and ICC_DATA pins are not available for the
application. If they are used as inputs by the application, an isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values. During the ICC session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than mA at high level (push-pull output or pull-up resistor (< 1 kΩ)). A Schottky diode can be used
to isolate the application RESET circuit in this case. When using a classical RC network with a
resistor (> 1kΩ) or a reset management IC with open-drain output and pull-up resistor
Figure 11: Memory Map and Sector Address
Flash Program Memory ST7FLCD11 kΩ), no additional components are needed. In any case, the user must ensure that an
external reset is not generated by the application during the ICC session. The use of Pin 7 of the ICC connector depends on the Programming T ool architecture. This pin
must be connected when using most ST programming tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
5.6 In-Application Programming (IAP)This mode uses a Boot Loader program previously stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully-controlled by user software. This allows it to be adapted to the user application,
(user-defined strategy for entering programming mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is possible to download code from either DDC
interface and program it in the Flash memory. IAP mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during
the programming operation.
5.7 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)Read/Write
Reset Value: 0000 0000 (00h)
Figure 12: Typical ICP Interface
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ST7FLCD1 Flash Program MemoryThis register is reserved for use by Programming Tool software. It controls the Flash programming
and erasing operations.
For details on customizing Flash programming methods and In-Circuit T esting, refer to the ST7
Flash Programming Reference Manual and relevant Application Notes.
5.8 Flash Option BytesEach device is available for production in user programmable versions (Flash) as well as in factory
coded versions (ROM). Flash devices are shipped to customers with a default content (FFh), while
ROM factory coded parts contain the code supplied by the customer. This implies that Flash
devices have to be configured by the customer using the Option Bytes while the ROM devices are
factory-configured.
The option bytes are used to select the hardware configuration of the microcontroller. They have no
address in the memory map and can be accessed only in programming mode (for example, using a
standard ST7 programming tool). The default content of the Flash is fixed to FFh. T o program
directly the Flash devices using ICP , Flash devices are shipped to customers with the internal RC
clock source enabled. In masked ROM devices, the option bytes are fixed in hardware by the ROM
code.
Static Option Byte 1OPT0 = FMP_R Flash memory read-out protection
This option indicates if the user Flash memory is protected against read-out piracy. This protection
is based on a read and write protection of the memory in Test and ICP modes. Erasing the option
bytes when the FMP_R option is selected causes the entire user memory to be erased first. Read-out protection enabled Read-out protection disabled
Static Option Byte 2
76543210
Clocks & Low Power Modes ST7FLCD1 Clocks & Low Power Modes
6.1 Clock System
6.1.1 General DescriptionThe device requires a certain number of clock signals in order to operate. All clock signals are
derived from the root clock signal CkXT provided at the output of the "OSC" circuit (refer to
Figure 13). If a crystal oscillator or ceramic resonator is applied on pins OSCIN and OSCOUT, the
OSC operates in a crystal-controlled oscillator mode. An external clock signal can also be applied
on the OSCIN pin, putting the OSC in external clock mode operation.
The block diagram in Figure 13 shows the basic configuration of the clock system.
6.1.2 Crystal Oscillator Mode In this mode, the root clock is generated by the on-chip oscillator controlled by an external parallel
fundamental-mode crystal oscillator or a ceramic resonator. General design precautions must be
followed to ensure maximum stability. Foot capacitors CL1 and CL2 must be adapted to match the
crystal oscillator or ceramic resonator. A 100-kΩ resistor is internally connected between pins
OSCIN and OSCOUT.
Note: If a Murata ceramic resonator is to be used, Murata recommends their CERALOCK® CSTCG-
series (fundamental type) with built-in CL1 and CL2 capacitors, such as:
- CSTCG24M0V51-R0 for 24-MHz external, 8-MHz internal clock operation
- CSTCG27M0V51-R0 for 27-MHz external, 9-MHz internal clock operation
No additional external capacitor is therefore needed with either model of this series.
6.1.3 External Clock Mode In this mode, an external clock is provided on pin OSCIN, while pin OSCOUT is left open. The
signal is internally buffered before feeding the subsequent stages. There is the same emphasis on
stability of the external clock as in Crystal Oscillator mode.
Figure 13: Main Clock Generation
ST7FLCD1 Clocks & Low Power Modes
6.1.4 Clock SignalsThe root clock is divided by a factor of 3 to obtain the CPU clock (fCPU).
6.2 Power Saving ModesThe MCU offers the possibility to decrease power consumption at any time by software operation.
6.2.1 HALT ModeHALT mode is the MCU lowest power consumption mode. Also, HALT mode also stops the
oscillator stage completely which is the most critical condition (the MCU cannot recover by itself).
For this reason, HALT mode is not compatible with the watchdog protection.
6.2.2 WAIT ModeThis is a low power consumption mode. The WFI instruction sets the MCU in WAIT mode. The
internal clock remains active but all CPU processing is stopped. However, all other peripherals still
run.
Note: In WAIT mode, DMA (DDC A and DDC B) accesses are possible.
6.2.3 Exit from HALT and WAIT ModesThe MCU can exit HALT mode upon reception of an external interrupt on pins IT A or ITB. The
oscillator is then turned back on and a stabilizing time is necessary before releasing CPU operation
(4096 CPU clock cycles). After this delay, the CPU continues operation according to the cause of its
release, either by servicing an interrupt or by fetching the reset vector in case of reset.
During WAIT mode, the I bit from the Condition Code register is cleared, enabling all interrupts. This
leads the MCU to exit WAIT mode, the corresponding interrupt vector tois fetched, the interrupt
routine is executed and normal processing resumes.
A reset causes the program counter to fetch the reset vector. Processing starts as with a normal
reset.
Figure 14: Clock System Diagram
Table 8: Watchdog Compatibility
Clocks & Low Power Modes ST7FLCD1
6.2.4 Selected Peripherals ModeCertain peripherals have an “On/Off “bit to disconnect the block (or part of it) and decrease MCU
power consumption.
Figure 15: WAIT Flow Chart
Table 9: Peripheral Modes
ST7FLCD1 I/O Ports I/O Ports
7.1 Introduction I/O ports are used to transfer data through digital inputs and outputs. For specific pins, I/O ports
allow the input of analog signals or the Input/Output of alternate signals for on-chip peripherals
(DDC, Timer, etc.).
Each pin can be independently programmed as digital input or output. Each pin can be an analog
input when an analog switch is connected to the Analog-to-Digital Converter (ADC).
Note:1. This is a typical I/O pin configuration. Each port is customized with a specific configuration in order
to handle certain functions.
Figure 16: I/O Pin Critical Circuit
I/O Ports ST7FLCD1
7.2 Common Functional DescriptionEach port pin of the I/O Ports can be individually configured as either an input or an output, under
software control.
Each bit of Data Direction Register (DDR) corresponds to an I/O pin of the associated port. This
corresponding bit must be set to configure its associated pin as an output and must be cleared to
configure its associated pin as an input (see Note1onpage35). The Data Direction Registers can
be read and written.
A typical I/O circuit is shown in Figure 16. Any write to an I/O port updates the port data register
even when configured as an input. Any read of an I/O port returns either the data latched in the port
data register (pins configured as output) or the value of the I/O pins (pins configured as an input).
Remark: When there is no I/O pin inside an I/O port, the returned value is logic 0 (pin configured as an input).
At reset, all DDR registers are cleared, configuring all I/O ports as inputs. Data Registers (DR) are
also cleared at reset.
Input modeWhen DDR = 0, the corresponding I/O is configured in Input mode.
In this case, the output buffer is switched off and the state of the I/O is readable through the Data
Register address, coming directly from the TTL Schmitt Trigger output and not from the Data
Register output.
Output modeWhen DDR = 1, the corresponding I/O is configured in Output mode.
In this case, the output buffer is activated according to the Data Register content.
A read operation is directly performed from the Data Register output.
Analog inputEach I/O can be used as an analog input by adding an analog switch driven by the ADC. The I/O
must be configured as an input before using it as analog input.
When the analog channel is selected by the ADC, the analog value is directly driven to the ADC
through an analog switch.
Alternate modeA signal coming from an on-chip peripheral is output on the I/O which is then automatically
configured in output mode.
The signal coming from the peripheral enables the alternate signal to be output. A signal coming
from an I/O can be input to an on-chip peripheral.
Table 10: I/O Pin Function
ST7FLCD1 I/O PortsAn alternate Input must first be configured in Input mode (DDR = 0). Alternate and I/O Input
configurations are identical without pull-up. The signal to be input in the peripheral is taken after the
TTL Schmitt trigger when available.
The I/O state is readable as in Input mode by addressing the corresponding I/O Data Register.
7.3 Port AEach Port A bit can be defined as an Input line or as a Push-Pull. It can be also be used to output
the PWM outputs.
Outputs PA4 and PA5 may also be configured as high current (8 mA) push-pull outputs by means of
the MISCR register.
MISCELLANEOUS REGISTER (MISCR)Read/Write
Reset value:00h
Bits [7:3] = Reserved. Forced by hardware to 0.
Bit 2 = PA5OVD Port A Bit 5 Overdrive This bit is set and cleared by software. It is used only if Port A Bit 5 is set as an output (PADDR,
PWM5 or BUZOUT). It has no effect if set as an input. 2 mA Push-pull Output 8 mA Push-pull Output
Table 11: Port A Description Reset state. If both PWM5 and BUZOUT are enabled, BUZOUT has priority over PWM5.
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I/O Ports ST7FLCD1
Bit 1 = PA4OVD Port A Bit 4 Overdrive This bit is set and cleared by software. It is used only if Port A Bit 4 is set as an output (PADDR or
PWM4). It has no effect if set as an input. 2 mA Push-pull Output 8 mA Push-pull Output
Bit 0 = Reserved. Must be cleared by software.
Figure 17: Port A [5:0]
Figure 18: Port A [7:6]
ST7FLCD1 I/O Ports
7.4 Port BEach Port B bit can be used as the Analog source to the Analog-to-Digital Converter.
Only one I/O line at a time must be configured as an analog input. Pins levels are all limited to 5V.
All unused I/O lines should be tied to an appropriate logic level (either VDD or VSS).
Since ADC and microprocessor are on the same chip and if high precision is required, the user
should not switch heavily loaded signals during conversion. Such switching will affect the supply
voltages used as analog references. The conversion accuracy depends on the quality of power
supplies (VDD and VSS). The user must take special care to ensure that a well regulated reference
voltage is present on pins VDD and VSS (power supply variations must be less than 3.3 V/ms). This
implies, in particular, that a suitable decoupling capacitor is used at pin VDD.
Table 12: Port B Description Reset state.
Figure 19: Port B [2:0]
I/O Ports ST7FLCD1
7.5 Port CThe available port pins of port C may be used as general purpose I/Os.
For more information, refer to the relevant Application Notes.
Note: These 2 pins are reserved for ICC use during ICC communication. If ICC is not used at all, they can
be used as general purpose I/Os.
Figure 20: Port B [3]
Table 13: Port C Description Reset state.
ST7FLCD1 I/O Ports
7.6 Port DThe alternate functions are: the I/O pins of the on-chip I²C SCLI & SDAI for PD[1:0], the I/O pins of the on-chip DDC A SCLD & SDAD for PD[3:2], the I/O pins of the on-chip DDC B SCLD & SDAD for PD[5:4] input and output on PD[7:6].
Figure 21: Port C
Table 14: Port D Description Reset state.
I/O Ports ST7FLCD1
7.7 Register Description
DATA REGISTERS (PXDR)
DATA DIRECTION REGISTERS (PXDDR)(‘x’ corresponds to the I/O pin of the associated port. In Input mode, the value is 00h by default).I
Figure 22: Port D
Table 15: I/O Port Register Map
ST7FLCD1 PWM Generator
8PWM Generator
8.1 IntroductionThis PWM on-chip peripheral consists of two blocks, each one with its own 8-bit auto-reload
counter.
The first block (Block A) outputs up to 4 separate PWM signals at the same frequency. The second
block (Block B) outputs up to 2 separate PWM signals at another frequency.
Each PWM output may be enabled or disabled independently of the other. The polarity of each
PWM output may also be independently set.
8.2 Main Features 2 distinct programmable frequencies between 31.250 kHz and 8 MHz. Resolution: tCPU
8.3 Functional DescriptionThe free-running 8-bit counter is fed by the CPU clock and increments on every rising edge of the
clock signal.
When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARR
register.
Each PWMx output signal can be enabled independently using the corresponding OEx bit in the
PWM control register (PWMCR). When this bit is set, the corresponding I/O is configured as an
output push-pull alternate function.
PWM[3:0] all have the same frequency which is controlled by counter period A and the ARRA
register value. PWMA = f COUNTERA / (256-ARRA)
PWM[5:4] all have the same frequency which is controlled by counter period B and the ARRB
register value. PWMB = f COUNTERB / (256-ARRB)
When a counter overflow occurs, the PWMx pin level is toggled depending on the corresponding
OPx (output polarity) bit in the PWMCR register. When the counter reaches the value contained in
one of the Duty Cycle registers (DCRIx), the corresponding PWMx pin level is restored.
This DCRIx register can not be accessed directly, it is loaded from the Duty Cycle register (DCRx)
at each overflow of the counter. This double buffering method prevents glitch generation when
changing the duty cycle on the fly.
Note that the reload values will also affect the value and the resolution of the duty cycle of the PWM
output signal. To obtain a signal on a PWMx pin, the contents of the DCRx register must be greater
than or equal to the contents of the ARR register. The maximum available resolution for duty cycle
is 1/(256-ARR).
PWM Generator ST7FLCD1
Figure 23: PWM Block Diagram
Figure 24: PWM Generation
Figure 25: PWM Generation
ST7FLCD1 PWM GeneratorEquations:
This Pulse Width modulated signal must be filtered, using an external RC network placed as close
as possible to the associated pin. This provides an analog voltage proportional to the average
charge through the external capacitor. Thus for a higher mark/space ratio (High time much greater
than Low time) the average output voltage is higher. The external components of the RC network
should be selected for the filtering level required for control of the system variable.
With:
REXT = 1 kΩ
fPWM = fCPU / (256 - ARR)
fCPU = 8 MHz
VDD = 5V
Worst case, PWM Duty Cycle 50%
Table 16: Pulse WIdth in tCPU
Table 17: 8-bit PWM Ripple after FilteringDuty Cycle = DCR + 1
256 - ARR
VRIPPLE = (1 - e 1/(2 x CEXT x REXT x fPWM))2
|1 - e 1/(CEXT x REXT x fPWM)|
x VDD
PWM Generator ST7FLCD1
8.4 Register DescriptionEach PWM is associated with two control bits (OEx and OPx) and a control register (DCRx).
Figure 26: PWM Simplified Voltage Output after Filtering
Table 18: PWM Register Map
ST7FLCD1 PWM Generator
DUTY CYCLE REGISTERS (PWMDCRx)Read/Write
Reset Value 0000 0000 (00h)
Bits [7:0] = DC[7:0] Duty Cycle DataThese bits are set and cleared by software.
A DCRx register is associated with the DCRix register of each PWM channel to determine the
second edge location of the PWM signal (the first edge location is common to all 4 channels and
given by the ARR register). These DCR registers allow the duty cycle to be set independently for
each PWM channel.
CONTROL REGISTER A (PWMCRA)Read/Write
Reset Value: 0000 0000 (00h)
Bits [7:4] = OE [3:0] PWM Output Enable. These bits are set and cleared by software. They enable or disable the PWM output channels
independently acting on the corresponding I/O pin. the PWM pin is a general I/O. the PWM pin is driven by the PWM peripheral.
Bits [3:0] = OP[3:0] PWM Output Polarity. These bits are set and cleared by software. They independently select the polarity of the 4 PWM
output signals. positive polarity. negative polarity.
Note: When an OPx bit is modified, the PWMx output signal is immediately updated.
AUTO-RELOAD REGISTER A (PWMARRA)Read/Write
Reset Value: 1111 1111(FFh)
Bits [7:0] = AR[7:0] Counter Auto-Reload Data. These bits are set and cleared by software. They are used to hold the auto-reload value which is
automatically loaded in the counter when an overflow occurs. Writing in this register reload the
PWM counter to ARR A value. At the same time, the PWM output levels are changed according to
the corresponding OPx bit in the PWMCR register.
765 432 10
765 432 10
765 432 10
PWM Generator ST7FLCD1This register adjusts the PWM frequency (setting the PWM duty cycle resolution) for outputs
PWM[3:0].
CONTROL REGISTER B (PWMCRB)Read/Write
Reset Value: 0000 0000 (00h)
Bits [7:6] = Reserved. Forced by hardware to 0.
Bits [5:4] = OE[5:4] PWM Output Enable. These bits are set and cleared by software. They enable or disable the PWM output channels
independently acting on the corresponding I/O pin. the PWM pin is a general I/O. the PWM pin is driven by the PWM peripheral.
Bits [3:2] = Reserved. Forced by hardware to 0.
Bit [1:0] = OP[5:4] PWM Output Polarity. These bits are set and cleared by software. They independently select the polarity of the 4 PWM
output signals. positive polarity. negative polarity.
Note: When an OPx bit is modified, the PWMx output signal is immediately reversed.
AUTO-RELOAD REGISTER B (PWMARRB)Read/Write
Reset Value: 1111 1111 (FFh)
Bits [7:0] = AR [7:0] Counter Auto-Reload Data. These bits are set and cleared by software. They are used to hold the auto-reload value which is
automatically loaded in the counter when an overflow occurs. Writing in this register reload the
PWM counter to ARR B value. At the same time, the PWM output levels are changed according to
the corresponding OPx bit in the PWMCR register.
This register adjusts the PWM frequency (by setting the PWM duty cycle resolution) for outputs
PWM[5:4].
765 432 10
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