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ST7538Q
B-FSK
July 2006 Rev 1 1/44
ST7538QFSK power line transceiver
General features Half duplex frequency shift keying (FSK)
transceiver Integrated power line driver with programmable
voltage and current control Programmable interface: Synchronous Asynchronous Single supply voltage (from 7.5 up to 12.5V) Very low power consumption (Iq = 5mA) Integrated 5V voltage regulator (up to 50mA)
with short circuit protection Integrated 3.3V voltage regulator (up to 50mA)
with short circuit protection 3.3V or 5V digital supply 8 programmable transmission frequencies Programmable baud rate up to 4800BPS Receiving sensitivity up to 250µVrms Suitable to application in accordance with EN
50065 CENELEC specifications Carrier or preamble detection Band in use detection Programmable 24 or 48 bit register with
security checksum Mains zero crossing detection and
synchronization Watchdog timer Output voltage freeze 8 or 16 bit header recognition UART/SPI host interface ST7537 compatible
DescriptionThe ST7538Q is a Half Duplex
synchronous/asynchronous FSK Modem
designed for power line communication network
applications. It operates from a single supply
voltage and integrates a line driver and two linear
regulators for 5V and 3.3V. The device operation
is controlled by means of an internal register,
programmable through the synchronous serial
interface. Additional functions as watchdog, clock
output, output voltage and current control,
preamble detection, time-out, band in use are
included. Realized in Multipower BCD5
technology that allows to integrate DMOS, Bipolar
and CMOS structures in the same chip.
Order codes
Contents ST7538Q2/44
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155.1 Carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 ST7538Q mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 Host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.1 Communication between host and ST7538Q . . . . . . . . . . . . . . . . . . . . 20
5.6 Control register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7 Receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.1 High sensitivity mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.2 Synchronization recovery system (PLL) . . . . . . . . . . . . . . . . . . . . . . . . 23
5.7.3 Carrier/preamble detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.7.4 Header recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.8 T ransmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8.1 Automatic Level Control (ALC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.9 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.10 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.11 Detection method and Rx Sensitivity in UART mode . . . . . . . . . . . . . . . . 35
ST7538Q Contents 3/44
Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 366.1 Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3 Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4 Zero crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5 Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6 Output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.7 Extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.8 Reg OK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.9 Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.11 5V and 3.3V voltage regulators and power good function . . . . . . . . . . . . 39
6.12 Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Block diagram ST7538Q
4/44
1 Block diagram
Figure 1. Block diagram
ST7538Q Pin settings
5/44
2 Pin settings
2.1 Pin connection
Figure 2. Pin Connection (Top view)
Pin settings ST7538Q
6/44
2.2 Pin description
Table 1. Pin description
ST7538Q Pin settings
7/44 If not used this pin must be connected to VDC Cannot be left floating Cannot be left floating If not used this pin must be connected to VDC If not used this pin must be tied low (SGND or PAVss or DVss)
Table 1. Pin description (continued)
Electrical data ST7538Q
8/44
3 Electrical data
3.1 Maximum ratings
Table 2. Absolute maximum ratings This current is intended as not repetitive pulse current
ST7538Q Electrical characteristics
9/44
3.2 Thermal data
4 Electrical characteristics
Table 3. Thermal data Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB It's the same condition of the point above, without any heatsinking surface on the board.
Table 4. Electrical characteristics
(AVdd = DVdd = +5V, P AVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ TA ≤ 85°C, TJ < 125 °C, fc = 86kHz,
other control register parameters as default value, unless otherwise specified)
Electrical characteristics ST7538Q
10/44
Table 4. Electrical characteristics (continued)
(AVdd = DVdd = +5V, P AVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ TA ≤ 85°C, TJ < 125 °C, fc = 86kHz,
other control register parameters as default value, unless otherwise specified)
ST7538Q Electrical characteristics
11/44
Table 4. Electrical characteristics (continued)
(AVdd = DVdd = +5V, P AVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ TA ≤ 85°C, TJ < 125 °C, fc = 86kHz,
other control register parameters as default value, unless otherwise specified)
Electrical characteristics ST7538Q
12/44
Table 4. Electrical characteristics (continued)
(AVdd = DVdd = +5V, P AVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ TA ≤ 85°C, TJ < 125 °C, fc = 86kHz,
other control register parameters as default value, unless otherwise specified)
ST7538Q Electrical characteristics
13/44
Table 4. Electrical characteristics (continued)
(AVdd = DVdd = +5V, P AVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ TA ≤ 85°C, TJ < 125 °C, fc = 86kHz,
other control register parameters as default value, unless otherwise specified)
Electrical characteristics ST7538Q
14/44
Table 4. Electrical characteristics (continued)
(AVdd = DVdd = +5V, P AVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ TA ≤ 85°C, TJ < 125 °C, fc = 86kHz,
other control register parameters as default value, unless otherwise specified)
ST7538Q Functional description
15/44
5 Functional description
5.1 Carrier frequencies
ST7538Q is a multi frequency device: eight programmable Carrier Frequencies are available
(see Table5).
Only one Carrier could be used a time. The communication channel could be varied during
the normal working Mode to realize a multifrequency communication.
Selecting the desired frequency in the Control Register the Transmission and Reception
filters are accordingly tuned.
5.2 Baud rates
ST7538Q is a multi Baud rate device: four Baud Rate are available (See T able 6.).
Table 5. ST7538Q Channels List
Table 6. ST7538Q mark and space tones frequency distance vs baud rate and deviation Frequency deviation. Deviation = ∆F / (Baud Rate) Deviation 0.5 Not Allowed Default value
Functional description ST7538Q
16/44
5.3 Mark and space frequencies
Mark and space communication frequencies are defined by the following formula:
F ("0") = FCarrier + [∆F]/2
F ("1") = FCarrier - [∆F]/2
∆F is the Frequency Deviation.
With Deviation = “0.5” the difference in terms of frequency between the mark and space
tones is half the Baudrate value (∆F = 0.5*BAudrate). When the Deviation = “1” the
difference is the Baudrate itself (∆F = Baudrate). The minimal Frequency Deviation is
600Hz.
Table 7. ST7538Q synthesized frequencies
ST7538Q Functional description
17/44
5.4 ST7538Q mains access
ST7538Q can access the Mains in two different ways: Synchronous access Asynchronous access
The choice between the two types of access can be performed by means of Control
Register bit 14 (see Table 11) and affects the ST7538Q data flow in Transmission Mode as
in Reception Mode (for how to set the communication Mode, see Section 5.5 on page 18).
In Data Transmission Mode: Synchronous Mains access: on clock signal provided by ST7538Q (CLR/T line)
rising edge, data transmission line (TxD line) value is read and sent to the FSK
Modulator. ST7538Q manages the T ransmission timing according to the
BaudRate Selected. Asynchronous Mains access: data transmission line (TxD line) value enters
directly to the FSK Modulator. The Host Controller manages the Transmission
timing (CLR/T line should be neglected).
Table 7. ST7538Q synthesized frequencies
Functional description ST7538Q
18/44
In Data Reception Mode: Synchronous Mains access: on clock signal recovered by a PLL from ST7538Q
(CLR/T line) rising edge, value on FSK Demodulator is read and put to the data
reception line (RxD line). ST7538Q recovers the bit timing according to the
BaudRate Selected. Asynchronous Mains access: Value on FSK Demodulator is sent directly to the
data reception line (RxD line). The Host Controller recovers the communication
timing (CLR/T line should be neglected).
5.5 Host processor interface
ST7538Q exchanges data with the host processor through a serial interface.
The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged
using RxD, TxD and CLR/T lines.
Four are the ST7538Q working modes: Data Reception Data T ransmission Control Register Read Control Register Write
REG_DATA and RxTx lines are level sensitive inputs.
ST7538Q features two type of Host Communication Interfaces:
–SPI
–UART
The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to “0” SPI
interface is selected while if UART/SPI pin is forced to “1” UART interface is selected (a) . The
type of interface affects the Data Reception by setting the idle state of RxD line. When
ST7538Q is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available
on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the
RxD line is forced to “0” when UART/SPI pin is forced to ”0” or to “1” when UART/SPI pin is
forced to ”1”.
Table 8. Data and control register access bits configuration UART Interface Mode modifies also Control Register Functions and provides one more level of Rx sensitivity
(see par. 5.11)
ST7538Q Functional description
19/44
The UART interface allows to connect an UART compatible device instead SPI interface
allows to connect an SPI compatible device. The allowed combinations of Host
Interface/ST7538Q Mains Access are:
Figure 3. Synchronous and asynchronous ST7538Q/Host controller interfaces
ST7538Q allows to interface the Host Controller using a five line interface (RxD,TxD,RxTx,
CLR/T, & REG_DATA) in case of Synchronous mains access or using a 3 line interface
(RxD,TxD & RxTx) in Asynchronous mains access. Since Control Register is not accessible
in Asynchronous mode, in this case REG_DATA pin can be tied to GND.
Table 9. Host Interface / ST7538Q mains access combinations Received Data more stable than in Asynchronous Mains Access
Functional description ST7538Q
20/44
5.5.1 Communication between host and ST7538Q
The Host can achieve the Mains access by selecting REG_DATA = ”0” and the choice
between Data Transmission or Data Reception is performed by selecting RxTx line
(if RxTx =“1” ST7538Q receives data from mains, if RxTx = ”0” ST7538Q transmits data over
the mains).
Communication between Host and ST7538Q is different in Asynchronous and Synchronous
mode: Asynchronous mode
In Asynchronous Mode, data are exchanged without any data Clock reference. The
host controller has to recover the clock reference in receiving Mode and control the Bit
time in transmission mode.
If RxTx line is set to “1” & REG_DAT A = ”0” (Data Reception), ST7538Q enters in an
Idle State. After Tcc time the modem starts providing received data on RxD line.
If RxTx line is set to “0” & REG_DAT A=”0” (Data Transmission), ST7538Q enters in an
Idle State and transmission circuitry is switched on. After Tcc time the modem starts
transmitting data present on TxD line. Synchronous mode
In Synchronous Mode ST7538Q is always the master of the communication and
provides the clock reference on CLR/T line.
When ST7538Q is in receiving mode an internal PLL recovers the clock reference.
Data on RxD line are stable on CLR/T rising Edge.
When ST7538Q is in transmitting mode the clock reference is internally generated and
TxD line is sampled on CLR/T rising Edge.
If RxTx line is set to “1” & REG_DAT A=”0” (Data Reception), ST7538Q enters in an Idle
State and CLR/T line is forced Low. After Tcc time the modem starts providing received
data on RxD line.
If RxTx line is set to “0” & REG_DAT A=”0” (Data Transmission), ST7538Q enters in an
Idle State and transmission circuitry is switched on. After Tcc time the modem starts
transmitting data present on TxD line (Figure5) .
Figure 4. Receiving and transmitting data/recovered clock timing
ST7538Q Functional description
21/44
Figure 5. Data reception -> data transmission -> data reception
5.6 Control register access
The communication with ST7538Q Control Register is always synchronous. The access is
achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus
REG_DATA Line.
With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control
Register MSB first. The ST7538Q samples the TxD line on CLR/T rising edges. The control
Register content is updated at the end of the register access section (REG_DATA falling
edge).
In Normal Control Register mode (Control Register bit 21=”0”, see Table 11) if more than 24
bits are transferred to ST7538Q only latest 24 bits are stored inside the Control Register. If
less than 24 bits are transferred to ST7538Q the Control Register writing is aborted (in this
case if at least 16 bits are provided REGOK line will be activated).
In order to avoid undesired Control Register writings caused by REG_DATA line fluctuations
(for example because of surge or burst on mains), in Extended Control Register mode
(Control Register bit 21=”1” see Table 11) exactly 24 or 48 bits must be transferred to
ST7538Q in order to properly write the Control Register, otherwise writing is aborted and if
at least 16 bits are provided REGOK line will be activated. If 24 bits are transferred, only the
first 24 Control Register bits (from 23 to 0) are written.
With REG_DATA = 1 and RxTx = 1, the content of the Control Register is sent on RxD port.
The Data on RxD are stable on CLR/T rising edges MSB First. In Normal Control Register
mode 24 bits are transferred from ST7538Q to the Host. In Extended Control Register mode
24 or 48 bits are transferred from ST7538Q to the Host depending on content of Control
Register bit 18 (with bit 18 = ”0” the first 24 bits are transferred, otherwise all 48 bits are
transferred, see Table 11).
Functional description ST7538Q
22/44
Figure 6. Data reception -> control register read -> data reception timing diagram
Figure 7. Data reception -> control register write -> data reception timing diagram
Figure 8. Data transmission -> control reg. read data -> reception timing diagram
Figure 9. Data transmission -> control reg. write -> data reception timing diagram
