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ST7538P
POWER LINE FSK TRANSCEIVER
1/30
ST7538February 2003 HALF DUPLEX FREQUENCY SHIFT KEYING
(FSK) TRANSCEIVER INTEGRATED POWER LINE DRIVER WITH
PROGRAMMABLE VOLTAGE AND CURRENT
CONTROL PROGRAMMABLE INTERFACE:
– SYNCHRONOUS
– ASYNCHRONOUS SINGLE SUPPLY VOLTAGE (FROM 7.5 UP TO 12.5V) VERY LOW POWER CONSUMPTION (Iq=5 mA) INTEGRATED 5V VOLTAGE REGULATOR
(UP TO 100mA) WITH SHORT CIRCUIT
PROTECTION 8 PROGRAMMABLE TRANSMISSION
FREQUENCIES PROGRAMMABLE BAUD RATE UP TO 4800BPS RECEIVING SENSITIVITY 1 mVRMS SUITABLE TO APPLICATION IN ACCORDANCE
WITH EN 50065 CENELEC SPECIFICATIONS CARRIER OR PREAMBLE DETECTION BAND IN USE DETECTION PROGRAMMABLE REGISTER WITH
SECURITY CHECKSUM MAINS ZERO CROSSING DETECTION AND
SYNCHRONIZATION WATCHDOG TIMER
DESCRIPTIONThe ST7538 is a Half Duplex synchronous/asyn-
chronous FSK Modem designed for power line
communication network applications. It operates
from a single supply voltage and integrates a line
driver and a 5V linear regulator. The device oper-
ation is controlled by means of an internal register,
programmable through the synchronous serial in-
terface. Additional functions as watchdog, clock
output, output voltage and current control, pream-
ble detection, time-out, band in use are included.
Realized in Multipower BCDV technology that al-
lows to integrate DMOS, Bipolar and CMOS struc-
tures in the same chip.
POWER LINE FSK TRANSCEIVER
BLOCK DIAGRAM
ST7538 2/30
PIN CONNECTION (Top view)
PIN DESCRIPTION
3/30
ST7538<1> If not used this pin must be connected to VDC
<2> Cannot be left floating
<3> Cannot be left floating
<4> If not used this pin must be connected to VDC
<5> If not used this pin must be tied low (SGND or PAVss or DVss)
PIN DESCRIPTION (continued)
ST7538 4/30
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA(*) Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB
(**) It's the same condition of the point above, without any heatsinking surface on the board.
5/30
ST7538
ELECTRICAL CHARACTERISTCS (AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified)
ST7538 6/30
ELECTRICAL CHARACTERISTCS (continued)(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified)
7/30
ST7538
ELECTRICAL CHARACTERISTCS (continued)(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified)
ST7538 8/30
ELECTRICAL CHARACTERISTCS (continued)(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, unless otherwise specified)
9/30
ST7538
FUNCTIONAL DESCRIPTION
Carrier FrequenciesST7538 is a multi frequency device: eight programmable Carrier Frequencies are available (see table 1).
Only one Carrier could be used a time. The communication channel could be varied during the normal
working Mode to realize a multifrequency communication.
Selecting the desired frequency in the Control Register the Transmission and Reception filters are accord-
ingly tuned.
Table 1.
Baud RatesST7538 is a multi Baud rate device: four Baud Rate are available (See table 2).
Table 2. Note:1. Default value Frequency deviation. Deviation = ΔF / (Baud Rate) Deviation 0.5 Not Allowed
ST7538 10/30
Mark and Space FrequenciesMark and Space Communication Frequencies are defined by the following formula:
F ("0") = FCarrier + [ΔF]/2
F ("1") = FCarrier - [ΔF]/2
ΔF is the Frequency Deviation.
With Deviation = “0.5” the difference in terms of frequency between the mark and space tones is half the
Baudrate value (ΔF=0.5*BAudrate). When the Deviation = “1” the difference is the Baudrate itself (ΔF=
Baudrate). The minimal Frequency Deviation is 600Hz.
Table 3.
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ST7538
Host Processor InterfaceST7538 exchanges data with the host processor thorough a serial interface.
The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged using RxD, TxD
and CLR/T lines.
Four are the ST7538 working modes: Data Reception Data Transmission Control Register Read Control Register Write
REG_DATA and RxTx lines are level sensitive inputs.
Table 4. Mains AccessST7538 features two type of communication interfaces:
- Asynchronous
- Synchronous
The selection can be done through the internal Control Register.
Figure 1. Asynchronous Mode.ST7538 allows to interface the Host Controller using a 3 line interface (RXD,TXD & RxTx).
Data are exchange without any auxiliary Clock reference in an Asynchronous mode without adding any
protocol bits. The host controller has to recover the clock reference in receiving Mode and control the Bit
time in transmission mode. RxD line is forced to a low logic level when no carrier is detected.
ST7538 12/30
Synchronous mode. St7538 allows to interface the host Controller using a four lines synchronous interface (RXD,TXD, CLR/T
& RxTx). ST7538 is always the master of the communication and provides the clock reference on CLR/T
line.
When ST7538 is in receiving mode an internal PLL recovers the clock reference. Data on RxD line are
stable on CLR/T rising Edge.
When ST7538 is in transmitting mode the clock reference is internally generated and data are read on TxD
line on CLR/T rising Edge.
If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7538 enters in an Idle State and CLR/T
line is forced Low. After Tcc time the modem starts providing received data on RxD line.
If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7538 d in an Idle State and transmission
circuitry is switched on. (figure 3). After Tcc time the modem starts transmitting data present on TXD line
(figure 3) .
Figure 2.
Figure 3. Data Reception -> Data Transmission -> Data receptionPACKET MODE (Only for Reception)
In Packet mode data transmission from ST7538 to Host Controller is done at a higher speed than the
Mains one. This function could reduce the efficiency of data exchange process because the Host Control-
ler is involved in data reception for a shorter period of time.
To achieve this function is enabled an internal auxiliary buffer which stores the incoming bits. The buffer
is transferred to the host controller when full at the packet rate. The packet rate is programmable and is
related to the Mclk clock frequency. The length of the packet can be also programmed through the control
register (see table 9) to be 16, 14, 9 or 8 bits.
The packet mode to start working needs two levels of enable. One at the control register level the other at
the pin level. TxD is the pin that if forced High enables the Packet Mode Function. According to when TxD
is forced high, the next incoming bit is stored inside the internal buffer or delivered on RxD pin. If TxD pin
is forced low during a RX session the transceiver starts working in bit mode and the content of the packet
buffer is deleted.
13/30
ST7538
Figure 4. Packet Mode Timing
Control Register AccessThe communication with ST7538 Control Register is always synchronous. The access is achieved using
the same lines of the Mains interface (RxD, TxD and CLR/T) plus REG_DATA Line.
With REG_DATA = 1 and RxTx=0, the data present on TxD are loaded into the Control Register MSB first.
The ST7538 sampled the TxD line on CLR/T rising edges. The control Register content is updated at the
end of the register access section (REG_DATA falling edge). If more than 24 bits are transferred to
ST7538 only the latest 24 bits are stored inside the Control Register.
With REG_DATA = 1 and RxTx=1, the content of the Control Register is sent on RxD port. The Data on
RxD are stable on CLR/T rising edges MSB First.
ST7538 14/30
Figure 5. Data Reception � Control Register read � Data Reception Timing Diagram
Figure 6. Data Reception � Control Register write � Data Reception Timing Diagram
Figure 7. Data Transmission � Control Register read � Data Reception Timing Diagram
Figure 8. Data Transmission � Control Register Write � Data Reception Timing Diagram
15/30
ST7538
Receiving ModeThe receive section is active when RxTx Pin =”1” and REG_DATA=0.
The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass
Filter (+-10KHz). The Pre-Filter can be removed setting one bit in the Control Register. The Input Stage
features a wide dynamic range to receive Signal with a Very Low Signal to Noise Ratio. The Amplitude of
the applied waveform is automatically adapted by an Automatic Gain Control block (AGC) and then filtered
by a Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (+-6K). The result-
ing signal is down-converted by a mixer using a sinewave generated by the FSK Modulator. Finally an
Intermediate Frequency Band Pass-Filter (IF Filter) improves the Signal to Noise ration before sending the
signal to the FSK demodulator. The FSK demodulator then send the signal to the RX Logic for final digital
filtering. Digital filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal
Jitter. RxD Line is forced at logic level “0” when neither mark or space frequencies are detected on RAI Pin.
Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct de-
modulation.
While ST7538 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line Interface included,
are turned off. This allows the device to achieve a very low current consumption (5 mA typ). In Receiving
mode ATOP2 pin is internally connected to PAVSS.
High Sensitivity ModeIt is possible to increase ST7538 Receiving Sensitivity setting to “1” the High Sensitivity Bit of Control
Register. This Function allows to increase the communication reliability when the ST7538 sensitivity is
the limiting factor.
Synchronization Recovery System (PLL)ST7538 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host
Controller.
The clock recovery system is realized by means of a second order PLL. Data on the data line (RxD) are
stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN
Range).
The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock condition, CLR/T and RxD
lines are forced to a low logic level.
When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number
of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive
only to RxD rising Edges to reduce the CLR/T Jitter.
ST7538 PLL is forced in the un-lock condition, when more than 32 equal symbols are received.
Figure 9.
