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ST72T311J2B6SGSN/a250avai8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERS
ST72T311J4T3STN/a24avai8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERS
ST72T311J4T6ST ?N/a6538avai8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERS
ST72T311N4B6STN/a236avai8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERS


ST72T311J4T6 ,8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERSFunctional Description . . . . . . . 795.6.4 Low Power Modes . . 795.6.5 Interrupts ..
ST72T311N4B6 ,8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERSfeatures an enhanced instruction set. The device Voltage Detector (LVD) and the following on-chipis ..
ST72T311R6 ,8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACESTable of Contents12.4.5 On-Chip Peripheral . . . . . . . 13712.5 CLOCK AND TIMING CHARACTERI ..
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ST72T311R6T6 ,8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACESTable of Contents8.3 I/O PORT IMPLEMENTATION . . . . 418.4 LOW POWER MODES . . 428.5 I ..
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STR710FZ2T6 ,STR71x: 144/64-pin ARM7TDMI MCU with up to 256KB FLASH, 64KB RAM and EMIfeatures including CAN, USB and External Memory Interface. The two 64-pin versions do notinclude Ex ..
STR710RZH6 ,ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CANFeatures■ Core– ARM7TDMI 32-bit RISC CPULQFP6410 x 10– 59 MIPS @ 66 MHz from SRAM LQFP14420 x 20– 4 ..
STR710RZT6 ,ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CANThermal characteristics . . . . 36Table 11. General operating conditions . . . . . . . 37 ..


ST72T311J2B6-ST72T311J4T3-ST72T311J4T6-ST72T311N4B6
8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERS
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ST72E31 1
ST72T31 1
8-BIT MCU WITH 8 TO 16K OTP/EPROM,
384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
a User Program Memory (OTP/EPROM):
8 to 16K bytes
a Data RAM: 384 to 512 bytes including 256 bytes
of stack
Master Reset and Power-On Reset
Low Voltage Detector Reset option
Run and Power Saving modes
44 or 32 multifunctional bidirectional IIO lines:
- 15 or 9 programmable interrupt inputs
- 8 or 4 high sink outputs
- 8 or 6 analog alternate inputs
- 13 alternate functions
- EMI filtering
a Software or Hardware Watchdog (WDG)
a Two 16-bit Timers, each featuring:
- 2 Input Captures 1)
- 2 Output Compares 1)
- External Clock input (on Timer A)
- PWM and Pulse Generator modes
I: Synchronous Serial Peripheral Interface (SPI)
n Asynchronous Serial Communications Interface
a 8-bit ADC with 8 channels 2)
a 8-bit Data Manipulation
n 63 basic Instructions and 17 main Addressing
" 8 x 8 Unsigned Multiply Instruction
a True Bit Manipulation
a Complete Development Support on DOS/
WINDOWSTM Real-Time Emulator
a Full Software Package on DOSNVINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
Device Summary
DATASHEET
PSDIP42 CSDIP42W
PSDIP56 CSDIP56W
TQFP64 TQFP44
(See ordering information at the end ofdatasheet)
Notes:
1. One only on Timer A.
2. Six channels only for ST72T311J.
Features ST72T311J2 ST72T311J4 ST72T311N2 ST72T311N4
Program Memory - bytes 8K 16K 8K 16K
RAM (stack) - bytes 384 (256) 512 (256) 384 (256) 512 (256)
Peripherals Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset
Operating Supply
3 to 5.5V
CPU Frequency
8M Hz max (16MHz oscillator) - 4MHz max over 85°C
Temperature Range
- 40°C to + 125°C
Package TQFP44 - SDIP42
I TQFP64 - SDIP56
Note: The ROM versions are supported by the ST72314 family.
May 2001
Rev. 1.8
Table of Contents
1 GENERAL DESCRIPTION M..................................................... 4
1.1 INTRODUCTION _........................................................ 4
1.2 PIN DESCRIPTION _...................................................... 5
1.3 EXTERNAL CONNECTIONS ................................................ 9
1.4 MEMORY MAP w....................................................... . 10
1.5 OPTION BYTE w......................................................... 13
2 CENTRAL PROCESSING UNIT ................................................. 14
2.1 INTRODUCTION ........................................................ 14
2.2 MAIN FEATURES ....................................................... 14
2.3 CPU REGISTERS _...................................................... 14
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES ........................ 17
3.1 CLOCK SYSTEM _....................................................... 17
3.1.1 General Description ................................................. 17
3.1.2 External Clock ..................................................... 17
3.2 RESET _............................................................... 18
3.2.1 Introduction _...................................................... 18
3.2.2 External Reset ..................................................... 18
3.2.3 Reset Operation _................................................... 18
3.2.4 Low Voltage Detector Reset .......................................... 19
4 INTERRUPTS ............................................................... 20
4.1 NON MASKABLE SOFTWARE INTERRUPT .................................. 20
4.2 EXTERNAL INTERRUPTS _............................................... 20
4.3 PERIPHERAL INTERRUPTS ............................................... 20
4.4 POWER SAVING MODES ................................................. 23
4.4.1 Introduction _...................................................... 23
4.4.2 Slow Mode w....................................................... 23
4.4.3 WaitMode ........................................................ 23
4.4.4 Halt Mode _........................................................ 24
4.5 MISCELLANEOUS REGISTER ............................................. 25
5 ON-CHIP PERIPHERALS ...................................................... 26
5.1 I/O PORTS ............................................................. 26
5.1.1 Introduction ....................................................... 26
5.1.2 Functional Description ............................................... 26
5.1.3 I/O Port Implementation .............................................. 27
5.1.4 Register Description ................................................. 30
5.2 WATCHDOG TIMER (WDG) ............................................... 32
5.2.1 Introduction _...................................................... 32
5.2.2 Main Features W.................................................... 32
5.2.3 Functional Description w.............................................. 32
5.2.4 Hardware Watchdog Option ........................................... 33
5.2.5 Low Power Modes .................................................. 33
5.2.6 Interrupts _........................................................ 33
5.2.7 Register Description w................................................ 33
5.3 16-BIT TIMER _......................................................... 35
5.3.1 Introduction _...................................................... 35
5.3.2 Main Features w.................................................... 35
5.3.3 Functional Description ............................................... 35
5.3.4 Low Power Modes P................................................ 47
5.3.5 Interrupts _........................................................ 47
2/101 dry
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