ST72T251 ,REAL-TIME DEVELOPMENT TOOLS FOR THE ST7 MCU FAMILYFEATURES■ A common Hardware Development System ■ Logic Analyzer events may trigger a breakpointmain ..
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ST72T251G1B6 ,8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WGD, SPI, I2C AND 2 TIMERSfeatures an enhanced instruction set. The de- RAM, 22 I/O lines and the following on-chip pe-vice n ..
ST72T251G1M6 ,8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WGD, SPI, I2C AND 2 TIMERSTable of Contents7.8 I2C CHARACTERISTICS . . 958 GENERAL INFORMATION . . . . . 968.1 EP ..
ST72T251G2B6 ,8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WGD, SPI, I2C AND 2 TIMERSGeneral Description . 153.2 RESET 163.2.1 Introduction . . . . . . . 163.2.2 E ..
ST72T251G2M6 ,8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WGD, SPI, I2C AND 2 TIMERSST722518-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,2256 BYTES RAM, ADC, WDG, SPI, I C AND 2 TIMERSDATASHEE ..
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STR710FZ2T6 ,STR71x: 144/64-pin ARM7TDMI MCU with up to 256KB FLASH, 64KB RAM and EMIfeatures including CAN, USB and External Memory Interface. The two 64-pin versions do notinclude Ex ..
STR710RZH6 ,ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CANFeatures■ Core– ARM7TDMI 32-bit RISC CPULQFP6410 x 10– 59 MIPS @ 66 MHz from SRAM LQFP14420 x 20– 4 ..
STR710RZT6 ,ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CANThermal characteristics . . . . 36Table 11. General operating conditions . . . . . . . 37 ..
ST72T251
REAL-TIME DEVELOPMENT TOOLS FOR THE ST7 MCU FAMILY
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ST7MDTx-EMU2
REAL-TIME DEVELOPMENT TOOLS
FOR THE ST7 MCU FAMILY
FEATURES
A common Hardware Development System
mainframe supports the entire ST7 family of
MCUs, in conjunction with the appropriate
ST7xxx-DBE Dedicated Board Emulator.
Real-time source level emulation allows viewing
and breakpoint setting on high level source
code rather than on disassembled target code
for optimum user friendliness.
64 KBytes of user modifiable and configurable
emulation RAM, allows memory mapping of all
ST7 family devices as well as modelling
hypothetical memory configurations.
Unlimited breakpoints may be set for any op-
code fetch or any address access, and
conditions may be defined for the generation of
2 external synchronization signals.
1K by 32-bit wide trace memory for Logic
Analyzer allows complex and sequential events
to be defined on any combination of address
and data, as well as 3 internal and 5 external
logic signals.
Logic Analyzer events may trigger a breakpoint
or simply define data capture parameters, in
accordance with user preferences.
Simple connection ofthe emulator system to the
Host PC via RS-232 serial channel or via
parallel port”
Emulation system may be driven by a Windows-
based GNU debugger software or DOS
software running on host PC, allowing full
control and monitoring of hardware resources.
Multiple windows allow concurrent real-time
display ofsource code, MCU resources, internal
registers, trace data, etc.
Log files allow storage and subsequent
redisplay of any displayed screen for
subsequent analysis.
Command flles can be used to execute a set of
debugger commands in batch mode.
Editable configuration files ensure tailoring of
working environment to user preferences.
Note 1. On the ST7-EMU2 version of the Emulator.
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ST7MDTx-EMU2
OVERVIEW
The ST7 real-time development tools consist of
various hardware and software components,
which together form a flexible and sophisticated
system designed to provide comprehensive devel-
opment support for the ST7 family of MCUs.
The Hardware Development System (HDS) main-
frame is common to all ST7 devices and, in con-
junction with various Dedication Board Emulators
(DBE), allows emulation and development of spe-
cific devices. Only the DBE and probe need to be
changed to emulate a new ST7 family device.
The development system is controlled by a Host
PC on which a choice of Windows-based software
may be run. The Host PC is simply connected to
the Emulator Mainframe by means of an RS-232
serial link or a parallel port. The STVD7 Windows
GNU Debugger software suite is supplied as
standard issue with the Emulator hardware, in ad-
dition to the conventional DOS ST7 Software
suite, which includes a macroassembler, a link-
er/loader. Third party C Toolchain and Debugger
software is also available. The Windows-based
debugger provides a user friendly and highly flexi-
ble interface which may be configured to precisely
match the user's requirements. All emulator set-
tings are accessible via the control software.
Once assembled, and/or compiled and linked, the
application software may be downloaded to the
real-time emulation memory, which can be config-
ured, mapped and modified as required by the us-
er. The device probe is then connected to the ap-
plication target hardware in place of the MCU and
real-time emulation of the target application can
begin, thus allowing sophisticated testing and de-
bugging of both application hardware and soft-
User definable breakpoints allow the MCU to be
halted when the application software accesses
specific addresses, and/or addresses within a se-
lected range, and/or on data fetch cycles. The
user may then read and modify any register and
memory location. An on line ayiembl.er/disassem-
bler is also available to ease debugging.
An important feature of the ST7 development sys-
tem is that true source level debugging is possible,
meaning code may be viewed at source level and
breakpoints may be set on high level code, rather
than on disassembled target code. This is much
more meaningful to the user and ensures a more
convivial and productive development environ-
A separate and concurrent Logic Analyzer func-
tion is available. This hardware implemented func-
tion features 1KByte of 32-bit wide trace memory
which allows events to be defined for any combi-
nation of address (16 bits) and data (8 bits), as
well as according to the state of 3 internal and 5
external logic signals. Complex and sequential
conditions may be defined, and all bits are maska-
ble. The external signals are input from 5 probes
which can be connected to the target hardware.
Trace memory events may be used as break-
points or simply to trigger data acquisition accord-
ing to user specified parameters, without halting
the target system. Such a powerful tool enables
the user to detect and trap virtually any pattern,
and thus rapidly debug the target application.
Log files offer the ability to send any screen dis-
play to a text file. In particular, log files are very
useful to save the contents of the logic analyzer
and/or the contents of data registers to be subse-
quently analysed or printed.
Command files can be used to execute a set of
debugger commands in batch mode, to simplify
and speed up the emulation session.
Finally, when the target program is fully de-
bugged, the appropriate ST7 EPROM/OTP/
FLASH programming board can be used to pro-
gram the EPROM/OTP/FLASH version of the tar-
get device to allow stand-alone testing and evalu-
ation.
