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ST72T101G1M6-ST72T101G2B6-ST72T212G2M6-ST72T213G1B6-ST72T213G1M6
8-BIT MICROCONTROLLER (MCU) WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WGD, TIMERS, SPI
/eiTir, ST72101IST72212lST72213
8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,
256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
User Program Memory (ROM/OTP/EPROM):
4 to 8K bytes
Data RAM: 256 bytes, including 64 bytes of
Master Reset and Power-On Reset
1: Run, Wait, Slow, Halt and RAM Retention
22 multifunctional bidirectional l/O lines:
- 22 programmable interrupt inputs
- 8 high sink outputs
- 6 analog alternate inputs
- 10 to 14 alternate functions
- EMI filtering
1: Programmable watchdog (WDG)
n One or two 16-bit Timers, each featuring:
- 2 Input Captures
- 2 Output Compares
- External Clock input (on Timer A only)
- PWM and Pulse Generator modes
I: Synchronous Serial Peripheral Interface (SPI)
8-bit Analog-to-Digital converter (6 channels)
(ST72212 and ST72213 only)
8-bit Data Manipulation
63 Basic Instructions
17 main Addressing Modes
8 x 8 Unsigned Multiply Instruction
True Bit Manipulation
Complete Development Support on PC/DOS-
WINDOWSTM Real-Time Emulator
Full Software Package on DOS/WINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
DATASHEET
(See ordering information at the end of datasheet)
PSDIP32
CSDIP32W
Device Summary
Features ST72101G1 ST72101G2 ST72213G1 ST72212G2
Program Memory- bytes 4K 8K 4K 8K
RAM (stack) - bytes 256 (64)
16-bit Timers one one one two
ADC no no yes yes
Other Peripherals Watchdog, SPI
Operating Supply 3 to 5.5 V
CPU Frequency 8MHz max (16MHz oscillator) - 4MHz max over 85''C
Temperature Range - 40°C to + 125°C
Package SO28 - SDIP32
Rev. 1.8
May 2001 1/85
Table of Contents
1 GENERAL DESCRIPTION M..................................................... 4
1.1 INTRODUCTION _........................................................ 4
1.2 PIN DESCRIPTION _...................................................... 5
1.3 EXTERNAL CONNECTIONS ................................................ 9
1.4 MEMORY MAP ........................................................ . 10
2 CENTRAL PROCESSING UNIT ................................................. 13
2.1 INTRODUCTION ........................................................ 13
2.2 MAIN FEATURES ....................................................... 13
2.3 CPU REGISTERS V...................................................... 13
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES ........................ 16
3.1 CLOCK SYSTEM _....................................................... 16
3.1.1 General Description ................................................. 16
3.2 RESET _............................................................... 17
3.2.1 Introduction _...................................................... 17
3.2.2 External Reset w.................................................... 17
3.2.3 Reset Operation .................................................... 17
3.2.4 Power-on Reset .................................................... 17
4 INTERRUPTS q.............................................................. 18
4.1 NON MASKABLE SOFTWARE INTERRUPT .................................. 18
4.2 EXTERNAL INTERRUPTS ................................................ 18
4.3 PERIPHERAL INTERRUPTS ............................................... 18
4.4 POWER SAVING MODES ................................................. 21
4.4.1 Introduction ....................................................... 21
4.4.2 Slow Mode _....................................................... 21
4.4.3 WaitMode _....................................................... 21
4.4.4 Halt Mode _........................................................ 22
4.5 MISCELLANEOUS REGISTER ............................................. 23
5 ON-CHIP PERIPHERALS ...................................................... 24
5.1 l/O PORTS B............................................................ 24
5.1.1 Introduction _...................................................... 24
5.1.2 Functional Description ............................................... 24
5.1.3 I/O Port Implementation .............................................. 25
5.1.4 Register Description ................................................. 28
5.2 WATCHDOG TIMER (WDG) ............................................... 30
5.2.1 Introduction _...................................................... 30
5.2.2 Main Features q.................................................... 30
5.2.3 Functional Description ............................................... 31
5.2.4 Low Power Modes w................................................. 31
5.2.5 Interrupts P........................................................ 31
5.2.6 Register Description w................................................ 31
5.3 16-BIT TIMER _......................................................... 32
5.3.1 Introduction ....................................................... 32
5.3.2 Main Features ..................................................... 32
5.3.3 Functional Description ............................................... 32
5.3.4 Low Power Modes ................................................. 44
2/85 dry
