ST72F651AR6T1 ,ST7ST7265xLOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K2FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, ..
ST72F651AR6T1E ,LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPIST7265xLOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K2FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, ..
ST72T101G1M6 ,8-BIT MICROCONTROLLER (MCU) WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WGD, TIMERS, SPIELECTRICAL CHARACTERISTICS . . . . . . 747.4 RESET CHARACTERISTICS . . . . . . 757.5 OSC ..
ST72T101G2B6 ,8-BIT MICROCONTROLLER (MCU) WITH 4 TO 8K ROM/OTP/EPROM, 256 BYTES RAM, ADC, WGD, TIMERS, SPIST72101/ST72212/ST722138-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 ..
ST72T121J2 ,8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16 K ROM/OTP/EPROM, 384 TO 512 BYTES RAM, WDG, SCI, SPI & 2 TIMERSST72E121ST72T1218-BIT MCU WITH 8 TO 16K OTP/EPROM,384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERSD ..
ST72T141K2B6 ,8-BIT MICROCONTROLLER (MCU) FOR ELECTRIC-MOTOR CONTROL WITH 8K ROM/OTP/EPROM, 256 BYTES RAM,ADC, WDG, SPI & 2 TIMERS, SDIP32-SO34Table of Contents10.4 GENERAL TIMING CHARACTERISTICS . . . . 11910.5 I/O PORT CHARACTERISTICS ..
STR7102 , Separate Excitation Switching Type
STR7102 , Separate Excitation Switching Type
STR710FZ1H6 ,ARM-Based Flash microcontrollers with USB and CANAbsolute maximum ratings . . . . 354.3 Operating conditions 374.3.1 Supply current charac ..
STR710FZ2T6 ,STR71x: 144/64-pin ARM7TDMI MCU with up to 256KB FLASH, 64KB RAM and EMIfeatures including CAN, USB and External Memory Interface. The two 64-pin versions do notinclude Ex ..
STR710RZH6 ,ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CANFeatures■ Core– ARM7TDMI 32-bit RISC CPULQFP6410 x 10– 59 MIPS @ 66 MHz from SRAM LQFP14420 x 20– 4 ..
STR710RZT6 ,ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CANThermal characteristics . . . . 36Table 11. General operating conditions . . . . . . . 37 ..
ST72F651AR6T1
ST7
November 2002 1/160
Rev. 2.2
ST7265xLOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K
FLASH, 5K RAM, FLASH CARD I/F , TIMER, PWM, ADC, I2 C, SPI
PRELIMINARY DATA Memories Up to 32K of ROM or High Density Flash (HD-Flash) program memory with read/write pro-tection For HDFlash devices, In-Application Pro-gramming (IAP) via USB and In-Circuit pro-gramming (ICP) Up to 5 Kbytes of RAM with up to 256 bytesstack
Clock, Reset and Supply Management PLL for generating 48 MHz USB clock using a12 MHz crystal Low Voltage Reset (except on E suffix devic-es) Dual supply management: analog voltage de-tector on the USB power line to enable smartpower switching from USB power to battery(on E suffix devices). Programmable Internal Voltage Regulator forMemory cards (2.8V to 3.5V) supplying:Flash Card I/O lines (voltage shifting)Up to 50 mA for Flash card supply Clock-out capability
47 programmable I/O lines 15 high sink I/Os (8mA @0.6V /
[email protected]) 5 true open drain outputs 24 lines programmable as interrupt inputs
USB (Universal Serial Bus) Interface with DMA for full speed bulk applications com-pliant with USB 12 Mbs specification (version2.0 compliant) On-Chip 3.3V USB voltage regulator andtransceivers with software power-down 5 USB endpoints:1 control endpoint 2 IN endpoints supporting interrupt and bulk2 OUT endpoints supporting interrupt andbulk Hardware conversion between USB bulkpackets and 512-byte blocks
Device Summary
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4 POWER SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5611.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.2 DATA TRANSFER COPROCESSOR (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
11.5 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.7 I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11712.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12313.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
13.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 144
13.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15114.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 15315.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 154
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
16 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
1 INTRODUCTIONThe ST7265x MCU supports volume data ex-
change with a host (computer or kiosk) via a full
speed USB interface. The MCU is capable of han-
dling various transfer protocols, with a particular
emphasis on mass storage applications.
ST7265x is compliant with the USB Mass Storage
Class specifications, and supports related proto-
cols such as BOT (Bulk Only Transfer) and CBI
(Control, Bulk, Interrupt).
It is based on the ST7 standard 8-bit core, with
specific peripherals for managing USB full speed
data transfer between the host and most types of
FLASH media card:
– A full speed USB interface with Serial Interface
Engine, and on-chip 3.3V regulator and trans-
ceivers.
– A dedicated 24 MHz Data Buffer Manager state
machine for handling 512-byte data blocks (this
size corresponds to a sector both on computers
and FLASH media cards).
– A Data Transfer Coprocessor (DTC), able to
handle fast data transfer with external devices.
This DTC also computes the CRC or ECC re-
quired to handle Mass storage media.
– An Arbitration block gives the ST7 core priority
over the USB and DTC when accessing the Data
Buffer. In USB mode, the USB interface is serv-
iced before the DTC.
– A FLASH Supply Block able to provide program-
mable supply voltage and I/O electrical levels to
the FLASH media.
Figure 1. USB Data Transfer Block Diagram
INTRODUCTION (Cont’d)In addition to the peripherals for USB full speed
data transfer, the ST7265x includes all the neces-
sary features for stand-alone applications with
FLASH mass storage.
– Low voltage reset ensuring proper power-on or
power-off of the device (not on all products)
– Digital Watchdog
– 16-bit Timer with 2 output compare functions (not
on all products - see device summary).
– Two 10-bit PWM outputs (not on all products -
see device summary)
– Serial Peripheral interface (not on all products -
see device summary)
– Fast I2 C Single Master interface (not on all prod-
ucts - see device summary)
– 8-bit Analog-to-Digital converter (ADC) with 8
multiplexed analog inputs (not on all products -
see device summary)
The ST72F65x are the Flash versions of the
ST7265x in a TQFP64 package.
The ST7265x are the ROM versions in a TQFP64
package.
Figure 2. Digital Audio Player Application Example in Play Mode
