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ST70136
CPE ADSL ANALOG FRONT END
1/24September 2001 WIDE TRANSMIT AND RECEIVE DYNAMIC
RANGE TO REDUCE EXTERNAL
FILTERING REQUIREMENTS RECEIVE PROGRAMMABLE GAIN: 0 TO
31dB GAIN IN 1dB STEPS RECEIVE PROGRAMMABLE ATTENUATOR
0,-4dB, -8dB, -12dB 12-BIT A/D CONVERTER IN RECEIVE PATH TRANSMIT PROGRAMMABLE GAIN: 0 TO
-15dB IN 1dB STEPS 14-BIT D/A CONVERTER IN TRANSMIT PATH LOW POWER MODE: 10mW IN LISTENING
MODE, 250μW IN POWER DOWN TONE DETECTOR: ACTIVITY DETECTION
FOR WAKE-UP FUNCTION 64-PIN TQFP PACKAGE 64-PIN LFBGA PACKAGE 0.50μm, 5V BICMOS TECHNOLOGY 3.3V DIGITAL INTERFACE 5V ANALOG INTERFACE
INTRODUCTION
The ST70136 ADSL Analog Front End (AFE) chip
implements the analog transceiver functions
required in a Customer Premise ADSL modem. It
connects the digital modem chip with the loop
driver and hybrid balance circuits.
The AFE has been designed with high dynamic
range in order to greatly reduce the external filter-
ing requirements at the front end.
The AFE chip and its companion digital chip along
with a loop driver, implement the complete
G.992.2 and G.992.1 DMT modem solution.
The AFE receive path contains a programmable
gain amplifier (RxPGA), a low pass anti-aliasing
filter, and a 12-bit A/D converter. The RxPGA is
digitally programmable from 0 to 31dB in 1dB
steps.
The AFE transmit path consists of a 14-bit D/A
converter, followed by a programmable gain
amplifier (TxPGA). The transmit gain is program-
mable from 0 to -15dB in 1dB steps.
Figure 1 : Overall Application Block Diagram
ST70136
CPE ADSL ANALOG FRONT END
ST70136
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ST70136 Pinout
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1 - PIN LIST
The following list gives the different PIN Types:
AI Analog Input
AIO Analog Input/Output
AO Analog Ouptut
DI Digital Input
DIO Digital Input/Output
DO Digital Output
VDDA Analog Power Supply
VDDD Digital Power Supply
VSSA Analog Ground
VSSD Digital Ground
Table 1 : Pin Assignment
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* A "N" means active low. Example: R/NW means write active low.
Table 1 : Pin Assignment (continued)
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2 - PIN DESCRIPTION
2.1 - Analog Power Supplies
These pins are the positive analog power supply
voltage for the DAC and the ADC section. It is not
internally connected to digital supply. In any case
the voltage on these pins must be higher or equal
to the voltage of the Digital power supply.
2.2 - Digital Power Supplies
These pins are the power supply pins that are
used by the internal digital circuitry. All DVDD pins
must be connected together to a +3.3 V supply.
2.3 - Analog Ground and Substrate
These pins are the ground return of the analog
DAC and ADC blocks. The analog VDDA should
be decoupled with respect to the analog ground.
Decoupling capacitors should be as close as pos-
sible to the supplies pins. All grounds must be tied
together.
2.4 - Digital Ground
These pins are the ground return of the digital cir-
cuitry. The digital power supplies must should be
decoupled with respect to the digital ground.
Decoupling capacitors should be as close as pos-
sible to the supplies pins. All grounds must be tied
together.
2.5 - Powerdown - PWD
When pin PWD =”1”, the chip is set in low power
mode.
2.6 - Suspend
The SUSPEND pin is used to control the output of
CLKM. When SUSPEND is low CLKM output is
enabled otherwise CLKM is disabled.
2.7 - Reset
The reset function is implied when the NRESET
pin is at a low voltage input level. In this condition,
the reset function can be easily used for power up
reset conditions. Reset is asynchronous, tenths of
ns are enough to put the IC in reset. After reset, all
registers are set to their default value.
2.8 - Reference Voltages
2.8.1 - V125AD, V250AD, V375AD
These pins are used to externally decouple the
internal reference voltages used for the ADC
(1.25V, 2.5V, 3.75V).
2.8.2 - V3P75V
This pin is the 3.75V Bandgap output and should
be externally decoupled with an external capacitor
of 0.22uF.
2.8.3 - IREF50U
This pin is used for setting the bias current and
must be externally connected to a resistor of
2.5V/ 50μA equals 50kΩ.
2.8.4 - V290DA
This pin is the 2.9V transmit DAC output reference
voltage and must be decoupled externally.
2.9 - Analog Transmit Output
2.9.1 - TXP
This pin is the non-inverting output of the fully dif-
ferential analog amplifier.
2.9.2 - TXN
This pin is the inverting output of the fully differen-
tial analog amplifier.
2.9.3 - TXIP
This pin is the differential non-inverting input for
external filtering.
2.9.4 - TXIN
This pin is the differential inverting input for exter-
nal filtering.
2.9.5 - PGAP
This pin is the differential non-inverting PGA out-
put.
2.9.6 - PGAN
This pin is the differential inverting PGA output.
2.10 - Analog Receive Input
2.10.1 - RXN
This pin is the differential inverting receive input.
2.10.2 - RXP
This pin is the differential non-inverting receive
input.
2.11 - Tone Detector
The analog input differential signal must be less
than 8V peak to peak. These pins are used for
activity detection when in sleeping mode.
2.11.1 - TON
This pin is the differential inverting tone detector
input.
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2.11.2 - TOP
This pin is the differential non-inverting tone
detector input.
2.11.3 - ACTD
This pin is active when tone 40 or 72 has been
detected in sleeping mode (see control register)
2.12 - CRYSTAL
These pins must be tied to an external crystal= 35.328MHz).
2.12.1 - XTALI
This pin is the crystal oscillator input.
2.12.2 - XTALO
This pin is the crystal oscillator output.
2.13 - VCXO
2.13.1 - IVCO
This pin is the current reference for the VCO DAC
2.13.2 - VCOCAP
This pin is used to introduce time constant. The
tuning is done by connecting an external capacitor
2.13.3 - VCXOUT
This pin is the output control current generated by
a 8 bit DAC.
2.14 - Control Serial Interface
Access to the control register can be done only in
stable state fonctionality:
SUSPEND = "0".
2.14.1 - CTRLIN
This pin is used to program the internal registers.
The data burst is composed of 16 bits sampled at
CLKM when CLKWD = 1. The first bit is used as
start bit (’0’), the three LSBs being used to identify
the data contained in the twelve remaining bits.
The start bit b15 (b5 = 0) is transmitted first fol-
lowed by bits b[14:0]. At least 1 stop bit "1" need
to be provided to validate the data.
2.14.2 - CTRLOUT
This pin is the control register output. The burst
data on this pin is the value of the register
addressed by CTRLIN.
2.14.3 - CLKWD
This pin is the word clock used to sample the con-
trol information and equal to CLKM / 4.
2.14.4 - R/NW
This pin is used for the read and write operation
for the control interface and sampled at the same
time than bit b15 of CTRLIN.
2.14.5 - Digital Interface
The interface is a nibble serial interface running at
8.832MHz sampling frequency. The data are pre-
sented in 16bits format, and transferred in groups
of 4 bits (nibbles). The LSBs are transferred first.
Data is transmitted on the rising edge of the mas-
ter clock CLKM
2.14.6 - CLKM
This pin is the master clock equal to 35.328MHz
and is the sampling clock of the input / output
data.
2.14.7 - TX0, TX1, TX2, TX3
These pins are the digital transmit data input.
2.14.8 - RX0, RX1, RX2, RX3
These pins are the digital receive data output.
2.15 - Test
This pin is dedicated to put the ST70136 in test
mode.
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3 - BLOCK DIAGRAM
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4 - FUNCTIONAL DESCRIPTION
4.1 - General
The ST70136 consists of the following functional
blocks:
– Transmit Signal Path
– Receive Signal Path
– Bias Voltage and Current Generation
– Digital Data Interface
– Control Serial Interface
– Tone Detector
– Power Down mode management
4.2 - Transmit Path Description
The transmit path contains the 14-bit digital to
analog converter (DAC) necessary to generate
the transmit signal from a 16-bit digital input word.
This transmit signal is then scaled by the on chip
programmable gain amplifier (TxPGA) from 0 to
-15dB in 1dB steps. The scaled output signal is
then driven off chip to the external filters and
power amplifier (PA) which drives the DMT signal
to the subscriber loop. The transmit path is fully
differential.
4.3 - Receive Path Description
The receive path contains first an attenuator
(which allows the selection between 4 attenuated
versions of the signal) followed by a programma-
ble gain amplifier (RxPGA), a 1st order low pass
anti-aliasing filter, and a 12-bit analog to digital
converter (ADC). The RxPGA gain is digitally pro-
grammable from 0 to 31dB in 1dB steps. The
receive path is fully differential.
4.4 - VCXO
The ST70136 contains the circuits required to
construct an internal VCXO. It is divided in a crys-
tal driver and an auxiliary 8 bits DAC for timing
recovery. The crystal driver is able to operate at
35.328MHz.
The DAC which is driven by the CTRLIN pin (the
input of the Serial Control Interface), provides a
current output with 8 bits resolution and can be
used to tune the crystal frequency with the help of
external components. A time constant between
DAC input and VCXOUT can be introduced (via
CTRLIN interface) and programmed with the help
of an external capacitor (on VCOCAP pin).
4.5 - Bias Voltage and Current Generation
The bias circuitry contains a bandgap voltage ref-
erence from which the converters references and
analog ground voltages are generated. This block
also generates an accurate bias current using an
external resistor.
4.6 - Digital Data Interface
To facilitate data transfer between the ST70136
and the digital data pump, a 4-bit wide serial inter-
face for the transmit and receive path is incorpo-
rated into the AFE.
This interface consists of four transmit pins
(TX[0:3]), four receive pins (RX[0:3]), and the nec-
essary control signals (CLKM, CLKWD) to trans-
mit and receive the required data.
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Figure 2 : Digital Data Interface
4.7 - Control Serial Interface
There is a 4-pin serial digital interface (CLKWD,
CTRLIN, CTRLOUT, R/W) that access one of the x 12-bit registers that controls all the program-
mable features on the ST70136.
The registers are loaded with the asynchronous
type data burst delivered to CTRLIN pin. It is com-
posed of 16 bits from which the first bit (b15) is
used as start bit (‘0’), the three LSBs (b2:b0) being
used to identify the register to be loaded.
The twelve remaining bits (b14:b3) are the control
data. During a read operation, the CTRLOUT pin
figures out the register contents addressed by
CTRLIN pin.
Figure 3 : Control Register Interface Write Cycle
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Figure 4 : Control Register Interface Read cycle
4.7.1 - AFE registers
4.7.1.1 - Rx Gain Control
This register is located at the address “000” and is used to program the gain in the receive path.
4.7.1.2 - Tx Gain Control
This register is located at the address “001” and is used to program the gain in the transmit path.
Table 2 : Rx Gain Control (address [b2:b0]=”000”)
Table 3 : Tx Gain Control (address [b2:b0]=”001”)
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4.7.1.3 - Special Features Configuration
This register is located at the address “010” and is used to configure different blocks.
4.7.1.4 - VCXO Control
4.7.1.5 - Test Only Registers
They are presently located at address “100” to “101”.
4.7.1.6 - Tone Detection Threshold Setting Register
4.7.1.7 - Status Register & tone detector
This register can be used in the case of read / write registers.
Note: 1. R/W_clear: bit is resetted to 0 by writing 0.
Table 4 : Adsl Configuration (address [b2:b0]=”010”)
Table 5 : VCXO DAC Value (address [b2:b0]=”011”)
Table 6 : Tone Detection Threshold Setting Register (address [b2:b0]=”110”)
Table 7 : Status & Tone Detector Register (address [b2:b0]=”111”)
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4.8 - Tone Detector
The tone detector is dedicated for remote activation. It operates during SUSPEND mode with PWD = 0
only. When the tone detector level received Vin over tone 40 or 72 is greater than 15μV peak to peak, the
ACTD pin is set to wake up the modem.
ACTD pin is resetted when the AFE is back in full operating mode (SUSPEND = 0, PWD = 0). The maxi-
mum signal sensitivity at the Tone detector inputs is 50mV peak to peak.
4.9 - Mode Management
4.9.1 - General
The ST70136 can be used in a various range of ATU-R equipments, but a specific mode management
address USB application in its different modes.
In following table, "CPE" is an USB ADSL modem application done with a ST70136 AFE and a ST70137
DMT. The CPE is connected to an USB port of an equipment.
Table 8 : ST70136 / USB Operating Mode Configurations
Figure 5 : USB Power Management Operating Modes

Partno	Mfg	Dc	Qty	Available	Descript
ST70136	ST	N/a	2175	avai	CPE ADSL ANALOG FRONT END