ST70134 ,ASCOT ADSL MODEM CHIP SET FOR CPEST70134 - ST70134ATMASCOT INTEGRATED ADSL CMOSANALOG FRONT-END CIRCUIT■ FULLY INTEGRATED AFE FOR CP ..
ST70134A ,ASCOT (TM) INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUITST70134 - ST70134ATMASCOT INTEGRATED ADSL CMOSANALOG FRONT-END CIRCUIT■ FULLY INTEGRATED AFE FOR CP ..
ST70135 ,ASCOTTM DMT TRANSCEIVERGENERAL DESCRIPTIONINTERLEAVEDThe ST70135A is the DMT modem and ATMframer of the STMicroelectronics ..
ST70135A ,ASCOT DMT TRANSCEIVERGENERAL DESCRIPTIONINTERLEAVEDThe ST70135A is the DMT modem and ATMframerof the STMicroelectronics ..
ST70135A/ ,ASCOT DMT TRANSCEIVERBlock DiagramTEST SIGNALS CLOCKTEST MODULE DATA SYMBOL TIMING UNIT VCXOGENERICTRELLISSTMDSP FFT/IFF ..
ST70136 ,CPE ADSL ANALOG FRONT ENDST70136CPE ADSL ANALOG FRONT END■ WIDE TRANSMIT AND RECEIVE DYNAMIC The AFE receive path contains a ..
STPR2010CT ,On Technology Corporation - SUPER FAST GLASS PASSIVATED RECTIFIERS
STPR2420CT ,ULTRA FAST RECOVERY RECTIFIER DIODESapplications.Symbol Parameter Value UnitRepetitive peak reverse voltageVRRM 200 VRMS forward curren ..
STPR2520CW ,Diode
STPR320 ,Conductor Holdings Limited - SUPER FAST RECTIFIERS
STPR502D , Ultra Fast Recovery Diodes
STPR520D ,ULTRA-FAST RECOVERY RECTIFIER DIODESFEATURESn Suited for SMPSTO-220AC ISOWATT220ACn Very low forward lossesSTPR520D STPR520Fn Negligibl ..
ST70134-ST70134A
ASCOT (TM) INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
1/22January 2001 FULLY INTEGRATED AFE FOR CPE ADSL OVERALL 12 BIT RESOLUTION, 1.1MHz
SIGNAL BANDWIDTH IN Rx 8.8MS/s ADC 8.8MS/s DAC THD: -60dB @FULL SCALE 4-BIT DIGITAL INTERFACE TO/FROM THE
DMT MODEM 1V FULL SCALE INPUT DIFFERENTIAL ANALOG I/O ACCURATE CONTINUOUS-TIME CHANNEL
FILTERING 3rd & 4th ORDER TUNABLE CONTINUOUS
TIME LP FILTERS 0.5 WATT AT 3.3V 0.5mm HCMOS5 LA TECHNOLOGY 64 PIN TQFP PACKAGE
DESCRIPTIONST70134 is the Analog Front End of the STMicro-
electronics ASCOTTM ADSL chipset and when
coupled with ST70135A or ST70235 (DMT
modem) allows to get a T1.413 Issue 2 or G.dmt
compliant solution.
The ST70134 analog front end handles 2 trans-
mission channels on a balanced 2 wire intercon-
nection; a 16 to 640Kbit/s upstream transmit
channel and a 1.536Mbit/s to 8.192Mbit/s down-
stream receive channel.
This asymmetrical data transmission system uses
high resolution, high speed analog to digital and
digital to analog conversion and high order analog
filtering to reduce the echo and noise in both
receivers and transmitters.
External low noise driver and input stage used
with ST70134 guarantee low noise performances.
The filters, with a programmable cutoff frequency,
use automatic Continuous Time Tuning to avoid
time varying phase characteristic which can be of
dramatic consequence for DMT modem.
It requires few external components, uses a 3.3V
supply. It is packaged in a 64-pin TQFP in order to
reduce PCB area.
ST70134 - ST70134AASCOTTM INTEGRATED ADSL CMOS
ANALOG FRONT-END CIRCUIT
ST70134A 2/22
Figure 1 : Block Diagram
The Receiver (RX) PartThe DMT signal coming from the line to the
ST70134 is first filtered by two external filters,
Pots HP and channel filters.
An analog multiplexer allows the selection
between two input ports which can be used to
select an attenuated (0, 10dB for ex.) version of
the signal in case of short loop or large echo.
The signal is amplified by a low noise gain stage
(0-31dB) then low-pass filtered to avoid aliasing
and to ease further digital processing by removing
unwanted high frequency out-of-band noise.A
13-bit A/D converter samples the data at
8.832MS/s (or 4.416MS/s in alternative mode),
transforms the signal into a digital representation
and sends it to the DMT signal processor via the
digital interface.
The Transmitter (TX) partThe 12-bit data words at 8.832MS/s (or 4.416MS/
s) coming from the DMT signal processor through
the digital interface are transformed by D/A con-
verter into a analog signal.
This signal is then filtered to decrease DMT side-
lobes level and meet the ANSI transmitter spectral
response but also to reduce the out-of-band noise
(which can be echoed to the RX path) to an
acceptable level. The pre-driver buffers the signal
for the external line driver and in case of short
loop provide attenuation (-15...0dB).
The VCXO PartThe VCXO is divided in a XTAL driver and a auxil-
iary 8 bits DAC for timing recovery.The XTAL
driver is able to operate at 35.328MHz.
The DAC which is driven by the CTRLIN pin pro-
vides a current output with 8-bit resolution and
can be used to tune the XTAL frequency with the
help of external components. time constant between DAC input and VCXO
output can be introduced (via the CTLIN interface)
and programmed with the help of an external
capacitor (on VCOC pin).See chapter ’VCXO’ for
the external circuit related to the VCXO.
The Digital Interface PartThe digital part of the ST70134 can be divided in 2
sections:
– The data interface converts the multiplexed data
from/to the DMT signal processor into valid
representation for the TX DAC and RX ADC.
– The control interface allows the board processor
to configure the STL70134 paths (RX/TX gains,
filter band, ...) or settings (OSR, vcodac enable,
digital / analog loopback,...).
ST70134A3/22
DMT Signal (Done by the DMT companion
chip)A DMT signal is basically the sum of N indepen-
dently QAM modulated signals, each carried over
a distinct carrier. The frequency separation of
each carrier is 4.3125kHz with a total number of
256 carriers (ANSI). For N large, the signal can be
modelled by a gaussian process with a certain
amplitude probability density function. Since the
maximum amplitude is expected to arise very
rarely, we decide to clip the signal and to trade-off
the resulting SNR loss against AD/DA dynamic. A
clipping factor (Vpeak/Vrms = "crest factor") of 5.3
will be used resulting in a maximum SNR of 75dB.
ADSL DMT signals are nominally sent at an aver-
age of -38dBmHz (-1.65dBm/carrier) with a maxi-
mal power of 15.7mW for the transmitter
(upstream for ADSL over Pots, DMT carriers are
from 7 to 31, for ADSL over ISDN DMT carriers
are from 31 to 64).
Maximum / Minimum Signal LevelsThe following table gives the transmitted and
received signal levels for CPE (ATU-R) and, for
reference, at ATU-C. All the levels are referred to
the line voltages (i.e. after hybrid and transform-
ers in TX direction, before hybrid and transformer
in RX direction).
Note that signal amplitudes shown below are for
illustration purpose and depending on the transmit
power and line impedance signal amplitudes can
differ from these values.
The reference line impedance for all power calcu-
lations is 100Ω.
PackageThe ST70134 is packaged in a 64-pin TQFP pack-
age (body size 10x10mm, pitch 0.5mm).
* Power cut back software co facility.
Table 1 : Target Signal Levels (on the line)
ST70134A 4/22
Figure 2 : Pin Connection
ST70134A5/22
Table 2 : Pin Functions
ST70134A 6/22
Figure 3 : Grounding and Decoupling Networks
ST70134A7/22
BLOCK DIAGRAMApplication principle is described in Figure4.
A LP filter may be used on the TX path to reduce
DMT sidelobes and out of band noise influence on
the receiver. On the RX path, a HP filter must be
used in order to reduce the echo signal level and
to avoid saturation of the input stage of the
receiver. The POTS filter is used in both directions
to reduce crosstalk between ADSL signals and
POTS speech and signalling. Low pass POTS fil-
ter can be very simple for Lite - ADSL application
(see Figure 4).
RX Path
Speech FilterAn external bi-directional LC filter for up and
downstream POTS service splits the speech sig-
nal from the ADSL signal to the POTS circuits.
The ADSL analog front end integrated circuit does
not contain any circuitry for the POTS service but
it guarantees that bandwidth is not disturbed by
spurious signals from the ADSL-spectrum.
Channel FiltersThe external analog circuits provide partial echo
cancellation by an analog filtering of the transmit
upstream signal. This is feasible because the
upstream and the downstream data are modu-
lated on separate carriers (FDM) (see Figure 4).
Signal to Noise Performance
RX- PATH SENSITIVITY AT MAXIMUM GAINThe RX path sensitivity at the maximal RX-AGC of
the receiver is defined at -140dBm/Hz (for 100Ω
ref) on the line. This figure corresponds to the
equivalent input noise of 31nVHz-1/2 seen on the
line.
The maximum noise density within the pass band
can exceed the average value as follows:
RX path (max AGC setting):
<100nVHz-1/2 @ 138kHz
<31nVHz-1/2 for 250kHz < f
* For ADSL over ISDN, instead of SC2, HC2 1.1MHz LP filter is programmed.
Figure 4 : Block Diagram
ST70134A 8/22
RX-PATH NOISE AT MINIMUM GAINAt the minimum AGC the total average thermal
noise of the analog RX-path at the ADC input
should be lower than the ADC quantisation noise.
The maximum noise density within the pass band
can exceed the average value as follows:
RX path (min AGC setting) <500nVHz-1/2 @
138kHz < f
These noise specifications correspond to 10bit
resolution of the complete RX-path.
AGC of RX PathThe AGC gain in the RX-path is controlled through
a 5-bits digital code.
Four inputs are provided for RX input and the
selection is made with the RXMUX bits of the
CTRLIN interface.
This can be used to make lower gain paths in
case of high input signal.
RX FiltersThe combination of the external filter (an LC lad-
der filter typically) with the integrated lowpass fil-
ter must provide:
– Echo reduction to improve dynamic range.
– DMT sidelobe and out of band (anti-aliasing) at-
tenuation.
– Anti alias filter (60dB rejection @ image frequency).
RX FiltersThe integrated filter have the following character-
istics:
Table 3 : RX Common-mode Voltage
Table 4 : AGC Characteristics
Table 5 : Integrated HC Filter Characteristics
Table 6 : Phase Characteristic
ST70134A9/22
Figure 5 : HC Filter Mask for RX Note: The total RX path (including ADC) group delay distortion is 16μs (i.e. = 15μs + 1μs of ADC)
Linearity of RXLinearity of the RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies f1
and f2 and each with 0.5Vpd amplitude (total ≤ 1Vpd) at the output of the RX - AGC amplifier (i.e: before
the ADC) for the case of minimal AGC setting.
Table 7 lists the RX path intermodulation distortion (as S/IM3 ratio) in downstream and upstream band-
width.
Power Supply RejectionThe noise on the power supplies for the RX path must be lower than the following: <50mVrms in band
white noise for any AVDD.
In this case, PSR (power supply rejection) of ST70134 RX path is lower than -43dB.
Table 7 : Linearity of RX
Table 8 : RX Filter to A/D Interface
Table 9 : A/D Converters
ST70134A 10/22
TX Pre-driver CapabilityThe pre-driver drives an external line power amplifier which transmits the required power to the line.
TX FilterThe TX filter acts not only to suppress the DMT sidebands but also as smoothing filter on the D/A conver-
tor’s output to suppress the image spectrum. For this reason it must be realized in a continuous time
approach.
ATU-R TX FilterThe purpose of this filter is to remove out-of-band noise of the TX path echoed to the RX path. In order to
meet the transmitter spectral response, an additional filtering must be (digitally) performed. The inte-
grated filter has the following characteristics:
Note: The total TX path (including DAC) group delay distortion is 16μs (i.e. = 15μs + 1μs of DAC).
Table 10 : TX Pre-driver
Table 11 : Integrated SC Filter Characteristics
ST70134A11/22
Figure 6 : SC Filter Mask for TX
Linearity in TXLinearity of the TX is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and
each with 0.5Vpd amplitude (total ≤ 1Vpd) at the output of the pre-driver for the case of a total
AGC= 0dB.
TX Idle Channel NoiseThe idle channel noise specifications correspond with 11bit resolution of the complete TX-path. TX idle
channel output noise on TXP, TXN.
Power Supply RejectionThe noise on the power supplies for the TX-path must be lower than the following: 50mVrms in-band white noise for AVDD. 15mVrms in-band white noise for Pre-driver AVDD.
VCXO voltage controlled crystal oscillator driver is integrated in ST70134. The nominal frequency is
35.328MHz. The quartz crystal is connected between the pins XTALI and XTALO. The principle of the
VCXO control is shown in Figure7.
Table 12 : D/A Converter (A current steering architecture is used)
Table 13 : Linearity in TX
Table 14 : TX idle channel noise
