ST6397B1 ,8-BIT MICROCONTROLLER (MCU) FOR TV FREQUENCY SYNTHESIS WITH OSDGENERAL DESCRIPTION . . . . ... . ... . . . 3PINDESCRIPTION .. .. ... .. .. . ... .. .. ... .. . ..
ST63T87B1 ,8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNINGGENERAL DESCRIPTION . . . . . . 51.1 INTRODUCTION . 51.2 PIN DESCRIPTION . . ..
ST63T88B1 ,8-BIT MCUS WITH ON-SCREEN-DISPLAY FOR TV TUNINGGENERAL DESCRIPTION . . . . . . 51.1 INTRODUCTION . 51.2 PIN DESCRIPTION . . ..
ST662A , DC-DC CONVERTER FROM 5V TO 12V, 0.03A FOR FLASH MEMORY PROGRAMMING SUPPLY
ST662A , DC-DC CONVERTER FROM 5V TO 12V, 0.03A FOR FLASH MEMORY PROGRAMMING SUPPLY
ST662AB ,DC-DC CONVERTER FROM 5V TO 12V, 0.03A FOR FLASH MEMORY PROGRAMMING SUPPLYAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
STP9NB50 ,N-CHANNEL 500VELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFFSymbol Parameter Test Condi ..
STP9NB50. ,N-CHANNEL 500VABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitSTP9NB50 STP9NB50FPV Drain-source Voltage (V = 0 ..
STP9NB50FP ,N-CHANNEL ENHANCEMENT MODE POWERMESH MOSFETSTP9NB50STP9NB50FPN-CHANNEL 500V - 0.75 Ω - 8.6 A TO-220/TO-220FPPowerMesh™ MOSFETTYPE V R IDSS DS( ..
STP9NB60 ,N-CHANNEL 600VSTP9NB60STP9NB60FP®N - CHANNEL 600V - 0.7Ω - 9A TO-220/TO220FPPowerMESH™ MOSFETTYPE V R IDSS DS(on ..
STP9NB60FP ,N-CHANNEL 600VSTP9NB60STP9NB60FP®N - CHANNEL 600V - 0.7Ω - 9A TO-220/TO220FPPowerMESH™ MOSFETTYPE V R IDSS DS(on ..
STP9NC60 ,N-CHANNEL 600VSTP9NC60STP9NC60FPN-CHANNEL 600V - 0.6Ω - 9A - TO-220/TO-220FPPowerMesh™II MOSFETTYPE V R IDSS DS(o ..
ST6391B1-ST6397B1
8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD
ST6391, ST6392, ST6393
ST6395, ST6397, ST6399
DATA SHEET
USEIN LIFE SUPPORTDEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USEAS CRITICAL COMPONENTS INLIFE SUPPORT DEVICESOR SYS-
TEMS WITHOUT THEEXPRESSWRITTEN APPROVALOF SGS-THOMSON Microelectronics. used herein: Life support devicesor systems are those which(a) are
intendedfor surgical implantintothe body,or (b)support sustain life, and whose failureto perform, when prop-
erly usedin accordance with instructionsfor use pro-
vided with the product, canbe reasonably expectedtoA critical componentis any componentofalife support
deviceor system whose failureto perform can reason-
ablybe expectedto causethe failureofthelife support
deviceor system,orto affectits safetyor effectiveness.
ST639x DATASHEET INDEX
Pages
ST6391, ST6392, ST6393
ST6395, ST6397, ST6399.. ......... ....... ... .... ......
1GENERAL DESCRIPTION............ .................... ...... 3
PIN DESCRIPTION .. .. ... .. .. ......... ... .. .. ... .. ......... 5
ST639x CORE............................................ 7
MEMORY SPACES......................................... 10
INTERRUPT... ...... .......... .... ......... ... ....... ... 17
RESET................................................ 21
WAIT& STOP MODES................ .......... ............. 23
ON-CHIP CLOCK OSCILLATOR.................................. 24
INPUT/OUTPUT PORTS...................................... 25
TIMERS............................................... 28
HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION...... ............. 31
SERIAL PERIPHERAL INTERFACE................................. 32
6-BITPWM D/A CONVERTERS................ ............. ...... 41
AFC A/D COMPARATOR...................................... 41
DEDICATED LATCHES................................. ...... 42
ON-SCREEN DISPLAY (OSD)..... ........ ... ....... ............. 43
SOFTWARE DESCRIPTION..... ......... ....... ....... ......... 52
ABSOLUTEMAXIMUM RATINGS.................................. 57
PACKAGE MECHANICAL DATA.................................. 61
ORDERING INFORMATION TABLE..................... ...... ...... 64
8-BIT HCMOS MCUs
FOR TV FREQUENCY SYNTHESIS WITH OSD
ST6391, ST6392, ST6393
ST6395, ST6397, ST63994.5to6V supply operatingrange
8MHz Maximum Clock Frequency
User Program ROM: Upto 20140 bytes
Reserved Test ROM:Upto 340 bytes
Data ROM: User selectable size
Data RAM: 256 bytes
Data EEPROM: Upto 384 bytes
42-Pin Shrink Dualin Line Plastic Packageto 23 software programmable general pur-
pose Inputs/Outputs, including2 direct LED
driving Outputs
Two Timers each includingan 8-bit counter with 7-bit programmable prescaler
Digital Watchdog Function
Serial Peripheral Interface(SPI) supporting
S-BUS/I2C BUS and standard serial protocols
SPIfor external frequency synthesistuningto Six 6-Bit PWM D/A Converters
AFC A/D converter with 0.5V resolution
Five interrupt vectors (IRIN/NMI, Timer1&2,
VSYNC, PWR INT.)
On-chip clock oscillator Linesby15 Characters On-Screen Display
Generator with 128 Characters
All ROM types are supported by pin-to-pin
EPROMand OTPversions.
The development toolof the ST639x microcon-
trollers consistsof the ST638x-EMUemulation
and development systemtobe connected viaa
standard RS232 serial lineto an MS-DOS Per-
sonal Computer.
(Ordering Informationat the endof the datasheet)
PSDIP42
PRELIMINARY DATA
DEVICE ROM(Bytes)
EEPROM(Bytes)
ST6391 16K 128
ST6392 20K 128
ST6393 16K 128
ST6395 20K 384
ST6397 20K 384
ST6399 16K 128
DEVICE SUMMARY
PC0 (SCL)
PB2
PB1
DA5DA4
DA3 4 22
PA7
RESET
OSCin
OSCout
PA5
PA6
TEST
OSDOSCin
OSDOSCout29
PC7
VA00339SS
DA0
PC1 (SDA)40DA2
DA1
VDD
PC2
PC3 (SEN)
PC4
PC5
PC6 (IRIN)
VSYNC
HSYNC
BLANK
PA4
PA3
PA2
PA0
PA1
AFC
PB4
PB5
PB6
Figure1. ST6393/97 Pin ConfigurationPC0 (SCL)
PB2
PB1
PB062.5kHz OUT
DA3 4 22
PA7 (HD1)
RESET
OSCin
OSCout
PA5
PA6 (HD0)
TEST
OSDOSCin
OSDOSCout29
PC7
VA00340SS
DA0
PC1 (SDA)40DA2
DA1
VDD
PC2
PC3 (SEN)
PC4 (PWRIN)
PC5
PC6 (IRIN)
VSYNC
HSYNC
BLANK
PA4
PA3
PA2
PA0
PA1
PB3
PB4
PB5
PB6
Figure2. ST6392/99 Pin ConfigurationPC0 (SCL)
PB2
PB1
PB0DA4
DA3 4 22
PA7 (HD1)
RESET
OSCin
OSCout
PA5
PA6 (HD0)
TEST
OSDOSCin
OSDOSCout29
PC7
VA00337SS
DA0
PC1 (SDA)40DA2
DA1
VDD
PC2
PC3 (SEN)
PC4 (PWRIN)
PC5
PC6 (IRIN)
VSYNC
HSYNC
BLANK
PA4
PA3
PA2
PA0
PA1
PB3
PB4
PB5
PB6
(1)
Figure3. ST6391/95 Pin Configuration
Note 1.ST6395 only
ST6391,92,93,95 ,97,99
GENERAL DESCRIPTIONThe ST639x microcontrollers are membersof the8-
bit HCMOS ST638x family,a seriesof devices spe-
cially orientedto TVapplications.Different ROM size
and peripheral configurations are availableto give
the maximum application and cost flexibility. All
ST639x members are basedona building blockap-
proach:a common coreis surroundedbya combina-
tionof on-chip peripherals (macrocells) available
froma standard library. These peripherals are de-
signed with the same Core technology providing full
compatibility and short design time. Manyof these
macrocells are specially dedicatedto TV applica-
tions.The macrocellsof the ST639x family are: two
Timer peripherals each including an 8-bit counter
witha 7-bit software programmable prescaler
(Timer),a digital hardware activated watchdog
function (DHWD),a 14-bitvoltage synthesis tuning
peripheral,a Serial Peripheral Interface (SPI),up six 6-bit PWM D/A converters,an AFC A/D con-
verter with 0.5V resolution, an on-screen display
(OSD) with15 characters per line and 128 charac-
ters(in two banks eachof64 characters).In addi-
tion the following memory resourcesare available:
program ROM (upto 20K), data RAM (256 bytes),
EEPROM (upto 384 bytes).Referto pin configura-
tions figures andto ST639x device summary (Ta-
ble1) for the definitionof ST639x family members
anda summaryof differences among the different
types.
ST6391,92,93,95,97,99
STACK LEVEL1
STACK LEVEL2
STACK LEVEL3
STACK LEVEL4
STACK LEVEL5
STACK LEVEL6
D/AOutputs
TIMER2
IRINTERRUPT
Input
TEST
TIMER1
PORTC
PORTB
PORTA
AFC Input
ON-SCREEN
DISPLAY
DIGITAL
WATCHDOG/TIMER
SERIAL PERIPHERAL
INTERFACE
VDD VSS OSCin OSCout RESETG,B, BLANK
HSYNC, VSYNC
VR01753G
PA0- PA7*
DA0- DA5
IRIN/PC6
TEST
AFC
PB0- PB7*
PC2, PC4- PC7*
PC0/ SCL
PC1/ SDA
PC3/ SEN
POWER SUPPLY OSCILLATOR RESET
8-BIT COREUSER PROGRAM
ROM TO20 kBytes
DATA ROM
USER SELECTABLE
DATA EEPROM
384 Bytes
DATA RAM
256 Bytes ReferTo Pin Configuration For Additional Information
Figure4. ST6391,92,93,95,97,99Block Diagram
DEVICE ROM(Bytes)
RAM(Bytes)
EEPROM(Bytes)
AFC D/A COLOUR
PINS
LOW
POWERIN
RESET
PWRIN
PIN
SPI
CLKFREQ.
(kHz)
62.5kHz
Pin
EMULATING
DEVICESST6391 16K 256 128 NO 5 3 NO NO 62.5 NO ST63E91
ST6392 20K 256 128 NO 4 3 YES YES 62.5 YES ST63E92
ST6393 16K 256 128 YES 6 3 NO NO 62.5 NO ST63E93
ST6395 20K 256 384 NO 5 3 NO YES 100 NO ST63E95
ST6397 20K 256 384 YES 6 3 NO NO 100 NO ST63E97
ST6399 16K 256 128 NO 4 3 YES YES 62.5 YES ST63E99
Table1. Device Summary
ST6391,92,93,95 ,97,99
PIN DESCRIPTION
VDD and VSS. Poweris suppliedto the MCU using
these twopins. VDDis power and VSS isthe ground
connection.
OSCin, OSCout. These pins are internally con-
nectedto the on-chip oscillator circuit.A quartz
crystalora ceramic resonator can be connected
between these two pinsin orderto allow the cor-
rect operationof the MCU with various stabil-
ity/cost trade-offs. The OSCin pinis the input pin,
the OSCout pinis the output pin.
RESET. The active low RESET pinis usedto start
the microcontrollerto the beginningofits program.
Additionally the quartz crystal oscillator willbe dis-
abled when the RESET pinis lowto reducepower
consumption during resetphase (ST6392/99 only).
TEST. The TEST pin mustbe heldat VSSfor nor-
mal operation.
PA0-PA7. These8 lines are organizedas one I/O
port (A). Each line maybe configuredas eitheran
input withor without pull-up resistoror asan output
under software controlof the data direction regis-
ter. Pins PA4to PA7 are configuredas open-drain
outputs (12V drive). On PA4-PA7 pins the input
pull-up optionis not available while PA6 and PA7
have additional current driving capability (25mA,
VOL:1V). PA0to PA3 pins are configuredas push-
pull.
PB0-PB2, PB4-PB6. These6 lines are organized oneI/O port (B).Each line maybe configuredas
either aninput withor without internal pull-up resis-
toror as an output under software controlof the
data direction register.
PC0-PC7. These8 lines are organizedas one I/O
port (C). Each line maybe configuredas eitheran
input withor without internal pull-up resistororas output under software controlof the data direc-
tion register. Pins PC0to PC3 are configuredas
open-drain (5V drive)in output mode while PC4to
PC7 are open-drain with 12V drive and the input
pull-up options does not existon thesefour pins.
PC0, PC1 and PC3 lines whenin output mode are
“ANDed” with the SPI control signals and areall
Open-drain. PC0is connectedtothe SPI clock sig-
nal (SCL), PC1 with the SPI data signal (SDA)
while PC3is connected with SPI enable signal
(SEN, usedin S-BUS protocol).Pin PC4 and PC6
can alsobe inputsto software programmable edge
sensitive latches which can generate interrupts;
PC4 can be connectedto Power Interrupt while
PC6 can be connectedto the IRIN/NMI interrupt
line.
DA0-DA5. These pins are the six PWM D/A out-
putsof the 6-bit on-chip D/A converters. These
lines have open-drain outputs with 12V drive. The
output repetition rateis 31.25KHz (with 8MHz
clock).
AFC. Thisis the inputof the on-chip 10levels com-
parator that can be usedto implement the AFC
function. This pinisan high impedance input able withstand signals witha peak amplitude upto
12V.
OSDOSCin, OSDOSCout. These are the On
Screen Display oscillator terminals. An oscillation
capacitor and coil network haveto beconnectedto
provide the right signalto the OSD.
HSYNC, VSYNC. These are the horizontal and
vertical synchronization pins. The active polarityof
these pinsto the OSD macrocell canbe selected the useras ROM mask option.If the deviceis
specifiedto have negative logic inputs, then these
signals are low the OSD oscillator stops.If the de-
viceis specifiedto have positive logic inputs, then
when these signals are high the OSD oscillator
stops.
G,B, BLANK. Outputs from the OSD.R,G and are the color outputs while BLANKis the blank-
ing output.All outputsare push-pull. The active po-
larityof these pins canbe selectedby the useras
ROM mask option.
62.5kHz OUT. This pinis available only on the
ST6392/99. The pinisan open drain (12V) output the frequencyof 62.5kHz (withan 8MHz clock).
The pin canbe usedto drive the SGS-THOMSON
TEA5640 Chroma Processor. Refer to the
TEA5640 Data sheetfor more information.
ST6391,92,93,95,97,99
Pin Function DescriptionDA0to DA5 Output, Open-Drain, 12V
AFC Input, High Impedance, 12V
R,G,B, BLANK Output, Push-Pull
HSYNC, VSYNC Input, Pull-up, Schmitt Trigger
OSDOSCin Input, High Impedance
OSDOSCout Output, Push-Pull
TEST Input, Pull-Down
OSCin Input, Resistive Bias, Schmitt Triggerto Reset Logic Only
OSCout Output, Push-Pull
RESET Input, Pull-up, Schmitt Trigger Input
PA0-PA3 I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input
PA4-PA5 I/O, Open-Drain, 12V,No Input Pull-up, Schmitt Trigger Input
PA6-PA7 I/O, Open-Drain, 12V,No Input Pull-up, Schmitt Trigger Input, High Drive
PB0-PB6 I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input
PC0-PC3 I/O, Open-Drain,5V, SoftwareInput Pull-up, Schmitt Trigger Input
PC4-PC7 I/O, Open-Drain, 12V,No Input Pull-up, Schmitt Trigger Input
VDD,VSS Power Supply Pins
62.5kHz OUT Output, Open-Drain 12V
Table2. Pin Summary
ST6391,92,93,95 ,97,99
ST639x COREThe Coreofthe ST639xFamily isimplementedinde-
pendently from the I/Oor memory configuration.
Consequently,it canbe treatedasan independent
centralprocessorcommunicating with I/Oand mem-
oryvia internaladdresses,data,and control busses.
The in-core communicationis arrangedas shown the following block diagram figure; the controller
being externallylinkedto both the reset and the os-
cillator, while the coreis linkedto the dedicatedon-
chip macrocellsperipherals via the serial data bus
and indirectly for interrupt purposes through the
control registers.
RegistersThe ST639x Family Core has five registers and
three pairsof flags availableto the programmer.
They are shownin Figure5 and are explainedin
the following paragraphs together with the pro-
gram anddata memory page registers.
Accumulator (A). The accumulatorisan 8-bit gen-
eral purpose register usedinall arithmetic calcula-
tions, logical operations, and data manipulations.
The accumulatoris addressedin the data spaceas
RAM locationat the FFh address.
Accordingly, the ST639x instruction set can use
the accumulatoras any other registerof the data
space.
Figure5. ST639x Core Block DiagramSHORT
DIRECT
ADDRESSING
MODEV REGISTER REGISTER
PROGRAMCOUNTER
SIXLEVELS
STACKREGISTER
NORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
INDEX
REGISTER
VA000423b11
ACCUMULATOR REG. POINTER REG.POINTER
Figure6. ST639x Core Programming Model
ST6391,92,93,95,97,99
ST639x CORE (Continued)
Indirect Registers (X, Y). These two indirect reg-
isters are usedas pointerstothe memorylocations the data space. They are usedin the register-in-
direct addressing mode.These registers can be
addressedin the data spaceas RAM locationsat
the 80h (X)and 81h (Y) addresses.They can also accessed with the direct, short direct,or bitdi-
rect addressing modes. Accordingly, the ST639x
instruction set can use the indirect registersas any
other registerof the data space.
Short Direct Registers (V, W). These two regis-
ters are usedto save one bytein short direct ad-
dressing mode.These registers canbe addressed the data spaceas RAM locationsat the 82h (V)
and 83h (W) addresses. They can also be ac-
cessed with the direct and bit direct addressing
modes. Accordingly, the ST639x instruction set
can use the short direct registersas any other reg-
isterof the data space.
Program Counter (PC)The program counteris a12-bitregisterthatcontains
the addressof the next ROM locationto be proc-
essedby thecore.This ROMlocation maybe anop-
code,an operand,or an addressof operand. The
12-bit length allows the direct addressingof 4096
bytesin the programspace.Nevertheless,if thepro-
gram space containsmore than 4096 locations,the
further program space can be addressedby using
the Program ROM Page Register. The PC valueis
incremented, afteritis read for the addressof the
currentinstruction,by sendingit through theALU,so
giving the addressof the next bytein the program.
Toexecute relative jumps the PC and the offsetval-
ues are shifted through the ALU, where they willbe
added,andtheresultis shiftedbackinto the PC.The
program counter can be changedin the following
ways: (Jump) instruction.... PC=Jump address
CALL instruction...........PC=Call address
Relative Branch
instructions................... PC=PC+offset
Interrupt........................ PC=Interrupt vector
Reset............................PC=Reset vector
RET& RETI instructions............PC=Pop (stack)
Normal instruction........PC= PC+1
WHEN CALL
INTERRUPT REQUEST
OCCURS
STACK LEVEL1
STACK LEVEL2
STACK LEVEL3
STACK LEVEL4
STACK LEVEL5
STACK LEVEL6
PROGRAM COUNTER
WHEN
RET ORRETI
OCCURS
VA000424
Figure7. Stack Operation
Flags (C,Z)The ST639x Core includes three pairsof flags that
correspondto3 different modes: normal mode,in-
terrupt mode and Non-Maskable-Interrupt-Mode.
Each pair consistsofa CARRY flag anda ZERO
flag. One pair (CN, ZN)is used during normal op-
eration, one pairis used during the interrupt mode
(CI,ZI) and one isused during the not-maskablein-
terrupt mode (CNMI, ZNMI).
The ST639x Core uses the pairof flags that corre-
spondsto the actual mode:as soonasan interrupt
(resp.a Non-Maskable-Interrupt)is generated, the
ST639x Core uses the interrupt flags (resp. the NMI
flags)insteadof the normal flags. When the RETIin-
structionis executed,thenormalflags (resp. the inter-
ruptflags) are restoredif the MCU wasin the normal
mode(resp.intheinterruptmode)beforetheinterrupt.
Should beobservedthateach flagset can onlybe ad-
dressedinits own routine (Not-maskable interrupt,
normal interruptor main routine). The interrupt flags
are not cleared during the context switching and so,
theyremainin the state they wereat the exitof the last
routine switching.
The Carry flagis set whena carryora borrow oc-
curs during arithmetic operations, otherwiseitis
cleared. The Carry flagis also setto the valueof
thebit testedina bit test instruction, and partici-
patesin the rotate left instruction.
The Zero flagis setif the resultof the last arithmetic logical operation was equalto zero, otherwiseit cleared.
The switching between these three setsis auto-
matically performed whenan NMI,an interrupt and RETI instructions occur. As the NMI modeis
automatically selected after the resetof the MCU,
the ST639x Core usesat first the NMI flags.
ST6391,92,93,95 ,97,99
ST639x CORE (Continued)
StackThe ST639x Core includes true LIFO hardware
stack that eliminates the needfora stack pointer.
The stack consistsof six separate 12-bit RAMlo-
cations thatdo not belongto the data space RAM
area. Whena subroutine call (or interruptrequest)
occurs, the contents ofeach levelis shiftedinto the
next level while the contentof the PCis shifted into
the first level (the valueof the sixth level will be
lost). When subroutineor interrupt return occurs
(RETor RETI instructions), the first level registeris
shifted back into the PC and the valueof each level shifted back into the previous level. These two
operating modes are describedin Figure7. Since
the accumulator,asall other data space registers, notstored inthis stack the handlingof thisregis-
ters shallbe performed inside the subroutine. The
stack pointer will remaininits deepest position,if
more than6 callsor interrupts are executed,so
that the last return address will be lost.It will also
remaininits highest positionif the stackis empty
anda RETor RETIis executed.In this case the
next instruction willbe executed.
Memory Registers
The PRPR canbe addressed likea RAM location the Data Spaceat the CAh address; neverthe-
lessitisa write-only register that can notbe ac-
cessed with single-bit operations. This registeris
usedto select the 2-Kbyte ROM bankof the Pro-
gram Space that willbe addressed.The numberof
the page hastobe loadedin the PRPR. ThePRPR not cleared during the MCU initialization and
should thereforebe definedbefore jumping outof
the static page. Referto the Program Space de-
scription for additional information concerning the
useof this register. The PRPRis not modified
whenan interruptora subroutine occurs.
PRPR
Program ROMPage Register
(CAh, Write Only)D6 D5D4 D3D2 D1D0
Figure8. Program ROM Page Register
DRBR
Data RAM Bank Register
(E8h, Write Only)D6 D5D4D3 D2D1 D0
Figure9. Data RAM Bank Register
DRWR
Data ROM Window Register
(C9h, Write Only)D6 D5D4D3 D2D1 D0
Figure 10. Data ROM Window Register
The DRBR canbe addressed likea RAM location the Data Spaceat the E8h address, neverthe-
lessitis write-only register that can not be ac-
cessed with single-bit operations. This registeris
usedto select the desired 64-byte RAM/EEPROM
bankof the Data Space. The numberof the bank
hastobe loadedin the DRBR and the instruction
hasto point tothe selected locationasit wasin the bank (from 00h addressto 3Fh address). This
registeris undefined afterReset. Referto the Data
Space description for additional information. The
DRBR registeris not modified whena interruptora
subroutine occurs.
The DRWR registercan beaddressedlikea RAMlo-
cationin the Data Spaceat the C9h address, never-
thelessitis write-only register that can not be
accessed with single-bit operations. This registeris
usedto moveup and down the 64-byte read-only
datawindow (from the 40h addressto 7Fh address the Data Space) along the ROMof the MCUby
stepof64 bytes. The effectiveaddressof the byteto readasa data inthe ROMis obtainedbythe con-
catenationof the6 less significant bitsofthe address
givenin the instruction (as less significant bits) and
the contentof the DRWR (as most significantbits).
Referto the DataSpace description foradditionalin-
formation.
ST6391,92,93,95,97,99
MEMORY SPACESThe MCUs operatein three different memory
spaces: Stack Space, Program Space, and Data
Space.A descriptionof these spacesis shownin
Figure 11.
Stack SpaceThe stack space consistsofsix12bit registers that
are usedfor stacking subroutine and interrupt return
addressesplusthe currentprogramcounterregister.
Program SpaceThe program spaceis physically implementedin
the ROM and includesall the instructions that arebe executed,as wellas the data requiredfor the
immediate addressing mode instructions, the re-
served test area and user vectors.Itis addressed
thanksto the 12-bit Program Counter register (PC
register) and so, the ST639x Core can directly ad-
dressupto4K bytesof Program Space. Neverthe-
less, the Program Space can be extendedby the
additionof 2-Kbyte ROM banksasitis shownin
Figure 13in whicha 20K bytes memoryis de-
scribed. These banks are addressed bypointingto
the 000h-7FFh locationsof the Program Space
thanksto the Program Counter, andby writingthe
appropriate codein the Program ROM Page Reg-
ister (PRPR) locatedat the CAh addressof the
Data Space. Becauseinterrupts and common sub-
routines should be availableall the time only the
lower 2K byteof the 4K program space are bank
switched while the upper 2K byte canbe seenas
static space. Table3 gives the different codes that
allows the selectionof the corresponding banks.
Note that, from the memory pointof view, the Page and the StaticPage represent the same physical
memory:itis onlya different wayof addressing the
same location. On the ST6392,95,97,a totalof
2048, bytesof ROM have been implemented;
20140 areavailableas user ROM while 340 arere-
servedfor testing.
PROGRAM SPACE
VR001568
INTERRUPT&
RESET VECTORS ACCUMULATOR
WREGISTER
RAM
DATA ROM
WINDOW
RAM/ EEPROM
BANKING AREA
DATA SPACE
DATA RAM
BANK SELECT
DATA ROM
WINDOW SELECT REGISTER REGISTER REGISTER
0000h
07FFh
0800h
0FF0h
0FFFh
000h
03Fh
040h
070h
080h
081h
082h
083h
084h
0FFh
0C0h
ROM
ROM
STACK LEVEL1
STACK LEVEL2
STACK LEVEL3
STACK LEVEL4
STACK LEVEL5
STACK LEVEL6
PROGRAM COUNTER
STACK SPACE
Figure 11. ST639x Memory Addressing Description DiagramProgram
counter
space
0000h 4FFFh
0FFFh
Static Page
Page1
0800h
07FFh
Page0 Page1StaticPage Page9
0000h
Figure 12. ST639x 20K Bytes Program Space
Addressing Description
ST6391,92,93,95 ,97,99
D7-D5. These bits are not used.
PRPR4-PRPR0. These are the program ROM
banking bits and the value loaded selects the cor-
responding pagetobe addressedin the lower part 4K program address spaceas specifiedin Table This registeris undefinedon reset.
Note. The numberof bits implemented depends the sizeof the ROMof the device. Only the
lower part of address space has been bank-
switched because interrupt vectors and common
subroutines should be availableall the time. The
reasonof this structureis dueto the fact thatitis
not possibleto jump froma dynamic pageto an-
other, unless jumping backto the static page,
changing contentsof PRPR, and, than,jumpingto differentdynamic page.
Careis required when handling the PRPRasitis
write only. For this reason,itis not allowedto
change the PRPR contents while executing inter-
rupts drivers,as the driver cannot save and than
restoreits previous content. Anyway, this opera-
tion maybe necessaryif the sumof common rou-
tines and interrupt drivers will take more than 2K
bytes;in this case couldbe necessaryto divide the
PRPR
Program ROMPage Register
(CAh, Write Only) D6D5D4 D3D2 D1D0
PRPR0
PRPR1
PRPR2
PRPR3
UNUSED
Figure 13. Program ROM Page Register
PRPR3 PRPR2 PRPR1 PRPR0 PC11 Memory
Page XXX 1
Static
Page
(Page1)
000 0 0 Page0
000 1 0
Page1
(Static
Page)
001 0 0 Page2
001 1 0 Page3
010 0 0 Page4
010 1 0 Page5
011 0 0 Page6
011 1 0 Page7
100 0 0 Page8
100 1 0 Page9
Table3. ST639x Program ROM Page Register
Coding
MEMORY SPACES (Continued)
interrupt driverina (minor) partin the static page
(start and end), andin the second (major) partin
one dynamic page.Ifitis impossibleto avoid the
writingof this registerin interrupts drivers,an im-
ageof this register mustbe savedina RAM loca-
tion, and each time the program writes the PRPRit
writes also the image register. The image register
mustbe written first,soifan interrupt occurs be-
tween the two instructions the PRPRis not af-
fected.
ST6391,92,93,95,97,99
ROM Page Device Address DescriptionPAGE0 0000h-007Fh
0080h-07FFh
Reserved
User ROM
PAGE1
“STATIC”
0800h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
User ROM
Reserved
Interrupt Vectors
Reserved
NMI Vector
Reset Vector
PAGE2 0000h-000Fh
0010h-07FFh
Reserved
User ROM
PAGE3 0000h-000Fh
0010h-07FFh
Reserved
User ROM
PAGE4 0000h-000Fh
0010h-07FFh
Reserved
User ROM
PAGE5 0000h-000Fh
0010h-07FFh
Reserved
User ROM
PAGE6 0000h-000Fh
0010h-07FFh
Reserved
User ROM
PAGE7 0000h-000Fh
0010h-07FFh
Reserved
User ROM(Endof 16KST6391,93,99)
PAGE8 0000h-000Fh
0010h-07FFh
Reserved
User ROM
PAGE9 0000h-000Fh
0010h-07FFh
Reserved
User ROM(Endof 20KST6392,95,97)
Table4. ST639x Program ROM Map (upto 20K Bytes)
MEMORY SPACES (Continued)
ST6391,92,93,95 ,97,99
b0000h
DATA RAM/EEPROM/OSD
BANK AREA
03Fh
040h
DATA ROM
WINDOW AREA
07Fh REGISTER 080h REGISTER 081h REGISTER 082h REGISTER 083h
084h
DATA RAM
0BFh
PORT ADATA REGISTER 0C0h
PORT BDATA REGISTER 0C1h
PORTC DATA REGISTER 0C2h
RESERVED 0C3h
PORT ADIRECTION REGISTER 0C4h
PORT BDIRECTION REGISTER 0C5h
PORT CDIRECTION REGISTER 0C6h
RESERVED 0C7h
INTERRUPT OPTION REGISTER 0C8h
DATA ROM WINDOW REGISTER 0C9h
PROGRAM ROMPAGE REGISTER 0CAh
RESERVED 0CBh
SPIDATA REGISTER 0CCh
0CDh
RESERVED
0D1h
TIMER 1PRESCALERREGISTER 0D2h
TIMER 1COUNTER REGISTER 0D3h
TIMER1 STATUS/CONTROL REG. 0D4h
0D5h
RESERVED
0D7h
WATCHDOG REGISTER 0D8h
Figure 14. ST639x Data Space b0
RESERVED 0D9h
TIMER 2PRESCALER REGISTER 0DAh
TIMER2 COUNTER REGISTER 0DBh
TIMER 2STATUS CONTROL REG. 0DCh
0DDh
RESERVED
0DFh
DA0 DATA/CONTROL REGISTER 0E0h
DA1 DATA/CONTROL REGISTER 0E1h
DA2 DATA/CONTROL REGISTER 0E2h
DA3 DATA/CONTROL REGISTER 0E3h
AFC,IR& OSD RESULT REGISTER 0E4h
OUTPUTS CONTROL REGISTER 0E5h
DA4 DATA/CONTROL REGISTER 0E6h
DA5 DATA/CONTROL REGISTER 0E7h
DATA RAMBANK REGISTER 0E8h
DEDIC. LATCHES CONTROL REG. 0E9h
EEPROMCONTROLREGISTER 0EAh
SPICONTROL REGISTER1 0EBh
SPICONTROL REGISTER2 0ECh
OSD CHARAC. BANK SELECT REG. 0EDh
0F0h
RESERVED
0FEh
ACCUMULATOR 0FFh
OSD CONTROL REGISTERSLOCATED PAGE6 OFBANKEDDATA RAM
VERTICALSTART ADDRESS REG. 010h
HORIZONTALSTARTADDRESSREG. 011h
VERTICAL SPACEREGISTER 012h
HORIZONTAL SPACEREGISTER 013h
BACKGROUND COLOUR REGISTER 014h
GLOBAL ENABLEREGISTER 017h
Figure 15. ST639x Data Space (Continued)
MEMORY SPACES (Continued)
Data SpaceThe instruction setof the ST639x Core oper-
ates ona specific space, named Data Space
that contains all the data necessary for the
processingof the program. The Data Spaceal-
lows the addressingof RAM (256 bytes for the
ST639x family), EEPROM (up to 384 bytes),
ST639x Core/peripheralregisters, andread-only
data such asconstantsand thelook-up tables.
ST6391,92,93,95,97,99
MEMORY SPACES (Continued)
Data ROM Addressing.All the read-only data are
physically implementedin the ROMin which the Pro-
gram Spaceis also implemented.The ROMtherefore
containstheprogramto beexecutedandalsothecon-
stantsandthe look-up tablesneededfor the program.
The locationsofDataSpaceinwhichthedifferentcon-
stants and look-up tables are addressed by the
ST639x Core canbe consideredas beinga 64-byte
window throughwhichitis possibleto accessto the
read-onlydata storedin the ROM. This windowislo-
catedfrom the40haddressto the7Fh addressin the
Data space andallows thedirect readingofthe bytes
from the 000h addressto the 03Fh addressin the
ROM.All the bytes ofthe ROMcanbe usedto store
either instructions orread-onlydata. Indeed,the win-
dow can bemovedbystepof 64bytesalongthe ROM writing the appropriate codein the Write-only Data
ROMWindowregister (DRWR, location C9h). Theef-
fective addressof the bytetobe readasa datain the
ROMis obtainedby the concatenationof the6 less
significant bitsof the addressin the Data Space (as
less significant bits) and the contentof the DRWR (as
most significant bits). So when addressing location
40hof data space,and0is loadedin the DRWR, the
physical addressed locationin ROM is00h.
Note. The data ROM window cannot addresswin-
dows above the 16k byte range.
DWR
Data ROMWindow Register
(C9h, Write Only) D6D5D4 D3D2 D1D0
DWR0 =Data ROMWindow0
DWR1 =Data ROMWindow1
DWR2 =Data ROMWindow2
DWR3 =Data ROMWindow3
DWR4 =Data ROMWindow4
DWR5 =Data ROMWindow5
DWR6 =Data ROMWindow6
DWR7 =Data ROMWindow7
Figure 16. Data ROM Window RegisterDATA ROM
WINDOW REGISTER
CONTENTS
DATA SPACE ADDRESS
40h-7Fh INSTRUCTION
PROGRAM SPACEADDRESS
65432 0
543 210
543 210
READ17891011
VR01573B
DATA SPACE ADDRESS
59h000 1 00 11
Example:
(DWR)
DWR=28h00 00 00001ROM
ADDRESS:A19h 11 1
Figure 17. Data ROM Window Memory Addressing
DWR7-DWR0. These are the Data Rom Window
bits that correspondto the upper bitsof data ROM
program space. This registeris undefined afterre-
set.
Note. Careis required when handlingthe DRWRasis write only. For this reason,itis not allowedto
change the DRWR contents while executing inter-
rupts drivers,as the driver cannot save and thanre-
storeits previous content.Ifitis impossibleto avoid
the writingof thisregisterin interrupts drivers, anim-
ageof thisregister must besavedin aRAM location,
and each time the program writes the DRWRit
writes also the image register. The image register
must be written first,soif an interrupt occurs be-
tweenthe two instructionsthe DRWR registeris not
affected.
ST6391,92,93,95 ,97,99
DRBR
Data RAM
Bank Register
(E8h, Write Only) D6D5D4 D3D2 D1D0
DRBR0
DRBR1
DRBR2
DRBR3
DRBR4
DRBR5
DRBR6
DRBR7
Figure 18. Data RAM Bank Register
MEMORY SPACES (Continued)
Data RAM/EEPROM/OSDRAM Addressingall membersofthe ST639x family64 bytesof data
RAM are directly addressableinthe dataspacefrom
80hto BFh addresses. The additional 192 bytesof
RAM, the 384 bytesof EEPROM, and the OSD
RAM can be addressed using the banksof 64
bytes located between addresses 00h and 3Fh.
The selectionof the bankis doneby programming
the Data RAM Bank Register (DRBR) locatedat
the E8h addressof the Data Space.In this way
each bankof RAM,EEPROMor OSDRAMcan se-
lect64 bytesata time. No more than one bank
shouldbe setata time.
DRBR Value
Selection
Hex. Binary01h 0000 0001 EEPROMPage0
All devices
02h 0000 0010 EEPROMPage1
03h 0000 0011 EEPROMPage2
ST6395and ST6397
ONLY
81h 1000 0001 EEPROMPage3
82h 1000 0010 EEPROMPage4
83h 1000 0011 EEPROMPage5
04h 0000 0100 RAM Page2
All devices
08h 0000 1000 RAM Page3
10h 0001 0000 RAM Page4
20h 0010 0000 OSD Page5
40h 0100 0000 OSD Page6
Table5. Data RAM Bank Register Set-up
DRBR7,DRBR1,DRBR0. These bits select the
EEPROM pages.
DRBR6, DRBR5.Eachof these bits, when set, will
select one OSD RAM register page.
DRBR4,DRBR3,DRBR2.Each ofthese bits, when
set, will select one RAM page.
This registeris undefined afterreset.
Table5 summarizes howto set the Data RAM
Bank Registerin orderto select the various banks pages.
Note:Careis required when handling the DRBRasitis
write only. For this reason,itis not allowedto
change the DRBR contents while executing inter-
rupts drivers,as the driver cannot save and than
restoreits previous content.Ifitis impossibleto
avoid the writingof this registerin interrupts driv-
ers,an imageof this register mustbe savedina
RAM location, and each time the program writes
the DRBRit writes also the image register.
The image register mustbe written first,soifanin-
terrupt occurs between the two instructions the
DRBRis not affected.
ST6391,92,93,95,97,99
MEMORY SPACES (Continued)
EECR
EEPROM Control Register
(EAh, Read/Write) D6D5D4 D3D2 D1D0= EEPROMEnableBit =EEPROM BusyBit =ParallelMode EnableBit =ParallelStartBit
Reserved(Mustbeset Low)
Reserved(Mustbeset Low) =Stand-byEnableBit
Unused
Figure 19. EEPROM Control Register
EEPROM DescriptionThe data spaceof ST639x family from 00hto 3Fh paged as describedin Table5. 384 bytesof
EEPROM locatedin six pagesof64 bytes (pages
0,1,2,3,4 and5, see Table5).
Through the programmingof the Data RAM Bank
Register (DRBR=E8h) the user can select the
bankor page leaving unaffected the wayto ad-
dress the static registers. The wayto address the
“dynamic” pageisto set the DRBRas describedin
Table 5(e.g.to select EEPROM page0, the DRBR
hasto be loaded with content 01h, see Data
RAM/EEPROM/OSD RAM addressing for addi-
tional information).Bits0,1 and7of the DRBR are
dedicatedto the EEPROM.
The EEPROM pagesdo not require dedicatedin-
structionstobe accessedin readingor writing. The
EEPROMis controlled by the EEPROM Control
Register (EECR=EAh). Any EEPROM location can readjust like any other data location,alsoin terms access time. write an EEPROM location takes an average
timeof5 ms (10ms max) and during this time the
EEPROMis not accessibleby the Core.A busy
flag canbe readby the Coreto know the EEPROM
status before trying any access.In writing the
EEPROM can workin two modes: Byte Mode
(BMODE) and Parallel Mode (PMODE). The
BMODEis the normal wayto use the EEPROM
and consistsin accessing one byteata time. The
PMODE consistsin accessing8 bytes per time.
D7. Not used
SB. WRITE ONLY.If thisbitis set the EEPROMis
disabled (any access will bemeaningless)and the
power consumptionof the EEPROMis reducedto
the leakage values.
D5, D4. Reserved for testingpurposes, they must setto zero.
PS. SETONLY. Oncein Parallel Mode,as soonas
the usersoftware sets the PSbit the parallelwriting the8 adjacent registers will start. PSis internally
resetat the endof the programming procedure.
Note that less than8 bytes can be written; after
parallel programming the remaining undefined
bytes will haveno particular content.
PE. WRITE ONLY. Thisbit must be set by the
user programin orderto performparallel program-
ming (more bytes per time).If PEis set and the
“parallelstart bit” (PS)is low,upto8 adjacent bytes
canbe writtenat the maximum speed, the content
being storedin volatile registers. These8 adjacent
bytes can be consideredas row, whose A7, A6,
A5, A4, A3 are fixed while A2, A1 and A0 are the
changing bytes. PEis automatically resetat the
endof any parallel programming procedure. PE
can be resetby the user software before starting
the programming procedure, leaving unchanged
the EEPROM registers.
BS. READ ONLY. This bitwillbe automatically set the CORE when the user program modifiesan
EEPROMregister. The user program hasto testit
before any reador write EEPROM operation; any
attemptto access the EEPROM while “busy bit”is
set willbe aborted and the writing procedurein pro-
gress completed.
EN. WRITE ONLY. Thisbit MUSTbe setto onein
orderto write any EEPROM register.If the user
program will attemptto write the EEPROM when
EN= “0” the involved registers will be unaffected
and the “busy bit”will notbe set.
AfterRESETthecontentof EECRregisterwill be00h.
Notes:When the EEPROMis busy (BS=“1”) the EECR
can notbe accessedin write mode,itis only possi-
bleto read BS status. This implies thatas longas
the EEPROMis busyitis not possibleto change
the statusof the EEPROMcontrol register. EECR
bits4 and5 are reserved for test purposes, and
must neverbe setto “1”.
ST6391,92,93,95 ,97,99
MEMORY SPACES (Continued)
INTERRUPTThe ST639x Core can manage4 different mask-
able interrupt sources, plus one non-maskablein-
terrupt source (top priority level interrupt). Each
source isassociated with aparticular interrupt vec-
tor that containsa Jump instructionto the related
interrupt service routine. Each vectoris locatedin
the Program Spaceata particular address (see
Table 6). Whena source providesan interruptre-
quest, and the request processingis also enabled the ST639x Core, then the PC registerisloaded
with the addressof the interrupt vector (i.e.of the
Jump instruction). Finally,the PCis loaded with the
addressof the Jump instruction and the interrupt
routineis processed.
The relationship between vector and source and
the associated priorityis hardware fixedfor the dif-
ferent ST639x devices. For some interrupt sourcesis also possibleto selectby software the kindof
event that will generate the interrupt.
All interrupts canbe disabledby writingto the GEN
bit (global interruptenable)of the interrupt option
register (address C8h). Aftera reset, ST639xisin
non maskable interrupt mode,sono interrupts will accepted and NMI flags will be used, untila
RETI instructionis executed.Ifan interruptis exe-
cuted, one special cycleis madeby the core, dur-
ing that the PCis setto the related interrupt vector
address.A jump instructionat this address hasto
redirect program executionto the beginningof the
related interruptroutine. The interrupt detectingcy-
cle, also resets the related interrupt flag (not avail-
ableto the user),so that another interrupt canbe
storedfor this current vector, whileits driveris un-
der execution. additionalinterruptsarrive fromthe samesource,
they will be lost. NMI can interrupt other interrupt
routinesat any time, while other interrupts cannot
interrupt each other.If more than one interruptis
waiting for service, they are executed accordingto
their priority. The lower the number, the higher the
priority. Priorityis, therefore, fixed. Interrupts are
checked during the last cycleof an instruction
(RETI included). Level sensitive interrupts haveto valid during this period.
Additional Notes on Parallel Mode.If the user
wantsto performa parallel programming the first
action shouldbe theset toone the PE bit; from this
moment the first time the EEPROM will be ad-
dressedin writing, the ROW address will be
latched andit willbe possibleto changeit onlyat
the endof the programming procedureorby reset-
ting PE without programming the EEPROM. After
the ROW address latching the Core can “see” just
one EEPROM row (the selected one) and anyat-
temptto writeor read other rows will produce er-
rors. Do not read the EEPROM while PEis set. soon asPEbitis set,the 8volatile ROW latches
are cleared. From this moment the user can load
datain the whole ROWor justina subset. PS set-
ting willmodify the EEPROM registerscorrespond-
ingto the ROW latches accessed after PE. For
example,if the software sets PE and accesses
EEPROMin writingat addresses18h,1Ah,1Bhand
then setsPS, thesethreeregisterswillbe modifiedat
the same time; the remaining bytes will haveno par-
ticular content.Note thatPEis internally resetat the
endof the programming procedure.Thisimpliesthat
the user must set PEbit between two parallel pro-
gramming procedures. Anyway theusercan set and
then resetPE without performing any EEPROMpro-
gramming. PSisa set onlybit andis internally reset the endof the programming procedure. Note that the usertriesto set PS while PEis not setthere will
notbe any programming procedure and the PSbit
willbe unaffected. ConsequentlyPSbit can notbe
setif ENis low. PScanbe affectedby the usersetif,
and onlyif, EN and PE bits are also setto one.
ST6391,92,93,95,97,99
Interrupt Vectors/SourcesThe ST639x Core includes5 different interrupt
vectorsin orderto branchto5 different interrupt
routines. The interrupt vectors are locatedin the
fixed (or static) pageof the Program Space.
The interrupt vectorassociatedwith the non-mask-
able interrupt sourceis named interrupt vector #0.is locatedat the (FFCh,FFDh) addressesin the
Program Space. This vectoris associated with the
PC6/IRIN pin.
The interrupt vectors located at addresses
(FF6h,FF7h), (FF4h,FF5h), (FF2h,FF3h),
(FF0h,FF1h) are named interrupt vectors #1, #2, and#4 respectively.These vectors are associ-
ated with TIMER2 (#1), VSYNC (#2), TIMER1
(#3) andPC4(PWRIN) (#4).
Interrupt PriorityThe non-maskable interrupt request has the high-
est priority and can interrupt any other interrupt
routinesat any time, nevertheless the other inter-
rupts cannot interrupt each other.If more than one
interrupt requestis pending, they are processedby
the ST639x Core accordingto their priority level:
vector#1 has the higher priority while vector#4 the
lower. The priorityof each interrupt sourceis hard-
ware fixed.
Interrupt Option RegisterThe Interrupt Option Register (IOR register, loca-
tion C8h)is usedto enable/disable the individual
interrupt sources andto select the operating mode theexternal interrupt inputs.This register canbe
addressedin the Data Spaceas RAM locationat
the C8h address, neverthelessitis write-only reg-
ister that can not be accessed with single-bit op-
erations. The operating modesof the external
interrupt inputs associatedto interrupt vectors #1
and #2are selectedthrough bits4 and5of the IOR
register.
D7. Not used.
EL1. Thisis the Edge/Level selectionbitof inter-
rupt #1. When setto one,the interruptis generated low levelof the related signal; when clearedto
zero, the interruptisgeneratedon falling edge.The
bitis clearedto zero after reset.
ES2. Thisis the edge selectionbiton interrupt #2.
Thisbitis used onthe ST639x devices with on-chip
OSD generatorfor VSYNC detection.
GEN. Thisis theglobalenablebit.Whensetto oneall
interruptsare globally enabled;whenthis bitis cleared zeroall interruptsare disabled(excludingNMI).
- D0. These bits are not used.
Interrupt Source Associated
Vector Vector Address
PC6/IRIN
Pin
(1) Interrupt
Vector#0 (NMI) 0FFCh-0FFDh
Timer2 Interrupt
Vector#1 0FF6h-0FF7h
Vsync Interrupt
Vector#2 0FF4h-0FF5h
Timer1 Interrupt
Vector#3 0FF2h-0FF3h
PC4/PWRIN Interrupt
Vector#4 0FF0h-0FF1h
Note 1.This pinisassociated withtheNMI Interrupt Vector
Table6. Interrupt Vectors/Sources
Relationships
INTERRUPT (Continued)
IOR
InterruptOption Register
(C8h, Write Only) D6D5D4 D3D2 D1D0
Unused
GEN =GlobalEnableBit
ES2= EdgeSelectionBit
EL1 =EdgeLevel SelectionBit
Unused
Figure 20. InterruptOption Register
ST6391,92,93,95 ,97,99
Interrupt ProcedureThe interrupt procedureis very similartoa call pro-
cedure; the user can consider the interruptas an
asynchronous call procedure. As thisis an asyn-
chronous event the user does not know about the
context and the timeat whichit occurred.Asa re-
sult the user should saveall the data space regis-
ters which willbe used inside theinterrupt routines.
There are separate setsof processor flagsfor nor-
mal, interrupt and non-maskable interrupt modes
which are automatically switched andso thesedo
not needtobe saved.
The followinglist summarizes the interrupt proce-
dure (refer alsoto Figure 21. Interrupt Processing
Flow Chart): Interrupt detection The flagsC andZof the main routine are ex-
changed with the flagsC andZof the interrupt
routine (resp. the NMI flags) The valueof the PCis storedin the first levelof
the stack- The normal interrupt lines are inhib-
ited (NMIstill active) The edgeflip-flopis reset The related interrupt vectoris loadedin the PC. User selected registers are saved inside thein-
terrupt service routine (normally ona software
stack) The sourceof the interruptis found by polling
(if more than one sourceis associatedto the
same vector) Interrupt servicing Return from interrupt (RETI) Automatically the ST639x core switches back the normal flags (resp the interrupt flags)
and pops the previous PC value from the stack
The interrupt routine begins usuallyby the identifi-
cationof the device that has generated the inter-
rupt request. The user should save the registers
which are used inside the interrupt routine (that
holds relevantdata) intoa software stack.
After the RETI instruction execution, the Core car-
ries out the previous actions and the main routine
can continue.
ST639x Interrupt Details Interrupt (#0). The IRIN/PC6 Interruptis con-
nectedto the first interrupt#0 (NMI, 0FFCh).If the
IRINT interruptis disabledat the Latch circuitry,
thenit willbe high. The#0 interrupt input detectsa
highto low level. Note that once #0 has been
latched, then the only wayto remove the latched signalisto service theinterrupt.#0 can interrupt
the other interrupts.A simple latchis provided from
the PC6(IRIN) pinin orderto generate the IRINT
signal. This latch can be triggered by either the
positiveor negative edgeof IRIN signal. IRINTis
inverted with respectto the latch. The latch canbe
read bysoftware and resetby software.
INTERRUPT (Continued)
LOADPC FROM
INTERRUPT VECTORFFC/FFD)
SET
INTERRUPT MASK
PUSH THE INTOTHE STACK
SELECT
INTERNAL MODE FLAG
CHECKIF THEREIS INTERRUPT REQUEST
AND INTERRUPT MASK
INSTRUCTION
WAS
THE INSTRUCTION
ARETITHE CORE
ALREADYIN
NORMAL MODE
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
CLEAR
INTERRUPT MASK
SELECT
PROGRAM FLAGSPOP”
THE STACKEDPC
YES
YES
YES
VA000014
Figure 21. InterruptProcessing Flow-Chart
ST6391,92,93,95,97,99
INTERRUPT (Continued)
TIMER2 Interrupt (#1). The TIMER2 Interruptis
connectedto the interrupt#1 (0FF6h). The TIMER2
interruptgeneratesa low level(whichis latchedin the
timer). Only thelow level selectionfor#1can beused.
Bit6 ofthe interruptoptionregister C8h hastobe set.
VSYNC Interrupt (#2). The VSYNC Interruptis
connectedto the interrupt #2. When disabled the
VSYNC INTsignalis low. The VSYNCINT signalis
inverted with respectto the signal appliedto the
VSYNC pin. Bit5of the interrupt option register
C8his usedto select the negative edge (ES2=0)or
the positive edge (ES2=1); the edge will depend the application. Note that once an edge has
been latched, then the only wayto remove the
latched signalisto service the interrupt.Care must taken notto generate spurious interrupts. This
interrupt may be used for synchronizeto the
VSYNC signalin orderto change charactersin the
OSD only when the screenison vertical blanking
(if desired). This method may alsobe usedto blink
characters.
TIMER1 Interrupt (#3). The TIMER1 Interruptis
connectedto the fourth interrupt#3 (0FF2h) which
detectsa low level (latchedin the timer).
PWR Interrupt (#4). The PWR Interruptis con-
nectedto the fifth interrupt #4 (0FF0h).If the
PWRINTis disabledat the PWR circuitry, thenit
will be high. The #4 interrupt input detectsa low
level.A simple latchis provided from the PC4
(PWRIN)pinin orderto generate the PWRINT sig-
nal. This latch canbe triggeredby either the posi-
tive or negative edge of the PWRIN signal.
PWRINTis inverted with respectto the latch. The
latch canbe resetby software.
Notes Global disable does not reset edge sensi-
tive interruptflags. These edge sensitive interrupts
become pending again when global disablingisre-
leased. Moreover, edge sensitive interrupts are
storedin the related flags also when interrupts are
globally disabled, unless eachedge sensitive inter-
ruptis also individually disabled before the inter-
rupting event happens. Global disableis doneby
clearing the GEN bitof Interrupt option register,
while any individual disableis donein the control
registerof the peripheral. The on-chip Timer pe-
ripherals havean interruptrequestflagbit (TMZ), this
bitis setto onewhen thedevice wants togeneratean
interruptrequestand amask bit(ETI) that mustbe set oneto allowthe transferof theflagbitto the Core.
ST6391,92,93,95 ,97,99
VA000200 ST6 RESET
ST6
INTERNAL RESET
OSCILLATOR
SIGNAL
WATCHDOG RESET
VDD
300k
RESET
(ACTIVE LOW)
COUNTER
1.0k
Figure 22. Internal Reset Circuit
RESETThe ST639xdevices canbe resetintwoways:by the
external reset input (RESET) tied low and by the
hardwareactivated digital watchdogperipheral.
RESET InputThe external activelow reset pinis usedto reset the
ST638x devices and provide an orderly software
startup procedure. The activationof the Reset pin
may occurat any timein the RUNor WAIT mode.
Even short pulsesat the reset pin willbe accepted
since the reset signalis latchedinternallyandis only
cleared after 2048 clocksat the oscillator pin. The
clocks from theoscillator pinto the reset circuitry are
bufferedbya schmitt triggerso thatan oscillatorin
start-up conditions will not give spurious clocks.
Whenthereset pinis held low, the external crystal os-
cillatoris also disabledin orderto reduce current con-
sumption.The MCUis configuredin the Reset mode longas the signalof the RESET pinis low. The
processingoftheprogramis stoppedandthestandard
Input/Outputports(portA,port Band portC) arein the
input state.As soonas the levelon the reset pin be-
comes high, the initialization sequenceis executed.
RefertotheMCU initialization sequencefor additional
information.
Watchdog ResetThe ST639x devices are provided withan on-chip
hardware activated digital watchdog functioninor-
derto providea graceful recovery froma software
upset.If the watchdog registeris notrefreshed and
the end-of-countis reached, then the reset state
willbe latched into the MCU andan internal circuit
pulls down the reset pin. This also resets the
watchdog which subsequently turns off the pull-
down and activates the pull-up deviceat the reset
pin. This causes the positive transitionat the reset
pin. The MCU will then exit the reset state after
2048 clockson the oscillator pin.
Application Notes external resistor between VDD and the reset pin not required becausean internal pull-up device provided.The user may preferto addan external
pull-up resistor. internal Power-on device does not guarantee
that the MCU will exit the reset state when VDDis
above 4.5V and therefore the RESET pin should externally controlled.
ST6391,92,93,95,97,99
RESET RESET
STILL PRESENT
YES
VA000427
NMI MASK SET
INT LATCH CLEAREDIF PRESENT)
SELECT
NMI MODE FLAGS
PUT FFEh ADDRESS BUS
LOADPC
FROM RESET LOCATIONS
FFE/FFF
FETCH INSTRUCTION
Figure 23. Reset& Interrupt Processing
Flow-ChartRESET VECTOR
INITIALIZATION
ROUTINE
JP:2 BYTES/4 CYCLES
RETI: 1BYTES/2 CYCLESRETI
VA000181
RESET
Figure 24. Restart Initialization Program
Flow-Chart
MCU Initialization SequenceWhena reset occurs the stackis resetto program
counter, the PCis loaded with the addressof the
reset vector (locatedin the program ROMat ad-
dresses FFEh& FFFh).A jump instructionto the
beginningof the program hasto be written into
these locations. Aftera reset the interrupt maskis
automatically activatedso that the Coreisin non-
maskable interrupt modeto prevent falseor ghost
interrupts during the restart phase. Therefore the
restart routine shouldbe terminatedbya RETIin-
structionto switchto normal mode and enablein-
terrupts.If no pending interruptis presentat the
endof the reset routine, the ST639x will continue
with the instruction after the RETI; otherwise the
pendinginterrupt willbe serviced.
RESET Low Power Mode
(ST6392 and ST6399 only)When the reset pinis low, the quartz oscillatoris
Disabled allowing reduced current consumption.
When the reset pinis raised the quartz oscillatoris
enabled and oscillations will startto build up.The
internal reset circuitry will count 2048 clockson the
oscillator pin before allowing the MCUtogo outof
the reset state;the clocks are aftera schmitt trigger that falseor multiple counts are not possible.
RESET (Continued)
ST6391,92,93,95 ,97,99
WAIT& STOPMODESThe STOP and WAIT modes have been imple-
mentedin the ST639x Corein orderto reduce the
consumptionof the device when the latter hasno
instructionto execute. These two modes are de-
scribedin the following paragraphs.On ST639xas
the hardware activateddigital watchdog functionis
present the STOP instructionis de-activated and
any attemptto executeit will cause the automatic
executionofa WAIT instruction.
WAIT ModeThe configurationof the MCUin theWAIT mode oc-
cursas soonas the WAIT instructionis executed.
The microcontroller can alsobe consideredas beinga “software frozen” state where the Core stops
processing the instructionsof the routine, the con-
tentsof the RAM locations and peripheral registers
are savedas longas the power supply voltageis
higherthan the RAM retention voltage but wherethe
peripheralsarestill working.
The WAIT modeis used when the user wantstore-
duce theconsumptionof the MCU whenitisin idle,
while not losing countof timeor monitoringof exter-
nal events. The oscillatoris not stoppedin orderto
provide clock signalto the peripherals. The timers
counting may be enabled (writing the PSI bitin
TSCR register) and the timer interrupt maybe also
enabledbefore enteringthe WAIT mode; this allows
the WAIT modeto be left when timer interrupt oc-
curs.If the exit from the WAIT modeis performed
witha general RESET (either from the activationof
the external pinorby watchdogreset) the MCU will
entera normal reset procedureas describedin the
RESET chapter.Ifan interruptis generated during
WAIT mode the MCU behaviour dependson the
stateof the ST639x Core before theinitializationof
the WAIT sequence, but alsoof the kindof thein-
terrupt request thatis generated. This case willbe
describedin thefollowingparagraphs.In any case,
the ST639x Core does not generate any delay af-
ter the occurrenceof the interrupt because the os-
cillator clockis still available.
STOP Mode ST639x the hardware watchdogis present and
the STOP instruction has been de-activated. Any
attemptto executea STOP will cause the automat- executionofa WAIT instruction.
Exit from WAIT ModeThe following paragraphs describe the output pro-
cedure ofthe ST639x Core from WAITmode when interruptoccurs. Itmustbe noted that therestart
sequence depends on the original stateof the
MCU (normal, interruptor non-maskableinterrupt
mode) before the startof the WAIT sequence, but
alsoof the typeof the interrupt request thatis gen-
erated.Inall casesthe GENbitof IOR hastobe set1in orderto restart from WAIT mode. Contrary the operationof NMIin the RUN mode, the NMI maskedin WAIT modeif GEN=0.
Normal Mode.If the ST639x Core wasin the main
routinewhenthe WAIT instructionhasbeenexecuted,
theST6398xCoreoutputsfromthewait mode assoon
asany interrupt occurs; the relatedinterrupt routineis
executedand atthe endoftheinterruptservice routine
theinstructionthat followsthe WAIT instructionis exe-
cutedif nootherinterruptsare pending.
Non-maskable Interrupt Mode.If the WAIT in-
struction has been executed during the execution the non-maskable interrupt routine, the ST639x
Core outputs from the wait modeas soonas any
interrupt occurs: the instruction that follows the
WAIT instructionis executed and the ST639x Core stillin the non-maskable interrupt mode evenif
another interrupt has been generated.
Normal Interrupt Mode.If the ST639x Core was the interrupt mode before the initializationof the
WAIT sequence,it outputs from the wait modeas
soon as any interrupt occurs. Nevertheless, two
cases havetobe considered: If the interruptisa normal interrupt, the inter-
rupt routinein whichthe WAITwas entered will completed with the executionof the instruc-
tion that follows the WAIT and the ST639x
Coreis stillin the interrupt mode.At the endof
this routine pending interrupts will be serviced accordanceto their priority. If the interruptisa non-maskable interrupt, the
non-maskable routineis processedat first.
Then, the routinein which the WAIT was en-
tered will be completed with the executionof
the instruction that follows the WAIT and the
ST639x Coreis stillin the normal interrupt
mode.
Notes:all the interrupt sources are disabled, the restart theMCU can onlybe done bya Resetactivation.
The Wait instructionis not executedifan enabled
interrupt requestis pending.In the ST639x the
hardware activated digital watchdog functionis
present. As the watchdogis always activated the
STOP instructionis de-activatedand any attempt execute the STOP instruction will causean exe-
cutionofa WAIT instruction.
ST6391,92,93,95,97,99
ON-CHIP CLOCK OSCILLATORThe internal oscillator circuitis designedto require minimumof external components.A crystal
quartz,a ceramic resonator,or an external signal
(providedto the OSCin pin) maybe usedto gener-
atea system clock with various stability/cost trade-
offs. The typical clock frequencyis 8MHz. Please
note that differentfrequencieswill affecttheoperation thoseperipherals(D/As, SPI)whosereference fre-
quenciesarederivedfrom the system clock.
The different clock generator options connection
methods are shownin Figures25 and 26. One ma-
chine cycle takes 13 oscillator pulses; 12 clock
pulses are neededto increment the PC while and
additional 13thpulseis neededto stabilize the inter-
nal latches during memory addressing. This means
thatwitha clock frequencyof 8MHz the machinecy-
cleis 1.625μs.
The crystal oscillator start-up timeisa functionof
manyvariables:crystal parameters (especially RS),
oscillatorload capacitance (CL),IC parameters,am-
bienttemperature,and supply voltage.Itmustbe ob-
served that the crystalor ceramic leads and circuit
connections mustbeas shortas possible. Typical
valuesfor CL1 and CL2 arein the rangeof 15pFto
22pF buttheseshouldbe chosen basedon thecrys-
tal manufacturersspecification. Typical inputcapaci-
tanceforOSCin and OSCout pinsis 5pF.
The oscillatoroutput frequencyis internallydivided 13to produce the machine cycle andby12to
produce the Timer and the Watchdogclock.A byte
cycleis the smallest unit neededto execute any
operation (i.e.,increment the program counter).An
instruction may need two, four,or five byte cycles beexecuted (See Table7).
Instruction Type Cycles Execution
TimeBranchif set/reset 5 Cycles 8.125μs
Branch& SubroutineBranch 4 Cycles 6.50μs
Bit Manipulation 4 Cycles 6.50μs
Load Instruction 4 Cycles 6.50μs
Arithmetic& Logic 4 Cycles 6.50μs
Conditional Branch 2 Cycles 3.25μs
Program Control 2 Cycles 3.25μs
Table7. Intructions Timing with 8MHz Clock
Figure 25. Clock Generator Option(1)
Figure 26. Clock Generator Option(2)
Figure 27. OSCin, OSCout Diagram
ST6391,92,93,95 ,97,99
INPUT/OUTPUT PORTSThe ST639x microcontrollers use three standard
I/O ports (A,B,C) withupto eight pinson each port;
referto the device pin configurationsto see which
pins areavailable.
Each line canbe individuallyprogrammed eitherin
the input modeor the output modeas followsby
software. Output Input with on-chip pull-up resistor (selectedby
software) Input withouton-chip pull-up resistor (selected software)
Note: pins with 12V open-drain capabilitydo not
have pull-up resistors. output mode the following hardware configura-
tions are available: Open-drain output 12V (PA4-PA7, PC4-PC7) Open-drain output 5V (PC0-PC3) Push-pull output (PA0-PA3,PB0-PB6)
The lines areorganizedin three ports (portA,B,C).
The ports occupy6 registersin the data space.
Eachbitof these registersis associated witha par-
ticular line (for instance, the bits0of the PortA
Data and Direction registers are associated with
the PA0 lineof Port A).
There arethree Data registers (DRA, DRB, DRC),
that are used toread the voltage level valuesof the
lines programmedin the input mode,orto write the
logic valueof the signaltobe outputon the lines
configuredin the output mode. The port Data Reg-
isters canbe readto get the effectivelogic levelsof
the pins, but they canbe also writtenby the user
software,in conjunction with the related Data Di-
rection Register,to select the different input mode
options. Single-bit operationson I/O registers (bit
set/reset instructions) are possible but careis nec-
essary because readingin input modeis made
from I/O pins and therefore mightbe influencedby
the external load, while writing will directly affect
the Port data register causing an undesired
changesof the input configuration. The three Data
Direction registers (DDRA, DDRB, DDRC) allow
the selectionof the directionof each pin (inputor
output).
All the I/O registers canbe reador writtenas any
other RAM locationof the data space,sono extra
RAM cellis needed for port data storing and ma-
nipulation. During the initializationof the MCU,all
the I/O registers are cleared and the input mode
with pull-upis selectedonall the pinsthusavoiding
pin conflicts(with theexceptionofPC2 that issetin
output mode andis set highie. high impedance).
Detailsof I/O PortsWhen programmedasan inputa pull-up resistor(if
available) can be switched active under program
control. When programmedas an output the I/O
port will operate eitherin thepush-pull mode orthe
open-drain mode accordingto the hardware fixed
configurationas specified below.
PortA. PA0-PA3 are availableas push-pull when
outputs. PA4-PA7 are availableas open-drain (no
push-pull programmability) capableof withstand-
ing 12V (no resistive pull-upin input mode). PA6-
PA7 has been specially designed forhigher driving
capability and are ableto sink 25mA witha maxi-
mum VOLof 1V.
PortB.All lines are configuredas push-pull when
outputs.
PortC. PC0-PC3 are availableas open-drain ca-
pable ofwithstandinga maximumV DD+0.3V. PC4-
PC7 are available as open-drain capable of
withstanding 12V (no resistive pull-upin input
mode). Some lines are also usedas I/O buffersfor
signals coming from the on-chip SPI. this case the final signal on the output pinis
equivalenttoa wired AND with the programmed
data output. the user needsto use the serial peripheral, the
I/O line should be setin output mode while the
open-drain configurationis hardware fixed; the
corresponding data bit must setto one.If the
latched interrupt functions are used(IRIN, PWRIN)
then the corresponding pins shouldbe setto input
mode. ST639x the I/O pins with doubleor special
functions are: PC0/SCL (connectedto theSPI clock signal) PC1/SDA (connectedto the SPI data signal) PC3/SEN(connected tothe SPI enable signal) PC4/PWRIN (connectedto the PWRIN inter-
rupt latch) PC6/IRIN (connectedto the IRIN interrupt
latch)
All the Port A,B andC I/O lines have Schmitt-trig-
ger input configuration witha typical hysteresisof
1V.
ST6391,92,93,95,97,99
PA7-PA0. Theseare the I/O port Adata bits. Reset power-on.
PB7-PB0.These are the I/O port Bdata bits. Reset power-on.
PC7-PC0. Setto 04hat power-on.Bit2 (PC2 pin) set to one (open drain therefore high im-
pedence).
PA7-PA0. These are the I/O portA data direction
bits. Whenabitis clearedto zero the related I/O
lineisin input mode,ifbitis setto one the related
I/O lineisin output mode. Resetat power-on.
PB7-PB0. These are the I/O portB data direction
bits. Whenabitis clearedto zero the related I/O
lineisin input mode,ifbitis setto one the related
I/O lineisin output mode. Resetat power-on.
PC7-PC0. These are the I/O portC data direction
bits. Whenabitis clearedto zero the related I/O
lineisin input mode,ifbitis setto one the related
I/O lineisin output mode. Setto 04hat power-on.
Bit2 (PC2 pin)is setto one (output mode se-
lected).
DDR DR Mode Option 0 Input With on-chip pull-up
resistor 1 Input Without on-chip pull-up resistor X Output Open-drain orPush-Pull
Note:X: Means don’tcare.
Table8. I/O Port Options Selection
DRA, DRB, DRC
PortA, B,C Data Register C0h PA,C1h PB,C2h PCRead/ Write) D6D5D4 D3D2 D1D0 -PA7 =DataBits
PB0 -PB7 =DataBits
PC0 -PC7 =DataBits
Figure 28. PortA,B,C Data Register DDRA, DDRB,DDRC
Port A,B, CData Direction Register C4hPA, C5h PB,C6h PCRead/ Write) D6D5D4 D3D2 D1D0
PA0 -PA7 =Data DirectionBits
PB0 -PB7 =Data DirectionBits
PC0 -PC7 =Data DirectionBits
“0” Definesbitas Input
”1” Definesbitas Output
Figure 29. PortA,B,C Data Register
I/O Pin ProgrammingEachpin canbe individuallyprogrammedas inputor
outputwith differentinput and outputconfigurations.
Thisis achievedby writingto the relevantbitin the
data (DR) and data direction register (DDR). Table showsall the port configurations that canbe se-
lectedby the user software.
INPUT/OUTPUT PORTS (Continued)
ST6391,92,93,95 ,97,99
Figure 30. I/O Configuration Diagram
(Open Drain 12V)
Figure 31. I/O Configuration Diagram (Open Drain 5V, Push-pull)
Input/Output ConfigurationsThe following schematics show the I/O lines hard-
ware configurationfor the different options. Figure shows the I/O configurationfor an I/O pin with
open-drain 12Vcapability (standard drive and high
drive). Figure31 shows the I/O configurationforan
I/O pin with push-pull and with open drain5V capa-
bility.
Notes:The WAIT instruction allows the ST639xto be
usedin situations where low power consumptionis
needed. This can onlybe achieved howeverif the
I/O pins either are programmedas inputs with well
defined logic levelsor haveno power consuming
resistive loadsin output mode.As the same dieis
usedfor the differentST639x versions theunavail-
able I/O linesof ST639x shouldbe programmedin
output mode.
Single-bit operationson I/O registers are possible
but
careis necessary because readingin input
modeis made from I/O pins while writing will di-
rectly affectthe Port data register causingan unde-
sired changesof the input configuration.
INPUT/OUTPUT PORTS (Continued)
ST6391,92,93,95,97,99
TIMERSThe ST639x devices offertwo on-chip Timer periph-
erals consistingofan 8-bit counter witha 7-bitpro-
grammable prescaler, thus givinga maximum count215, anda control logic that allows configuring the
peripheral operating mode. Figure 32 shows the
timer block diagram. The contentof the 8-bit count-
ers canbe read/writtenin the Timer/Counter regis-
tersTCR thatcan beaddressed inthe data spaceas
RAM locationat addresses D3h (Timer1) and DBh
(Timer 2). The stateof the 7-bit prescaler can be
readin thePSC registerat addressesD2h (Timer1)
and DAh (Timer2). The control logicis managedby
TSCR registersat D4h (Timer1) and DCh (Timer2)
addressesas describedin the following paragraphs.
The following description appliesto both Timer1
and Timer2. The 8-bit counter isdecrementby the
output (rising edge) coming from the 7-bit pres-
caler and canbe loaded and read under program
control. Whenit decrementsto zero then the TMZ
(timer zero)bitin the TSCRis setto one.If the ETI
(enable timer interrupt)bitin the TSCRis also set onean interrupt request, associatedto interrupt
vector#3 (forTimer1) and#1for Timer2, isgener-
ated. The interruptof the timer canbe usedto exit
the MCU from the WAIT mode.
The prescaler decrements on rising edge. The
prescaler inputis the oscillator frequency divided 12.
Dependingon the division factor programmedby
PS2/PS1/PS0(see Table9) bitsin the TSCR, the
clock inputof the timer/counter registeris multi-
plexedto different sources. division factor1, the clock inputof the prescaleris
alsothat oftimer/counter;on factor2,bit 0ofprescaler
registeris connectedto theclockinputof TCR.
Thisbit changesits statewith the halffrequencyof
prescaler clock input. On factor4,bit1of PSCis
connectedto clock inputof TCR, andso on. Ondi-
vision factor 128, the MSBbit6of PSCis con-
nected to clock input of TCR. The prescaler
initializebit (PSI)in the TSCR register mustbe set oneto allow the prescaler (and hence the
counter)to start.Ifitis clearedto zero thenallof
the prescaler bits are setto one and the counteris
inhibited fromcounting.
The prescaler can be given any value between0
and 7Fhby writingto the related register address,bit PSIin the TSCR register issetto one. The tap the prescaleris selectedusing the PS2/PS1/PS0
bitsin the control register. Figure 33 shows the
timer working principle.
Figure 32. Timer Peripheral Block Diagram
ST6391,92,93,95 ,97,99
TIMERS (Continued)
Timer Operating ModesAsonST639xdevicesthe externalTIMER pinis not
available the only allowed operatingmodeis the out-
put mode thathavetobe selectedby settingto1bit andby clearingto0bit5in the TSCR1 register.
Thisprocedurewill enable bothTimer1 and Timer2.
Output Mode(TSCR1D4=1, TSCR1 D5=0). On
this mode the timer prescaleris clocked by the
prescaler clock input (OSC/12). The user can se-
lect the desired prescaler division ratio throughthe
PS2/PS1/PS0 bits. When TCR count reaches0,it
sets the TMZbitin the TSCR.
The TMZbit canbe tested under program control perform timer functions wheneverit goes high.
Bit D4 and D5on TSCR2 (Timer2) registerare not
implemented.
Timer InterruptWhen the counter register decrementsto zero and
the softwarecontrolled ETI (enable timer interrupt)
bitis setto one then an interrupt request associ-
ated tointerruptvector#3 (forTimer 1)andto inter-
rupt vector#1 (for Timer2)is generated.When the
counter decrementsto zero also the TMZbitin the
TSCR registeris setto one.
Figure 33. Timer Working Principle
Notes:TMZis set when the counter reaches 00H; how-
ever,it maybe setby writing 00Hin the TCR regis-
teror setting thebit7of the TSCR register. TMZ
bit mustbe clearedby user software when servic-
ing the timer interruptto avoid undesired interrupts
when leaving the interrupt serviceroutine. Afterre-
set, the 8-bit counterregisteris loadedto FFh while
the 7-bit prescaler isloadedto 7Fh, andthe TSCR
registeris cleared which means that timeris
stopped (PSI=0) and timer interrupt disabled. writeto the TCR register will predominate over
the 8-bit counter decrementto 00h function, i.e.ifa
write anda TCR register decrementto 00h occur
simultaneously,the write will take precedence, and
the TMZbitis not set untilthe 8-bit counter reaches
00h again. The valuesof the TCR and the PSC
registers canbe readaccuratelyat any time.
ST6391,92,93,95,97,99
PS2 PS1 PS0 DividedBy 0 1 1 2 0 4 1 8 016 132 064 1 1 128
Table9. Prescaler DivisionFactors
TSCR
Imer 1&2 Status Control Registers
DAh Timer 1,DCh Timer2,
Read/ Write D6D5D4 D3D2 D1D0
PS0 =PrescalerMux.Select
PS1 =PrescalerMux.Select
PS2 =PrescalerMux.Select
PSI =PrescalerInitializeBit= TimersEnableBit*= TimersEnableBit*
ETI= Enable TimerInterrupt
TMZ=TimerZeroBit OnlyAvailable inTSCR1
Figure 34. Timer Status Control Registers
TIMERS (Continued)
TMZ. Low-to-high transition indicates thatthe timer
count register has decrementtozero. This bitmust clearedby user software beforeto start witha
new count.
ETI. This bit, when set, enables the timer interrupt
(vector #3forTimer 1,vector#1for Timer2) request. ETI=0 the timer interruptis disabled.If ETI=1 and
TMZ= 1an interrupt requestis generated.
D5. Thisis the timers enable bit D5.It must be
clearedto0 togetherwitha setto1ofbit D4to en-
able both Timer1 and Timer2 functions.Itis not
implementedon TSCR2 register.
D4. Thisis the timers enablebit D4. Thisbit must setto1 togetherwitha clearto0of bitD5to en-
able both Timer1 and Timer2 functions.Itis not
implementedon TSCR2 register.
D4 Timers 0 Disabled 1 Enabled X Reserved
PS1. Usedto initialize the prescaler and inhibit its
countingwhile PSI=0 theprescaleris setto7Fh and
the counteris inhibited. When PSI=1 the prescaler enabledto count downwards.As longas PSI=0
both counterand prescaler are not running.
PS2-PS0. These bits select the division ratioof the
prescaler register. (see Table9)
The TSCR1 and TSCR2 registers are clearedon
reset. The correct D4-D5 combination must be
writtenin TSCR1by user’s softwareto enable the
operationof Timer1 and Timer2.
TCR
Timer Counter1&2 Register
D3h Timer1, DBh Timer2, Read/ Write D6D5D4 D3D2 D1D0-D0= Counterbits
Figure 35. Timer Counter Registers
PSC
TimerPrescaler 1&2 Register
D2h Timer1, DAh Timer2, Read/ Write D6D5D4 D3D2 D1D0-D0= Prescalerbits
Always readas“0”
Figure 36. Timer Counter Registers
ST6391,92,93,95 ,97,99
