ST52T430K3B6 ,8-BIT INTELLIGENT CONTROLLER UNIT ICU Three Timer/PWMs, ADC, SCIGENERAL DESCRIPTION A Serial Communication peripheral (SCI), whichuses the UART protocol allows dat ..
ST52T430K3M6 ,8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, SCIFunctional Description . .51.2.1 Memory Programming Mode 51.2.2 Working mode . ..
ST52T440G3B6 ,8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDGTABLE OF CONTENTS1GENERALDESCRIPTION..... 71.1 Introduction.... ...... ...... ....... ...... ...... ..
ST5382 , BROADBAND ACCESS: xDSL, HPN, CMCs
ST5451D ,ISDN HDLC AND GCI CONTROLLERST5451 ISDN HDLC AND GCI CONTROLLERMONOLITHIC ISDN ORIENTED HDLC ANDGCI CONTROLLER.GCI AND μW/DSI ..
ST5771 ,PNP Switching Transistorapplications at currents to 100mA. Sourced from Process 65.See PN4258 for characteristics.Absolute ..
STN3904 , NPN Silicon Transistor
STN3904 , NPN Silicon Transistor
STN3906 , PNP Silicon Transistor
STN3906 , PNP Silicon Transistor
STN3906SF , PNP Silicon Transistor
STN3NE06 ,N-CHANNEL 60V
ST52T430K3B6-ST52T430K3M6
8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, SCI
Rev. 1.12 - May 2004 1/85
Memories Up to 8 Kbytes EPROM/OTP 256 bytes of RAM Readout Protection
Core Register File Based Architecture 55 instructions Hardware multiplication and division Decision Processor for the implementation of
Fuzzy Logic algorithms
Clock and Power Supply Up to 20 MHz clock frequency. Power Saving features
Interrupts 6 interrupt vectors Top Level External Interrupt (INT)
Peripherals 3 Programmable 8-bit Timer/PWMs with internal
16-bit Prescaler featuring: Watchdog timer On-chip 8-bit Sample and Hold A/D Converter
with 8-channel analog multiplexer Serial Communication Interface with
asynchronous protocol (UART)
ST52x430 Devices Summary
2/85
TABLE OF CONTENTS
ST52T430/E430
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2.1 Memory Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 Working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2 INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.1 ST52x430 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Control Unit and Data Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.3.1 RAM and STACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.2 Input Registers Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.3 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.4 Output Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.1 EPROM Programming Phase Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1.1 EPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.2 EPROM Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.3 EPROM Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1.4 EPROM Read/Verify Margin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.5 Stand by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.6 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Eprom Erasure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.1 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.2 Global Interrupt Request Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.4 Interrupt Maskability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.5 Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.6 Interrupts and Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
4.7 Interrupt RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5 CLOCK, RESET & POWER SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . 305.1 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.3 Power Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.3.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.2 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TABLE OF CON-
TENTS
ST52T430/E430
6 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
6.3 Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.4 Alternate Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.5 I/O Port Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7 FUZZY COMPUTATION (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397.1 Fuzzy Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.2 Fuzzyfication Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.3 Inference Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.4 Defuzzyfication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
7.5 Input Membership Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
7.6 Output Singleton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
7.7 Fuzzy Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
8 A/D CONVERTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
8.2 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
8.2.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.2.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.3 A/D Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
9 WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469.1 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
9.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
10 PWM/TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4810.1 Timer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
10.2 PWM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
10.3 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
11 SERIAL COMMUNICATION INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 6211.1 SCI Receiver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
11.2 SCI Transmitter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
11.3 Baud Rate Generator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6612.1 Parameter Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
12.1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.1.3 Typical curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
12.3 Recommended Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
12.4 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
ST52T430/E43012.5 Clock and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
12.6 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
12.7 ESD Pin Protection Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
12.7.1 Standard Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.7.2 Multi-supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8 Port Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
12.8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.9 Control Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
12.9.1 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.9.2 VPP pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.10 8-bit A/D Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
13 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8413.1 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
13.2 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
13.2.1 Exit from HALT with a long duration External Interrupt signal . . . . . . . . . . . . . . . . . . . . . 84
13.2.2 Interrupt priority change after a RINT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
13.2.3 Zero Flag after Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
13.3 HARDWARE TOOL WARNING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
13.3.1 ST52x430 low cost Evaluation Kits resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ST52T430/E430
1 GENERAL DESCRIPTION
1.1 IntroductionST52x430 is an 8-bit Intelligent Control Units (ICU)
of the ST Five Family, which can perform both
boolean and fuzzy algorithms in an efficient
manner, in order to reach the best performances
that the two methodologies allow.
ST52x430 is produced by STMicroelectronics
using the reliable high performance CMOS
process, including integrated-on-chip peripherals
that allow maximization of system reliability,
decreasing system costs and minimizing the
number of external components.
The flexible I/O configuration of ST52x400/440
allows for an interface with a wide range of external
devices, like D/A converters or power control
devices.
ST52x430 pins are configurable, allowing the user
to set the input or output signals on each single pin.
A hardware multiplier (8 bit by 8 bit with 16 bit
result) and a divider (16 bit over 8 bit with 8 bit
result and 8 bit remainder) are available to
implement complex functions by using a single
instruction. The program memory utilization and
computational speed is optimized.
Fuzzy Logic dedicated structures in ST52x430
ICU’s can be exploited to model complex systems
with high accuracy in a useful and easy way.
Fuzzy Expert Systems for overall system
management and fuzzy Real time Controls can be
designed to increase performances at highly
competitive costs.
The linguistic approach characterizing Fuzzy Logic
is based on a set of IF-THEN rules, which describe
the control behavior, as well as on Membership
Functions, which are associated to input and
output variables.
Up to 334 Membership Functions, with triangular
and trapezoidal shapes, or singleton values are
available to describe fuzzy variables.
The Ti mer/ PWM peripheral allows the
management of power devices and timing signals,
implementing different operating modes and high
frequency PWM (Pulse With Modulation) controls.
Input Capture and Output Compare functions are
available on the TIMER.
The programmable Timer has a 16 bit Internal
Prescaler and an 8 bit Counter. It can use internal
or external Start/Stop signals and clock.
An internal programmable Watchdog is available
to avoid loop errors and to reset the ICU.
ST52x430 includes an 8-bit Analog to Digital
Converter with an 8-analog channel Multiplexer.
Single/Multiple channels and Single/Sequence
conversion modes are supported.
A Serial Communication peripheral (SCI), which
uses the UART protocol allows data transfer from
the ST52x430 to other external devices.
In order to optimize energy consumption, two
different power saving modes are available: Wait
mode and Halt mode.
Program Memory (EPROM/OTP) addressing
capability addresses up to 8 Kbytes of memory
locations to store both program instructions and
permanent data.
EPROM can be locked by the user to prevent
external undesired operations.
Operations may be performed on data stored in
RAM, allowing the direct combination of new input
and feedback data. All bytes of RAM are used like
Register File.
OTP (One Time Programmable) version devices
are fully compatible with the EPROM windowed
version, which may be used for prototyping and
pre-production phases of development.
A powerful development environment consisting of board and software tools allows an easy
configuration and use of ST52x430.
The VISUAL FIVETM software tool allows
development of projects through a user-friendly
graphical interface and optimization of generated
code.
1.2 Functional DescriptionST52x430 ICU can work in two modes: Memory Programming Mode Working Mode
according to RESET and Vpp signals levels (see
pins description).
Note: When RESET=0 it is advisable not to usethe sequence “101010“ to port PA (7 : 2).
1.2.1 Memory Programming Mode.The ST52x430 memory is loaded in the Memory
Programming Phase. All fuzzy and standard
instructions are written inside the memory.
This phase starts by setting the control signals as
illustrated below:
When this phase starts, the ST52x430 core is set
to RESET status; then 12V are applied to the Vpp
ST52T430/E430pin in order to start EPROM programming. A signal
applied to PB1 is used to increment the memory
address; the data is supplied to PORT A (see
EPROM programming for further details).
1.2.2 Working mode.Below are the control signals of this mode:
The processor starts the working phase following
the instructions, which have been previously
loaded in the memory.
ST52x430’s in ternal structure includes a
computational block, CONTROL UNIT (CU) /
DATA PROCESSING UNIT (DPU), which allows
processing of boolean functions and fuzzy
algorithms.
The CU/DPU can manage up to 334 different
Membership Functions for the fuzzy rules
antecedent part. The rule consequents are “crisp”
values (real numbers). The maximum number of
rules that can be defined is limited by the
dimens ions of the implemented standard
algorithm.
EPROM is then shared between fuzzy and
standard algorithms. The Membership Function
data is stored inside the first 1024 memory
locations. The Fuzzy rules are parts of the program
instructions.
The Control Unit (CU) reads the information and
the status deriving from the peripherals.
Arithmetic calculus can be performed on these
values by using the internal CU and the 128/256
bytes of RAM, which supports all computations.
The peripheral input can be fuzzy and/or arithmetic
output, or the values contained in Data RAM and
EPROM locations.
ST52T430/E430
Figure 1.1 SSO34 Pin Configuration
Figure 1.2 PSDIP32 Pin Configuration
ST52T430/E430
Table 1.1 ST52x430 SSO34 & PSDIP32 Pin list
ST52T430/E430
1.3 Pin DescriptionDD,
VSS, V
DDA , GNDA, VPP . In order to avoidnoise disturbances, the power supply of the digital
part is kept separate from the power supply of the
analog part.
VDD. Main Power Supply Voltage (5V± 10%).SS . Digital circuit ground.
DDA . Analog VDD of the Analog to Digital
Converter.
GNDA. Analog VSS of the Analog to DigitalConverter. Must be tied to V
SS.
VPP. Main Power Supply for internal EPROM(12.5V±5%, in programming phase) and MODE
sele ctor. During the Programming phase
(programming), VPP must be set at 12V. In the
Working phase VPP must be equal to V
SS.
OSCin and OSCout. These pins are internallyconnected with the on-chip oscillator circuit. A
quartz crystal or a ceramic resonator can be
connected between these two pins in order to allow
the correct operations of ST52x430 with various
stability/cost trade-off. An external clock signal can
be applied to OSCin, in this case OSCout must be
floating.
RESET. This signal is used to restart ST52x430 atthe beginning of its program. It also allows one to
select the program mode for EPROM.
Ain0-Ain8. These 8 lines are connected to theinput of the analog multiplexer. They allow the
acquisi tion of 8 analog input. During the
Programming phase, Ain0, Ain1, Ain2 and Ain3 are
used to manage EPROM operation.
PA0-PA7, PB0-PB7, PC0-PC7. These lines areorganized as I/O port. Each pin can be configured
as input or output. PA7/PB7 are tied to the same
output. During Programming phase PA port is used
for EPROM read/write data.
T0RES, T0CLK, T0STRT. These pins are relatedwith the internal Programmable Timer/PWM 0.
This Timer can be reset externally by using
T0RES. In Working Mode, T0RES resets the
address counter of the Timer. T0RES is active at
low level.
The Timer 0 Clock can be the internal clock or can
be supplied externally by using pin T0CLK.
An external Start/Stop signal can be used to
control the Timer through T0STRT pin.
T0OUT, T1OUT, T2OUT. The TIMER/PWMoutputs are available on these pins.
T0OUT, T1OUT, T2OUT. The TIMER/PWMcomplementary outputs are available on these
pins.
Tx. Serial data output of SCI transmitter block
Rx. Serial data input of the SCI receiver block.
TEST. During the Programming and Workingphase it must be set to Vss.
ST52T430/E430
Figure 1.3 ST52X430 Block Diagram
ST52T430/E430
2 INTERNAL ARCHITECTUREST52x430 is made up of the following blocks and
peripherals: Control Unit (CU) and Data Processing Unit
(DPU) ALU / Fuzzy Core EPROM 256 Byte RAM Clock Oscillator Analog Multiplexer and A/D Converter 3 PWM / Timers SCI Digital I/O port
2.1 ST52x430 Operating ModesST52x430 works in two modes, Programming and
Working Modes, depending on the control signals
level RESET, TEST and VPP
The Operating modes are selected by setting the
control signal level as specified in the Control
Signals Setting table.
2.2 Control Unit and Data Processing UnitThe Control Unit (CU) formally includes five main
blocks. Each block decodes a set of instructions,
generating the appropriate control signals. The
main parts of the CU are illustrated in Figure 2.1.
The five different parts of the CU manage Loading,
Logic/Arithmetic, Jump, Control and the Fuzzy
instruction set.
The block called “Collector” manages the signals
deriving from the different parts of the CU, defining
the signals for the Data Processing Unit (DPU) and
the different peripherals of the microcontroller.
The block called “Arbiter” manages the different-
parts of the CU so that only one part of the system
is activated during working mode.
The CU structure is very flexible. It was designed
with the purpose of easily adapting the core of the
microcontroller to market needs. New instruction
sets or new peripherals can be easily included
without changing the structure of the
microcontroller, maintaining code compatibility.
The CU reads the instructions stored on EPROM
(Fetch) and decodes them. According to the
instruction types, the arbiter activates one of the
main blocks of the CU. Afterwards, all the control
signals for the DPU are generated.
A set of 46 different arithmetic, fuzzy and logic
instructions is available. Each instruction requires
6 (fuzzy instructions) to 26 (DIVISION) clock
pulses to be performed.
The DPU receives, stores and sends instructions
deriving from EPROM, RAM or peripherals in order
to execute them.
2.2.1 Program Counter.The Program Counter (PC) is a 13-bit register that
contains the address of the next memory location
to be processed by the core. This memory location
may be an opcode, operand, or an address of an
operand.
The 13-bit length allows direct addressing of a
maximum of 8,192 bytes in the program space.
After having read the current instruction address,
the PC value is incremented. The result of this
operation is shifted back into the PC.
The PC can be changed in the following ways: JP (Jump)PC = Jump Address InterruptPC = Interrupt Vector RETIPC = Pop (stack) RETPC = Pop (stack) CALLPC = Subroutines address ResetPC = Reset Vector Normal InstructionPC = PC + 1
2.2.2 Flags.The ST52x430 core includes a different set of
flags that correspond to 2 different modes: normal
mode and interrupt mode. Each set of flags con-
sists of a CARRY flag (C), ZERO flag (Z) and
SIGN flag (S).
One set (CN, ZN, SN) is used during normal
operation and one is used during interrupt mode
(CI, ZI, SI).
Formally, the user has to manage
only one set of flags: C, Z and S.
Table 2.1 Control Signals Setting
ST52T430/E430
Figure 2.2 CU/DPU Block Diagram
ST52T430/E430The ST52x430 core uses flags that correspond to
the actual mode. As soon as an interrupt is
generated the ST52x430 core uses the interrupt
flags instead of the normal flags.
Each interrupt level has its own set of flags, which
is saved in the STACK together with the Program
Counter. These flags are restored from the STACK
automatically when a RETI instruction is executed.
If the MCU was in normal mode before an interrupt,
the normal flags are restored when the RETI
instruction is executed.
Note: A CALL subroutine is a normal mode
execution. For this reason, a RET instruction,
consequent to a CALL instruction does not affect
the normal mode set of flags.
Flags are not cleared during context switching and
remain in the state they were at the end of the last
interrupt routine switching.
The Carry flag is set when an overflow occurs
during arithmetic operations, otherwise it is
cleared. Input Registers: 20 8-bit registers Output Registers 10 8-bit registers Configuration Registers: 21 8-bit registers Program memory up to 8K Bytes
Program memory will be described in further
details in the MEMORY section
2.3.1 RAM and STACK.RAM memory consists of 256 general purpose 8-
bit RAM registers.
All the registers in RAM can be specified by using
a decimal address. For example, 0 identifies the
first register of RAM.
To read or write RAM registers LOAD instructions
must be used. See Table 2.5
Each interrupt level has its own set of flags, which
is saved in the STACK together with the Program
Counter. These flags are restored from the STACK
automatically when a RETI instruction is executed.
When the instructions like Interrupt request or
ST52T430/E430The STACK POINTER indicates the first level
available to store data. When a subroutine call or
interrupt request occurs, the content of the PC and
the current set of flags are stored into the level
located by the STACK POINTER.
When a interrupt return occurs (RETI instruction),
the data stored in the highest stack level is
restored back into the PC and current flags.
Instead, when a subroutine return occurs (RET
instruction) the data stored in the highest stack
level are restored in the PC not affecting the flags.
These operating modes are illustrated in Figure
Note: The user must pay close attention to avoid
overwriting RAM locations where the STACK could
be stored.
All the registers can be specified by using a
decimal address (for example, 0 identifies the first
register of the IR).
The assembler instruction:
LDRI RAM_Reg. IR_i
loads the value of the i-th IR in the RAM location
identified by the RAM_Reg address.
The first input register is dedicated to store the
value of the stack pointer. The next 8 registers
(ADC_OUT_0:7) of the IR are dedicated to the 8
converted values deriving from the ADC. The last
9 Input Registers contain data from the I/O ports
and PWM/Timers. The following table summarizes
the IR address and the relative peripherals. In
order to simplify the concept, a mnemonic name is
assigned to the registers. The same name is used
ST52T430/E430
2.3.3 Configuration Registers.The ST52x430 configuration Registers allow the
configuration of all the blocks of the fuzzy
microcontroller. Table 2.3 describes the functions
and the related peripherals of each of the
Configuration Registers. By using the load
instructions, the Configuration Registers can be
set by using values stored in the Program Memory
(EPROM) or in RAM.
Use and meaning of each register will be described
in further details in the corresponding section.
Table 2.2 Input Registers
Table 2.3 Configuration Registers
ST52T430/E430
2.3.4 Output Registers.The Output Registers (OR) consist of 10 registers
containing data for the microcontroller peripherals
including the I/O Ports.
All registers can be specified by using a decimal
address (for example, 1 identifies the second OR).
By using LOAD instructions the Output Registers
(OR) may be set by using values stored in the
Program Memory (LDPE) or in RAM (LDPR)
The assembler instruction:
LDPR OR_i RAM_Reg.
loads the value of the RAM location identified by
the address RAM_Reg in the OR i-th Table 2.4
describes OR.
In order to simplify the concept, a mnemonic name
is assigned to OR. The same names are used in
FUZZYSTUDIOTM 4.0 development tools.
Use and meaning of each register will be described
in further details in the corresponding section.
Table 2.3 Configuration Registers (continued)
ST52T430/E430
2.4 Arithmetic Logic UnitThe 8-bit Arithmetic Logic Unit (ALU) allows the
performance of arithmetic calculations and logic
instructions, which can be divided into 5 groups:
Load, Arithmetic, Jump, Interrupts and Program
Control instructions (refer to the ST52x430
Assembler Set for further details).
The computational time required for each
instruction consists of one clock pulse for each
Cycle plus 3 clock pulses for the decoding phase.
The ALU of the ST52x430 can perform
multiplication (MULT) and division (DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Figure 2.5 and Figure 2.6.
WARNING: If the LSB of the multiplication
result is 0, the Zero flag is set although the
result is not 0.
Table 2.4 Output Registers
Table 2.5 Load instructions
ST52T430/E430
Table 2.6 Arithmetic & Logic instructions set
Table 2.7 Jump Instruction Set
Table 2.8 Interrupt Instructions Set
Table 2.5 Load instructions
ST52T430/E430
Table 2.9 Control Instructions Set
Table 2.8 Interrupt Instructions Set (continued)
ST52T430/E430
3 EPROMEPROM memory provides an on-chip user-
programmable non-volatile memory, which allows
fast and reliable storage of user data.
EPROM memory can be locked by the user. In
fact, a memory location called Lock Cell is devoted
to lock EPROM and avoid external operations. A
software identification code, called ID CODE,
distinguishes which software version is stored in
the memory.
64 kbits of memory space with an 8-bit internal
parallelism (up to 8 kbytes) addressed by an 13-bit
bus are available. The data bus is 8 bits.
Memory has a double supply: VPP is equal to
12V±5% in Programming Phase or to VSS during
Working Phase. VDD is equal to 5V±10%.
ST52x430 EPROM memory is divided into three
main blocks (see Figure ): Interrupt Vectors memory block (3 through 20)
contains the addresses for the interrupt routines.
Each address is composed of three bytes. Mbfs Setting memory block (21 through
MemAdd) contains the coordinates of the
vertexes of every Mbf defined in the program.
Figure 3.1 Program Memory Organization The maximum value of MemAdd is 1023. This
area is dynamically assigned according to the
size of the fuzzy routines. The unused memory
area, if any, is assigned to the Program
Instruction Set memory block. The Program Instructions Set memory block
(MemAdd through MemAddx) contains the
instruction set of the user program. The
following table summarizes the values of Mem
Addx for the different devices
Table 3.1 Mem AddxLocations 0, 1 and 2 contain the address of the first
microcode instruction.The operations that can be
performed on EPROM during the Programming
Phase are: Stand By, Memory Writing, Reading
and Verify/Margin Mode, Memory Lock, IDCode
Writing and Verify.
ST52T430/E430The operations above are managed by using the
internal 4-bit EPROM Control Register. The
reading phase is executed with VPP= 5V±5%, while
the verify/Margin Mode phase needs VPP=
12V±5%. The Blank Check must be a reading
operation with VPP= 5V±5%.
Table 3.2 illustrates EPROM Control Register
codes used to identify the operation running.
3.1 EPROM Programming Phase Procedure The Programming mode is selected by applying
12V±5% voltage or 5V±5% voltage to the VPP pin
and setting the control signal as following:
RESET =Vss
TEST =Vss
If the VPP voltage is 5V±5% only reading may be
performed.
RST_ADD, INC_ADD, RST_CONF, INC_CONF
and PHASE are the control signals used during the
Programming Mode.
PHASE, RST_CONF and RST_ADD signals are
active on level, the others are active on rising
edge.
Table 3.2 EPROM Control Register
ST52T430/E430PHASE and RST_ADD signals are active low,
RST_CONF signal is active high.
Port A is used for the memory data I/O. (See Table
3.2 for pin reference on the different packages). Memory may be locked by means of the Memory
Lock Status, which is a flag used to enable
EPROM operations.
If Memory Lock Status is 1 all EPROM operations
are enabled, otherwise the user may only read
(and verify) the OTP code and the Memory Lock
Status.
Only if EPROM is not locked by means of Lock Cell
(see EPROM Locking may EPROM operations be
enabled by changing the Memory Lock Status from
0 to 1.
RST_ADD signal resets the memory address
register and the Memory Lock Status. When the
RST_ADD becomes high, the memory must be
unlocked in order to read or write.
INC_ADD signal increments the memory address.
RST_CONF signal resets the EPROM Control
Register. When RST_CONF is high, the DATA I/
O Port A is in output, otherwise it is always in
input.INC_CONF signal increments the EPROM Control
Register value.
PHASE signal validates the operation selected by
means of the EPROM Control Register value.
3.1.1 EPROM Operation.In order to execute an EPROM operation (See
Table 3.2), the corresponding identification value
must be loaded in the EPROM Control Register.
The signal timing is the following: RST_ADD= high
and PHASE= high, RST_CONF changes from low
to high level, to reset the EPROM Control Register,
and INC_CONF signal generates a number of
positive pulses equal to the value to be loaded.
After this sequence, a negative pulse of the
PHASE signal will validate the operation selected.
The minimum PHASE signal pulse width must be
10 µs for EPROM Writing Operation and 100 ns for
the others.
When RST_CONF is high, DATA I/O Port A is
enabled in output and the reading/verifying
operation results are available.
After a writing operation, when RST_CONF is high,
Port A is in output without valid data.
3.1.2 EPROM Locking.The Memory Lock operation, which is identified
with the number 4 in the EPROM Control Register,
writes “0" in the Memory Lock Cell.
At the beginning of an External Operation, when
the RST_ADD signal changes from low level to
high level, the Memory Lock Status is “0", therefore
it must be unlocked before proceeding.
In order to unlock the Memory Lock Status the
operation, which is identified by the number 2 in
the EPROM Control Register must be executed
(see Figure 3.2).
Memory Lock Status can be changed only if
Memory Lock Cell is “1". After a Memory Lock
operation external operations cannot be executed
except to read (or verify) the OTP Code and the
Memory Lock Status.
3.1.3 EPROM Writing.When the memory is blank, all bits are at logic level
“1". Data is introduced by programming only the
zeros in the desired memory location. However, all
input data must contain both ”1" and “0".
The only way to change “0" into ”1" is to erase the
entire memory (by exposure to Ultra Violet light)
and reprogram it.
The memory is in Writing mode when the EPROM
Control Register value is 3.
The VPP voltage must be 12V±5%, with stable data
on the data bus PA(0:7).
The timing signals are the following (see Figure ):
1) RST_ADD and RST_CONF change from low to
high level,
2) two pulses on INC_CONF signal load the
Memory Unlock operation code,
3) a negative pulse (100 ns) on the PHASE signal
validates the Memory Unlock operation,
4) a negative pulse on RST_CONF signal resets
the EPROM Control Register,
5) three positive pulses on INC_CONF load the
Memory Writing operation code,
6) a train of positive pulses on INC_ADD signal
increments the memory location address up to the
requested value (generally this is a sequential
operation and only one pulse is used),
7) a negative pulse (10 µs) on the PHASE signal
validates the Memory Writing operation.
ST52T430/E430
3.1.4 EPROM Read/Verify Margin Mode.The read phase is executed with VPP= 5V±5%,
instead of the verify phase that needs VPP=
12V±5%.
The Memory Verify operation is available in order
to verify the accuracy of the data written. A
Memory Verify Margin Mode operation can be
executed immediately after writing each byte, in
this case (see Figure ):
1) a positive pulse on RST_CONF signal resets the
EPROM Control Register, if it wasn’t already reset;
2) one positive pulse on INC_CONF loads the
Memory Read/Verify operation code;
3) a negative pulse (100 ns) on the PHASE signal
validates the Memory Reading / Verify operation;
4) a negative pulse on RST_CONF signal puts in
the PA(0:7) port the value stored in the actual
memory address and resets the EPROM Control
Register;
If an error occurred writing, the user has to repeat
EPROM writing.
3.1.5 Stand by Mode.EPROM has a standby mode, which reduces the
active current from 10mA (Programming mode) to
less than 100 µA. Memory is placed in standby
mode by setting the PHASE signal at a high level
or when the EPROM Control Register value is 0
and the PHASE signal is low.
3.1.6 ID code.A software identification code, called ID code may
be written in order to distinguish which software
version is stored in the memory.
64 Bytes are dedicated to store this code by using
the address values from 0 to 63.
The ID Code may be read or verified even if the
Memory Lock Status is “0".
The timing signals are the same as that of a normal
operation.
3.2 Eprom ErasureThe transparent window available in the
CSDIP32W package, allows the memory contents
to be erased by exposure to UV light.
Erasure begins when the device is exposed to light
with a wavelength shorter than 4000Å. Sunlight, as
well as some types of artificial light, includes
wavelengths in the 3000-4000Å range which, on
prolonged exposure can cause erasure of memory
contents. Therefore, it is recommended that
EPROM devices be fitted with an opaque label
over the window area in order to prevent
unintentional erasure.
The erasure procedure recommended for EPROM
devices consists of exposure to short wave UV
light having a wavelength of 2537Å. The minimum
integrated dose recommended (intensity x expo-
sure time) for complete erasure is 15Wsec/cm 2.
This is equivalent to an erasure time of 15-20
minutes using a UV source having an intensity of
12mW/cm 2 at a distance of 25mm (1 inch) from
the device window.
bytes of the EPROM memory location between
address 3 and 20.
The Interrupt routine is performed as a
code, checking if a higher priority interrupt has to
be passed at the end of each instruction.
Interrupt request with the higher priority stops the
lower priority Interrupt. The Program Counter and
the arithmetic flags are stored in the stack.
With the RETI (Return from Interrupt)
the arithmetic flags and Program Counter (PC) are
restored from the top of the stack. This stack was
already described in section RAM and STACK.
An Interrupt request cannot stop processing of the
fuzzy rule, but this is passed only after the end
a fuzzy rule or at the end of a logic, or arithmetic
instruction.
NOTE1: A fuzzy routine can only be interrupted
in the Main program.
However, if the fuzzy routine in the main
interrupted by an Interrupt routine containing
another fuzzy routine, the internal
registers used for the first are modified
results of the latter routine.
NOTE2: It is recommended not to interrupt a
Fuzzy function contained in an Interrupt
routine. In order to use a Fuzzy function inside
an interrupt routine, the user MUST include the
Fuzzy function between an UDGI (MDGI)
instruction and an UEGI (MEGI) instruction
(see the following paragraphs).
ST52T430/E430
4.2 Global Interrupt Request EnablingWhen an Interrupt occurs, it generates a Global
Interrupt Pending (GIP), that can be masked by
software. After a GIP a Global Interrupt Request
(GIR) will be generated and Interrupt service
routine associated to the interrupt with higher
priority will start.
In order to avoid possible conflicts between
interrupt masking set in the main program, or
inside high level language compiler macros, the
GIP is hung up through the User Global Interrupt
Mask or the Macro Global Interrupt Mask (see
Figure 4.2).
UEGI/UDGI instruction switches on/off the User
Global Interrupt Mask, enabling/disabling the GIR
for the main program.
MEGI/MDGI instructions switch the Macro Global
Interrupt Mask on/off, in order to ensure that the
macro will not be broken.
4.3 Interrupt SourcesST52x430 manages interrupt signals generated by
the internal peripherals (PWM/Timers, UART and
Analog to Digital Converter) or coming from the
INT/PC0 pin. The External Interrupt can be
programmed to be active on the rising or falling
edge of INT/PC0 signal by setting the PEXTINT bit
of the Configuration Register to 0.
WARNING: Changing the interrupt priority insidean interrupt service routine can cause unwanted
interrupt requests.
Each peripheral can be programmed in order to
generate the associated interrupt; further details
are described in the related chapter.
4.4 Interrupt MaskabilityThe interrupts can be masked by configuring the
REG_CONF 0 by means of LDCR, or LDCE,
instruction. The interrupt is enabled when the bit
associated to the mask interrupt is “1". Viceversa,
when the bit is ”0", the interrupt is masked and is
kept pendent.
For example:
LDRC 10,6 //load the constant 6 in the
RAM Register 10
LDCR 0, 10 // set the CONF_REG 0 with
the value stored in the RAM Register
the result is CONF_REG0 =00000110 enabling the
interrupts deriving from the ADC (INT_ADC) and
from the PWM/TIMER 0 (INT_PWM/TIMER0). Reset Configuration ‘000000’
Table 4.1 Configuration Register 0
Description
ST52T430/E430
Figure 4.4 Interrupt Configuration Register 0
Table 4.2 Interrupts Description
Level 6 is associated to the Main Program, levels 5
to 1 are programmable by
registers called REG_CONF17 and
REG_CONF18 (see
whereas the higher level is related to the external
interrupt (INT_EXT).
PWM/Timers, UART and ADC are identified by a
three-bit Peripheral Codes (see Table 4.2); in order
to set the i-th priority level the user must write the
peripheral label i in the related INTi priority level.
i.e.
LDRC
193=’11000001’ in the RAM Register 10)
LDRC
168=’10101000’ in the RAM Register 11)
LDCR
‘11000001’
LDCR 18, 11 // set the REG_CONF18=
‘10101000’
The following priority levels are defined: Level 1: INT_PWM/TIMER0 (PWM/TIMER 0
Code: 001) Level 2: INT_ADC (ADC Code: 000) Level 3: Int_PWM/Timer2 (PWM/TIMER 2
Code: 011) Level 4: INT_UART (UART Code: 100) Level 5: INT_PWM/TIMER1 (PWM/TIMER 1
Code: 010)
ST52T430/E430
Figure 4.6 Example of a sequence of Interrupt requests
Note: The Interrupt priority must be fixed at the
beginning of the main program, because at the
RESET REG_CONF17=’00000000’ &
REG_CONF18=’00000000’, that could generate
erroneous operations.
During program execution the interrupt priority can
only be modified, at main program level, with the
following procedure:
STEP 1:
Mask the interrupts by means of a UDGI (or MDGI)
instruction
STEP 2:
Change the REG_CONF 17 and REG_CONF18
values to modify the interrupt priority
STEP 3:
Reset all the pending interrupt instructions by
means of RINT instructions.
STEP 4:
Unmask the interrupts by means of a UEGI (or
MEGI) instruction
When a source provides an Interrupt request and
the request processing is also enabled, the CU
changes the normal sequential flow of a program
by transferring program control to a selected
service routine.
When an interrupt occurs the CU executes a JUMP
instruction to the address loaded in the related
location of the Interrupt Vector.
When the execution returns to the original program
it immediately begins following the instruction that
was interrupted.
Table 4.4 RINT Instruction code
ST52T430/E430
4.6 Interrupts and Low power modeAll interrupts allow the processor to leave the WAIT
low power mode. Only the external Interrupt allows
the processor to leave the HALT low power mode.
4.7 Interrupt RESETAn eventually pending interrupt can be reset with
the instruction RINT j, which resets the interrupt
j-th where j identifies the peripherals as described
in the following table (see Table 4.4).
The assembler instruction:
RINT 2
Resets the PWM/Timer 1 interrupt.
Note: The RINT command must be preceded
from a UDGI (or MDGI) command and followed
by a UEGI (or MEGI) command.
WARNING: If an interrupt is reset, with the RINT
instruction within its own interrupt routine, the
priority level of the interrupt becomes the
lowest and the routine can be immediately
interrupted by a lower priority interrupt
request.
ST52T430/E430
5 CLOCK, RESET & POWER SAVING MODE
5.1 System ClockThe ST52x430 Clock Generator module generates
the internal clock for the internal Control Unit, ALU
and on-chip peripherals and it is designed to
require a minimum number of external
components.
The ST52x430 oscillator circuit generates an
internal clock signal with the same period and
phase as that of the OSCin input pin. The
maximum frequency allowed is 20 Mhz.
Note: When the SCI peripheral is used only a 5,
10, or 20 MHz system clock must be used. The system clock may be generated by using
either a quartz crystal, ceramic resonator or an
external clock.
The different methods of the clock generator are
illustrated in Figure 5.1.
When an external clock is used, it must be
connected on the OSCin pin, while OSCout can be
floating.
The crystal oscillator start-up time is a function of
many variables: crystal parameters (especially
Rs), oscillator load capacitance (CL), IC
parameters, environment temperature, supply
voltage.
Note: The crystal or ceramic leads and circuit
connections must be as short as possible. Typical
values for CL1, CL2 are 10pF for a 20 MHz crystal.
5.2 RESETThere are two Reset sources:
- RESET pin (external source.)
- WATCHDOG (internal source)
When a Reset event happens, the user program
restarts from the beginning.
The Reset pin is an input. An internal reset does
not affect this pin.
A Reset signal originated by external sources is
recognized instantaneously. The RESET pin may
be used to ensure VDD has risen to a point where
the MCU can operate correctly before the user
program runs. In working mode Reset must be set
to ‘1’ (see Table 2.1).
5.3 Power Saving ModeThere are two Power Saving modes: WAIT and
HALT mode. These conditions may be entered
using the WAIT or HALT instructions.
5.3.1 Wait Mode
ST52T430/E430and the watchdog remain active. During WAIT
mode, Interrupts are enabled. The MCU will
remain in Wait mode until an Interrupt or a RESET
occurs, whereupon the Program Counter jumps to
the interrupt service routine or, if a RESET occurs,
at the beginning of the user program.
REMARK: In Wait mode the CPU clock does notstop.
5.3.2 Halt ModeHalt mode is MCU’s lowest power consumption
Halt mode cannot be used when the watchdog
is enabled. If the HALT instruction is executed while the
watchdog system is enabled, it will be skipped
without modifying the normal CPU operations.
The ICU can exit Halt mode after an external inter-
rupt or reset. The oscillator is then turned on and
stabilization time is provided before restarting
CPU operations. Stabilization time is 4096 CPU
clock cycles after the interrupt and 1.000.000 after
the Reset.
ST52T430/E430
Figure 5.5 HALT Flow Chart
ST52T430/E430
6 I/O PORTS
6.1 IntroductionST52x430 devices feature flexible individually
programmable multi-functional input/output lines.
Refer to the following figure for specific pin
allocations.
23 I/O lines, grouped in 3 different ports are
available on the ST52x430:
PORT A = 7 or 8-bit ports (PA0 - PA7 pins)
PORT B = 7 or 8-bit ports (PB0 - PB7 pins)
PORT C = 8-bit port (PC0 - PC7 pins)PIN 24 in the SO34 or PIN 22 in the PDIP32 can be
configured to belong to port A or to port B.
These I/O lines can be programmed to provide
digital input/output and analog input, or to connect
input/output signals to the on-chip peripherals as
alternate pin functions.
Input buffers are TTL compatible with Schmitt
trigger in port A and C while port B is CMOS
compatible without Schmitt trigger.
The output buffer can supply up to 8 mA.
The port cannot be configured to be used
contemporaneously as input and output.
Figure 6.1 Ports A & C Functional Blocks Each port is configured by using two configuration
registers. The first is used to determine if a pin is
an input or output, while the second defines the
Alternate functions.
6.2 Input ModeThe input configuration is selected by setting the
corresponding configuration register bit to “1”
(REG_CONF 4, 13 and 15) (see paragraph I/O
Port Configuration Registers). The ports are
configured by using the configuration registers
illustrated in the following table.
Digital input data is automatically stored in the
Input Registers, but it cannot be read directly. In
order to read a single bit of the IR its value must be
copied in a RAM location. Digital data is stored in a
RAM location by using the assembler instruction:
LDRI RAM_Reg Input_i
Table 6.1 I/O Port Configuration Registers.
ST52T430/E430
Figure 6.2 Port B Functional Blocks
6.3 Output ModeThe output configuration is selected by setting the
corresponding configuration register bit to “0”
(REG_CONF 4, 13 and 15) (see paragraph I/O
Port Configuration Registers).
Digital data is transferred to the related I/O Port by
means of the Output register via the assembler
instructions LDPE or LDPR.
6.4 Alternate FunctionsSeveral ST52x430 pins are configurable to be
used with different functions (see Table 1.1).
When an on-chip peripheral is configured to use a
pin, the correct I/O mode of the related pin must be
selected.
For example: if pin 26 (PA5/T0CLK in the SO34)
has to be used as an external PWM/Timer0 clock,
the Reg_Conf 4(5) bit must be set to ‘1’.
When the signal is an on-chip peripheral input the
related I/O pin has to be configured in Input Mode.
When a pin is used as an A/D Converter input the
related I/O pin is automatically set in tristate. The
analog multiplexer (controlled by the A/D
configuration Register) switches the analog
voltage present on the selected pin to the common
analog rail, which is connected to the ADC input.
It is recommended that the voltage level not be
changed or that any port pins not be loaded while
conversion is running. Furthermore, it is
recommended that clocking pins not be located
close to a selected analog pin.
6.5 I/O Port Configuration RegistersThe I/O mode for each bit of the three ports is
selected by using the Configuration Registers 4,
Table 6.2 Input Register and I/O Ports
Table 6.3 Output Register and I/O Ports
ST52T430/E43013 and 15 (See Table 6.1) The structure of these
registers is illustrated in the following tables.
Each bit of the configuration registers determines
the I/O mode of the related port pin.
Table 6.4 Ports A REG_CONF 4
Table 6.5 Ports B REG_CONF 13
ST52T430/E430
Analog Input Option. The PB0-PB7 pins can beconfigured to be analog inputs according to the
codes programmed in the configuration register
REG_CONF 14 (See Table 6.7). These analog
inputs are connected to the on-chip 8-bit Analog to
Digital Converter.
Table 6.6 Port C REG_CONF 15
Table 6.7 Analog Inputs (REG_CONF 14)
ST52T430/E430
PWM/Timers Alternate Functions The pins of Port A and C can be configured to be I/ of the three PWM/Timers available on the
ST52x430. The configuration of these pins is
performed by using the Configuration Registers
REG_CONF 12 and REG_CONF 16 if the related
pin has to be output. When the related pin has to
be used as an input peripheral the configuration is
performed by the relative peripheral configuration
registers (See PWM/Timer Session).
Table 6.8 PWM/Timers REG_CONF 16
Table 6.9 PWM/Timers REG_CONF 12
ST52T430/E430
Figure 6.3 Configuration Register 12
Figure 6.4 Configuration Register 16
ST52T430/E430
7 FUZZY COMPUTATION (DP)The ST52T430/E430 Decision Processor (DP)
main features are: Up to 8 Inputs with 8-bit resolution; 1 Kbyte of Program/Data Memory available to
store more than 300 to Membership Functions
(Mbfs) for each Input; Up to 128 Outputs with 8-bit resolution; Possibility of processing fuzzy rules with an
UNLIMITED number of antecedents; UNLIMITED number of Rules and Fuzzy Blocks.
The limits on the number of Fuzzy Rules and
Fuzzy program blocks are only related to the
Program/Data Memory size.
7.1 Fuzzy Inference The block diagram shown in Figure 7.1 describes
the different steps performed during a Fuzzy
algorithm. The ST52T430/E430 Core allows for the
implementation of a Mamdani type fuzzy inference
with crisp consequents. Inputs for fuzzy inference
are stored in 8 dedicated Fuzzy input registers.
The LDFR instruction is used to set the Input Fuzzy
registers with values stored in the Register File.
The result of a Fuzzy inference is stored directly in
a location of the Register File.
7.2 Fuzzyfication PhaseIn this phase the intersection (alpha weight)
between the input values and the related Mbfs
(Figure 7.2) is performed.
Eight Fuzzy Input registers are available for Fuzzy
inferences.
Figure 7.1 Fuzzy Inference
Figure 7.2 Alpha Weight CalculationAfter loading the input values by using the LDFR
assembler instruction, the user can start the fuzzy
inference by using the FUZZY assembler
instruction. During fuzzyfication: input data is
transformed in the activation level (alpha weight) of
the Mbf’s.
7.3 Inference PhaseThe Inference Phase manages the alpha weights
obtained during the fuzzyfication phase to compute
the truth value (ω) for each rule.
This is a calculation of the maximum (for the OR
operator) and/or minimum (for the AND operator)
performed on alpha values according to the logical
connectives of Fuzzy Rules.
Several conditions may be linked together by
linguistic connectives AND/OR, NOT operators
and brackets.
The truth value ω and the related output singleton
are used by the Defuzzyfication phase, in order complete the inference calculation.
ST52T430/E430
Figure 7.3 Fuzzyfication
7.4 DefuzzyficationIn this phase the output crisp values are
determined by implementing the consequent part
of the rules.
Each consequent Singleton Xi is multiplied by its
weight values ωi, calculated by the Decision
processor, in order to compute the upper part of
the Defuzzyfication formula.
Each output value is obtained from the consequent
crisp values (Xi ) by carrying out the following
Defuzzyfication formula:
where:
i = identifies the current output variable = number of the active rules on the current
output
ωij = weight of the j-th singletonij = abscissa of the j-th singleton
The Decision Processor outputs are stored in the
RAM location i-th specified in the assembler
instruction OUT i.
7.5 Input Membership FunctionThe Decision Processor allows the management of
triangular Mbfs. In order to define an Mbf, three
different parameters must be stored on the
Program/Data Memory (see Figure 7.4): the vertex of the Mbf: V; the length of the left semi-base: LVD; the length of the right semi-base: RVD;
In order to reduce the size of the memory area and
the computational effort the vertical range of the
vertex is fixed between 0 and 15 (4 bits)
By using the previous memorization method
different kinds of triangular Membership Functions
may be stored. Figure 7.5 shows some examples
of valid Mbfs that can be defined in ST52T430/
E430.
Each Mbf is then defined storing 3 bytes in the first
Kbyte of the Program/Data Memory.
The Mbf is stored by using the following instruction:
MBF n_mbf lvd v rvdwhere:
n_mbf is a tag number that identifies the Mbf
lvd, v, and rvd are the parameters that describe the
Mbf’s shape as described above.
Figure 7.4 Mbfs Parametersiijωijij-------------------=
ST52T430/E430
Figure 7.5 Example of valid Mbfs
7.6 Output SingletonThe Decision Processor uses a particular kind of
membership function called Singleton for its output
variables. A Singleton doesn’t have a shape, like a
traditional Mbf, and is characterized by a single
point identified by the couple (X, w), where w is
calculated by the Inference Unit as described
earlier. Often, a Singleton is simply identified with
its Crisp Value X.
Figure 7.6 Output Membership Functions
7.7 Fuzzy RulesRules can have the following structures:
if A op B op C...........then Z
if (A op B) op (C op D op E...) ...........then Z
where op is one of the possible linguistic operators
(AND/OR)
In the first case the rule operators are managed
sequentially; in the second one, the priority of the
operator is fixed by the brackets.
Each rule is codified by using an instruction set, the
inference time for a rule with 4 antecedents and 1
consequent is about 3 microseconds at 20 MHz.
The Assembler Instruction Set used to manage the
Fuzzy operations is reported in the table below.
Table 7.1 Fuzzy Instructions Set
ST52T430/E430
Example 1: IF Input1 IS NOT Mbf1 AND Input4 is Mbf12 OR Input3 IS Mbf8 THEN Crisp1
is codified by the following instructions:
Example 2, the priority of the operator is fixed by the brackets:IF (Input3 IS Mbf1 AND Input4 IS NOT Mbf15 ) OR (Input1 IS Mbf6 OR Input6 IS NOT Mbf14 ) THEN Crisp2
At the end of the fuzzy rule, by using the instruction OUT RAM_reg, a byte is written. Afterwards, the
control of the algorithm returns to the CU.
LDN 1 1 calculates the NOT α value of Input1 with Mbf1 and stores the result in internal registers
LDP 4 12 fixes the α value of Input4 with Mbf12 and stores the result in internal registers
FZAND implements the operation AND between the results obtained with the previous instructions
LDK stores the result of the previous operation in internal DPU registers
LDP 3 8 fixes the α value of Input3 with Mbf8 and stores the result in internal registers
FZOR implements the operation OR between the results obtained with the previous instructions
CON crisp1 multiplies the result of the last Ω operation with the crisp value crisp1
LDP 3 1 fixes the α value of Input3 with Mbf1 and stores the result in internal registers
LDN 4 15 calculates the NOT α value of Input4 with Mbf15 and stores the result in internal registers
FZAND implements the operation AND between the results obtained with the previous instructions
SKM stores the result of the previous operation in register M
LDP 1 6 fixes the α value of Input1 with Mbf6 and stores the result in internal registers
LDN 2 14 calculates the NOT α value of Input6 with Mbf14 and stores the result in internal registers
FZOR implements the operation OR between the results obtained with the previous instructions
LDK stores the result of the previous operation in internal DPU registers
LDM copies the value of the register M in internal DPU registers
FZOR implements the operation OR between the last two values stored in DPU registers
CON crisp2 multiplies the result of the last Ω operation with the crisp value crisp2
ST52T430/E430
8 A/D CONVERTER
8.1 IntroductionThe A/D Converter of ST52x430 is an 8-bit analog
to digital converter with up to 8 analog inputs
offering 8 bit resolution with a total accuracy of 1
LSB and a typical conversion time of 8.2 µs with a
20 MHz clock. This period also includes the 5.1 µs
of the integral Sample and Hold circuitry, which
minimizes the need for external components and
allows quick sampling of the signal for a minimum
warping effect and Integral conversion error.
Conversion is performed in 82 A/D clock
pulses.The A/D clock is derived from the clock master.
The maximum A/D clock frequency has to be 10
MHz. When the master clock is higher than 10
MHz it has to be divided by 2 using the SCK bit of
the A/D configuration register REG_CONF 3 (See
Table 8.1).
The A/D peripheral converts the input voltage with
a process of successive approximations using a
fixed clock frequency derived from the oscillator.
The conversion range is between the analog and V references.precision performance, along with one separate
supply (V DDA ), allowing the best supply noise
rejection.
Up to 8 multiplexed Analog Inputs are available. A
group of signals can be converted sequentially by
simply programming the starting address of the
last analog channel to be converted.
Single or continuous conversion mode are
available.
The result of the conversion is stored in an 8-bit
Input Register (from IR 1 to IR 8).
The A/D converter is controlled via the
Configuration Register REG_CONF 3.
A Power-Down programmable bit allows the A/D
converter to be set to a minimum consumption idle
status.
The ST52x430 Interrupt Unit provides one
maskable channel for the End of Conversion
(EOC).
8.2 Operational DescriptionThe conversion is monotonic, meaning that the
result never decreases if the analog input doesn’t
