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ST52T301/P |ST52T301PSTN/a579avai8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER


ST52T301/P ,8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVERGENERAL DESCRIPTIONStandard TTL compatible input(1) (1)ST52E301 and ST52T301 devices areCMOS compat ..
ST52T420G0B6 ,8-BIT INTELLIGENT CONTROLLER UNIT ICU Three Timer/PWMs, ADC, WDGFunctional Description . ...... ....... ...... ....... ...... ....... ...... ...... ......71.2.1 Me ..
ST52T430K3B6 ,8-BIT INTELLIGENT CONTROLLER UNIT ICU Three Timer/PWMs, ADC, SCIGENERAL DESCRIPTION A Serial Communication peripheral (SCI), whichuses the UART protocol allows dat ..
ST52T430K3M6 ,8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Three Timer/PWMs, ADC, SCIFunctional Description . .51.2.1 Memory Programming Mode 51.2.2 Working mode . ..
ST52T440G3B6 ,8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDGTABLE OF CONTENTS1GENERALDESCRIPTION..... 71.1 Introduction.... ...... ...... ....... ...... ...... ..
ST5382 , BROADBAND ACCESS: xDSL, HPN, CMCs
STN3904 , NPN Silicon Transistor
STN3904 , NPN Silicon Transistor
STN3906 , PNP Silicon Transistor
STN3906 , PNP Silicon Transistor
STN3906SF , PNP Silicon Transistor
STN3NE06 ,N-CHANNEL 60V


ST52T301/P
8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER
ST52T301/E3018-Bit OTP/EPROM DuaLogic MCUs WITH ADC,
UART, TIMER, TRIAC& PWM DRIVER
ADVANCED DATA SHEET

High Speed dedicatedstructures forFuzzyLogic
(3.5μsto computea4Inx1 Outrule)
Capabilityto perform simple boolean and
arithmetic operations to4 Input,2 OutputConfigurableVariablesfor
each Fuzzy Algorithm andupto 300 Rulesto16 Triangularand TrapezoidalMembership
Functionsfor each Input variableto 256 Singleton Membership Functionsfor
all Consequents
Program and Data EPROM:2 Kbytes general purpose registers available as
Register File
Working Clock Frequencies:5,10 and 20MHz
On-Chip Clock Oscillator driven by Quartz
Crystalor Ceramic Resonator
One external interrupt
Standard TTL compatible input
CMOS compatible output channel8bit Analogto DigitalConverter
Bandgap reference 2.5V
Digital8bit I/O port indepedentlyprogrammable
with handshake signal
Serial Communicat ion Interface with
asynchronousprotocol (UART)
Programmable Timer withinternal Prescaler
Internal Power Fuzzy Controlto drive external
Triac (upto 25mA source,50 mA sink current)
Internal Fuzzy controlled PWMto drive an
external powerdevice
Software tools and Emulators availability
Windowed and One Time Programmable(OTP)
Memory parts available for prototyping and
production phases pin Plastic (PLCC44) and Ceramic Windowed
Leaded Chip Carrier (CLCC44-W)
July 1998
CLCC44-W
PLCC44
1.1 GENERAL DESCRIPTION

ST52E301(1) and ST52T301(1) devices are
membersof the W.A.R.P .familyof 8-bitDuaLogic
microcontrollers. They are ableto perform,in an
efficientway,both booleanand fuzzyalgorithms,in
orderto reach the best performances that the two
methodologies allow.
TheST52E301is theerasableEPROMversionand
the ST52T301is the OTPversion.
The ST52x301is completely developed and
producedby STMicroelectronics using the reliable
high performance CMOSM5E (O.7μm) process.
Thanksto Fuzzy Logic, ST52x301 allowsto
describea problemusinga linguisticmodelinstead
ofa mathematicalmodel.In thiswayitis veryuseful
and easyto modelize complex system with very
high accuracy.
The linguistic approachis based ona setof
IF-THEN rules, describing the control behaviour,
andon Membership Functions associatedto input
and output variables.
Fuzzy Inferenceisa setof operations which
computes the output values according with the
truth valuesof the involvedrules.
Note: (1)Formerly W.A.R.P.3TC
1/99
The flexible I/O configurationof ST52x301 allows interface witha wide rangeof external devices,
like D/A converters, power control devices (SCRs,
TRIACs) and external sensors.
The OTP (One Time Programmable) deviceis fully
compatible with the EPROM windowed version,
which may be usedto create prototype systems
andfor the pre-production phases.
The Fuzzy Core includes the fuzzifier (ALPHA
calculator),the inferenceunit and the defuzzifier. allowsto manage upto 300 Rules(4 Inputs and Output).The rules could be sharedin different
fuzzy subroutines that can be activatedby user
defined conditions.
The I/O capabilities, demanded from
microcontroller applications, are fulfilled by
ST52x301 with4 Analog Inputs,an asynchronous
Peripheral interface (UART) and an 8-bit I/O
communicationportinorderto transferdatafrom/to
the on-chip Register File.
The voltage reference provides biasingto the
analog portionof the internal circuitry. The internal
referenceisa 2.5V Bandgapreference.
The voltage reference can supplyupto 0.1 mAof
currentto power external circuitry.
ST52x301 includesan 8-bit sampling Analogto
Digital (A/D) Converter witha4 analog
channel fast multiplexer (32μs conversion
time/channel).is possibleto perform operationson data stored the Register File (16 bytes), allowingto manage
new inputs and feedback outputs.
The TRIAC/PWM Driver peripheral allowsto
manage directly power devices, implementing
three different operating modes: Burst Mode
(i.e.Thermal Applica tion s), PhaseA ngle
Partialization (i.e. Motors Controlby TRIACs) and
high frequency PWM controls. programmable Timer with Internal Prescaler,
using both internalor externalclock,is available.
The microcontroller configurationis storedin the
internal EPROM. powerful development environment,
FUZZYSTUDIO 3.0, consistingofa boardds oft waret ools,all ows an easy
configuration and useof ST52x301. 52x301 is fully sup port ed by
FUZZYSTUDIO3.0so ftware tools allowing graphically designa project and obtainan
optimized microcode.
ST52x301 exploitsa SGS-THOMSON patented
strategyto store the MFsinits internal memory.
OSCILLATOR
ALU
FUZZY
CORE
SYSTEM
REGISTERS
CONTROL
UNIT
REGISTER
FILE
PARALLEL
I/O PORT
2kBytes
EPROM
TRIAC/PWM
DRIVER
PROG.TIMER
WITH
PRESCALER
SCI
A/D
CONVERTER
BAND-GAP
REFERENCE

Figure1. ST52x301Architectural Block Diagram
2/99
ST52T301/E301
Figure 2.CLCC44-W Pin Configuration
Figure3. PLCC44 Pin Configuration
3/99
ST52T301/E301
PIN NAME TYPE Programming Phase Working Phase not connected - - AVDD Analog VDD Analog VDD AVSS Analog Ground Analog Ground EVDD EPROM Digital Power Supply EPROM Digital Power Supply EVSS EPROM Digital Ground EPROM Digital Ground VPP EPROM Programming
Power supply (12V ±5%) EPROM VDD (5V ±10%) VDD Digital Power Supply Digital Power Supply VSS Digital Ground Digital Ground P0 I/O I/O EPROM Data DigitalI/O P1 I/O I/O EPROM Data DigitalI/O P2 I/O I/O EPROM Data DigitalI/O P3 I/O I/O EPROM Data DigitalI/O P4 I/O I/O EPROM Data DigitalI/O P5 I/O I/O EPROM Data DigitalI/O P6 I/O I/O EPROM Data DigitalI/O P7 I/O I/O EPROM Data DigitalI/O READY O I/O port Handshaking Signal P8 O Digital Output TEST I (mustbesetto0) (mustbesetto0) MAIN2 I/O Zero Crossing/Prescaler Output MAIN1 I Zero Crossing VDD Digital Power Supply Digital Power Supply VSS Digital Ground Digital Ground TRIACOUT O Triac/PWM Driver Output Pulses MODE I Functionment Mode Selector Functionment Mode Selector RESET I General Reset General Reset CE/INT I Chip Enable EPROM External Interrupt TIMEROUT O Output Timer ERES/ TRES I EPROM Address Counter Reset External Timer Reset OE/ TCTRL I EPROM Output Enable Timer Start/Stop Signal OSCout I/O Oscillator Output Oscillator Output OSCin I Oscillator Input Oscillator Input CADD/ TCLK I EPROM Change Address Clock Timer External Clock VSS Digital Ground Digital Ground VDD Digital Power Supply Digital Power Supply TxD O SCI Output RxD I SCI Input not connected - - not connected - - AIN3 Ainp Analog Input AIN2 Ainp Analog Input AIN1 Ainp Analog Input AIN0 Ainp Analog Input BG Aout Band Gap Output
Table1. PLCC44 and CLCC44-W Pin Configuration
4/99
ST52T301/E301
1.2 PIN DESCRIPTION
VDD,EVDD,VSS, EVSS,AVDD,AVSS, VPP.
In orderto
avoid noise disturbances,the power supplyof the
digitalpartis kept separated from thepowersupply the analog part.
VDD.
Main Power Supply Voltage (5V 10%).
VSS.Digital
circuit Ground.
EVDD.
EPROM Main Power Supply Voltage (5V
10%).
EVSS.
EPROM Digital circuit Ground.
AVDD.
Analog VDD of the Analog to Digital
Converter.
AVSS.AnalogVSS
of theAnalogtoDigitalConverter.
Mustbe tiedto VSS.
VPP.
Main Power Supply for the internal EPROM
(12.5V 5%).
OSCin
and OSCout. These pins are internally
connected with the on-chip oscillator circuit.A
quartz crystalora ceramic resonator can be
connectedbetween these twopinsin ordertoallow
the correct operationsof ST52x301 with various
stability/cost trade-offs. An external clock signal
canbe appliedto OSCin,in thiscase OSCoutmust grounded.
RESET.
This signalis usedto restart ST52x301at
thebeginningof itsprogram.It alsoallowsto select
the program modefor the EPROM.
INT.
External interrupt active on risingor falling
edge.
AIN0-AIN3.
These4 lines are connectedto the
inputsof the analog multiplexer. They allowto
acquire4 analog inputs.
BG.A
Voltageequalto 2.5Vis availableon this pin. canbe usedfor Analog signal conditioning.
P0-P7.These8
linesareorganizedas oneI/O port.
During the Programming phase such portis used
for the EPROM data read/write.
READY.
Handshake signalof the parallel port.
P8.
Digital output.
TxD.
Serial data outputof the SCI transmitter
block.
RxD.
Serial data input of the SCI receiver
block.
TRES, TCLK,TCTRL, TIMEROUT.These
pins are
related with the internal ProgrammableTimer. The
Timer canbe reset externallyby using TRES.In
Working Mode, TRES resets the address counter the Timer. TRESis activeat low level
The Timer Clock canbe the internal clockor can supplied externallyby using the pin TCLK.
AnexternalStart/Stopsignalcan beusedto control
theTimer throughthe pinTCTRL.The Timeroutput availableon the pin TIMEROUT.
MAIN1, MAIN2, TRIACOUT.
ST52x301is ableto
drivea TRIACin two different modes: Burst mode Phase Angle Partialization control mode.
The Burst modeis usedfor thermal regulation.
MAIN1 and MAIN2 signals are usedto detect the
zero crossingof the main voltage.
Thepulseto drivetheTRIACis givenbyTRIACOUT
pin.is possibleto use the same pinsto implementa
PWM Driver.In this caseitis possibletofix the
periodof PWMandto changethe duty cycleonfly.
The PWM outputis givenby TRIACOUT pin.
CE, OE, ERES, CADD, VPP.
These pins are used manage the EPROM during the Programming
phase. Duringthe Programming phase
(programming) VPP must be setat 12V.In the
Working phase VPP mustbe equalto VDD.
ERESin Programming Mode resets the address
counterof the EPROM;itis activeat high level. the Workingphase OE,CE and CADDare used
like handshaking signalsfor the parallel port.
MODE.
It selectsthe functionment mode
(Programmingor Working mode).
TEST.
It enables the testing functionalities;during
the Programmingand Working phaseit must beset0.
5/99
ST52T301/E301
INTERNAL ARCHITECTUREST52x301is madeupby the following blocks and
peripherals:
Control Unit
Fuzzy Core
ALU
EPROM
Clock Oscillator
Analog Multiplexer and A/D Converter
PrescalerTimer
Bandgap
Triac/ PWM Driver
Digital I/O port
Serial Communication Interface
ST52x301 Operating Modes

ST52x301 worksin two modes, Programming and
Working Modes, dependingon the control signals
levelRESET, TEST and MODE.
The Operating modes are selectedby setting the
control signal level as specifiedin the Control
Signals Setting table.
2.1 CONTROL UNIT

The Control Unit (CU) manages: Registers File,
Input Registers, Configuration Registers, ALU,
Accumulator and Multiplexer inputs. Moreover the drives the Fuzzy Core and the peripherals riac/PWM Driver andTimer).
The CU reads the stored instructions on the
EPROM (Fetch) and decodifies them.If the
instructions are arithmeticor logic, the CU runs
them directly, sending the control signalsto the
related blocks.If thereisa STOP instruction, the transfers the controlto the Fuzzy Core.
The Fuzzy Core (FC) will read the next instruction
(thatmustbea fuzzyinstruction)from the EPROM.
The FC mantains the controlof the program until
the next STOP instruction. Then the FC transfers
the controlto the CU.
Thesecharacteristicsallowto mix fuzzy algorithms
with mathematical and logic instructions.
Figure 2.1 showsa flow-chart reasuming the logic
behaviourof the instructions management.
Control
Signal Programming Reset Working

RESET 00 1
TEST 00 0
MODE 10 0
Table 2.1. Control Signals setting
Readsfromthe EPROM
and
Decodifiestheinstruction
executesinstruction
FuzzyCore
Readsfromthe EPROM
and
Decodifiestheinstruction
STOP
STOP Fuzzy Core
executesinstruction
Yes
Yes

Figure 2.1. Computation Algorithm Flow Chart
6/99
ST52T301/E301
BITA/D CONVERTER
EPROM KBytes
TIMER
TRES
TCLK
TIMEROUT
FUZZY CORE
I/O
PARALLEL PORT
P0..P7
AIN0..AIN3
POWER SUPPLY OSCILLATOR RESET
TRIAC/PWM
DRIVER
MAIN1
MAIN2
TRIACOUT
CONTROL
UNIT
RESETOSCinVSSVDD
ALUPC
RegisterFileInput
Registers
INP_PORT
SCI_IN
SCI_ST
FUZZY_OUT_0
FUZZY_OUT_1
ADC_OUT_0
ADC_OUT_1
ADC_OUT_2
ADC_OUT_3
TMR_OUT
TMR_ADC_ST
VPP
Reg0
Reg15
Reg1
REG_CONF0
REG_CONF15
REG_CONF1
Configuration
Registers
SCI
(UART)
TxD
TCTRL
RxD
FLAGS
READY
OSCout
Peripheral
Register
PERIPH_REG_0
PERIPH_REG_1
PERIPH_REG_2
Figure 2.2. ST52x301 Block Diagram
7/99
ST52T301/E301
isnot possibileto stopthe fuzzy inference beforetheendof the defuzzificationof one output.Asetof different arithmetic and logic instructionsis
available.Eachinstruction requiresfrom4 to7 clock
pulsestobe performed.
2.1.1 Program Counter

The Program Counter(PC)isa 11-bit register that
contains the addressof the next memory locationbe processed bythe core.This memory location
maybe anopcode,an operandoran addressofan
operand.
The 11-bit length allows the direct addressing
modeof 2048 bytesin the programspace.
After having read the current instruction address,
the PC valueis incremented.To execute relative
jumps the PC and theoffset are shiftedthrough the
Fuzzy Coreor the ALU, where they willbe added.
The resultof this operationis shifted back into the
PC.
The PC canbe changedin the following ways: (Jump) instruction PC= Jump Address
Interrupt PC= InterruptVector
RETI instruction PC= Pop (stack)
Reset PC= Reset Vector
Normal Instruction PC= PC+1
2.1.2 Flags

The ST52x301core includestwo pairsof flagsthat
correspondto2 differentmodes:normal mode and
interrupt mode. Each pair consistofa CARRY flag
anda ZERO flag.One pair (CN,ZN)is used during
normal operation and oneis used during the
interrupt mode (CI, ZI).
The ST52x301 core uses the pairof flags that
correspondto the actual mode: as soon as an
interruptis generated,the ST52x301core uses the
interrupt flagsinsteadof thenormal flags.Whenthe
RETI instructionis executed the normal flags are
restoredif the MCUwasin the normal modebefore
the interrupt.It shouldbe observed that each flag
set can onlybe addressedinits own routine.
The flags are not cleared during the context
switching and remainin the state theywereat the
exitof the last routine switching.
The Carry flagis set whena carryora borrow
occurs during arithmetic operations,otherwiseitis
cleared.
The switching between the two setsof flagsis
automatically performed when an interruptora
RETI instruction occur.
2.2 ADDRESS SPACES

W.A.R.P3TC has four separate address spaces:
Register File:16 8-bit registers
Input Registers:11 8-bit registers
Configuration Registers:16 8-bit registers
PeripheralRegisters:3 8-bit registers
Program memoryupto 2K Bytes
The Program memory willbe describedin further
detailin the MEMORYsection
2.2.1 Register File

The Register File (RF) consistsof 16 general
purpose 8-bit registersReg0to Reg15.
Allthe registersin theRF canbe specifiedby using decimal address,
e.g.0 identify the first registerof the RF, called
Reg0.
Reg0:3 are directly connectedto the FC input.It
means that the input valuesof the fuzzyalgorithm
mustbe loaded into these registersby the user.
These registers are usedas temporary registers
during the macros’computation.
8/99
ST52T301/E301
Input Registers ALU
LDRI
RegisterFile FUZZY
CORE
LDPR
LDRR
LDRC
LDCF
CORE ON-CHIP PERIPHERALS
Peripheral Registers
Configuration
Registers
Program Memory RIPHERAL
BLOCK
LDCF CRi,x
(1)
Figure 2.3. Address Spaces description
Register File
Reg0
Reg1
Reg2
Reg3
Reg4
Reg5
Reg6
Reg7
Reg8
Reg9
Reg10
Reg11
Reg12
Reg13
Reg14
Reg15
FUZZY_IN_0
FUZZY_IN_1
FUZZY_IN_2
FUZZY_IN_3
Free
Free
Free
Free
Free
Free
Free
Free
Free
Free
Fuzzy CoreRegister Description
Free
Free
Figure 2.4. Register File description
9/99
ST52T301/E301
Figure 2.5. Input Registers Bench description
2.2.2 Input Registers Bench

The Input Registers(IR)bench consistsof11 8-bit
registers containing data or status ofthe
peripherals.
Allthe registers can bespecifiedbyusinga decimal
address,e.g.0 identifies the first registerof the IR.
The first four registers (ADC_OUT_0:3)of theIR
are dedicatedto the4 converted values coming
from the ADC.
TMR_OUT registers contains the current counted
valueby the internal Timer; whereas TMR_STis
the Timer status. For details about TMR_ST,
please referto Timer description.
Data read by the Parallel I/O Port are stored
automaticallyin the 6-th register, INP_PORT.
Data readby the SCI are stored automaticallyin
the 7-th register SCI_IN and SCI statusis storedin
the SCI_ST register. For details about SCI_ST,
please referto SCI description.
TheFuzzyCore writesthe computed outputvalues the FUZZY_OUT_0:1 registers.
10/99
ST52T301/E301
Figure 2.6. TMR_ADC_ST Registers
Figure 2.7. SCI_ST Registers
11/99
ST52T301/E301
2.2.3 Configuration Registers
The ST52x301 setting permitsto configure all
blocks.T able2.2 describesthe relatedblocktoeach
bitof the Configuration Registers.
Use andmeaningof eachregisterwillbe described further detailsin the corresponding section.
Register Peripheral Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
REG_CONF0 PARALLEL
PORT
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
REG_CONF1 SCI, CORE,
I/O PORT
RDRF OVR BRK TDRE TXC ECKF P8 OUT
REG_CONF2 ADC not used IADD 1 ADRST
REG_CONF3 SCI BRSL T8 M RE TE
REG_CONF4 TIMER TMLSB
REG_CONF5 TIMER TMMSB
REG_CONF6 TIMER not used POL TMS CKSL TMEL IESL TMST TMRST
REG_CONF7 TIMER not used FZSL INPSL INTR INTF INTSL
REG_CONF8 TRIAC TCLSB
REG_CONF9 TRIAC TCMSB
REG_CONF10 TRIAC IOSL PSF CKSL MODE TCST TCRST
REG_CONF11 TRIAC INTSL TCMSK TCTRS POL
REG_CONF12 TRIAC FZSL INPSL UTPMSB
REG_CONF13 TRIAC UTPLSB
REG_CONF14 INTERRUPT EXTI not used MSKTC MSKTM MSKSCI MSKAD MSKE
REG_CONF15 INTERRUPT INT4 INT3 INT2 INT1 able 2.2. Configuration Registers description
12/99
ST52T301/E301
2.2.4 Peripheral Registers
Periph eral Registers contain the initialization
valuesfor the Timer,Triac/PWMDriver and Parallel
Port.
The peripheral initialization valueis kept froma
locationof the Register File, by usinga LDPR
instruction, or from FUZZY_OUT_0/1 Input
Register according with the related Configuration
Registers. able 2.3 describes the related peripheralto each
Configuration Register.
Use andmeaningof eachregisterwillbe described further detailsin the corresponding section.
Peripheral Register Peripheral

PERIPH_REG_0 Timer
PERIPH_REG_1 Triac/PWM Driver
PERIPH_REG_2 Parallel Port
Table 2.3. Peripheral Register description
13/99
ST52T301/E301
2.4 FUZZY CORE
ST52x301 Fuzzy Core main features are:to4 Inputs with 8-bit resolutionto16 Membership Functions(Mbfs)for each
Input (64 possible Mbfs)to2 Outputs with 8-bit resolution
Possibilityto process fuzzy rules witha max.
numberof8 antecedents
2.4.1 Internal Structure

The block diagram shownin figure 2.9 describes
thestructureofST52x301Fuzzy Core.In thisfigure candistinguishdifferentfunctionalblocks:Alpha
Calculator, Inference Unit and Defuzzifier. These
blocks allowto performa MAMDANI type fuzzy
inferencewith crisp consequents.Itis importantto
underline that the fuzzy inferenceis performedby
usingas inputs the first4 locationsof theRegisters
File.
2.4.2 Alpha Calculator Unit

Thisblock performs the intersection (alpha weight)
betweenthe input values and the related Mbfs(fig.
2.8).
InputValueij
j-thMbf
i-thINPUT VARIABLE
Figure 2.8. Alpha Weigth calculation
Figure 2.9. Fuzzy Core Block Diagram
Notice that the inputs for this block come from the
firstfour locationsof the Register File; itmeans the
user,to evaluatea fuzzy function, must load the
input valuesin these registers.
Alpha Calculator performs whatis called
fuzzification:
the input data are transformedin
activationlevel (alpha weight)of the Mbfs.
14/99
ST52T301/E301
2.4.3 Inference Unit managesthe alphaweights obtainedbythe Alpha
Calculator Unitto compute the truth value(ω) for
each rule.
Thisisa calculationof the maximum (for the OR
operator) and/or minimum (for the AND operator)
performedon alpha values accordingto the logical
connectivesof fuzzy rules.is possibileto link togetherupto eightconditions linguistic connectives AND/OR, NOT operator
and brackets.
Each rule can haveat maximum8 alpha weights
(however they are connected).
The truth valueω and the related output singleton
are passedto the Defuzzifierto complete the
inferencecalculation.
Input1X1

Input2X2
=Max INPUT1ISX1 OR INPUT2ISX2 THEN .......
Input1X1

Input2X2
INPUT1ISX1 AND INPUT2ISX2 THEN .......
Figure 2.10.
2.4.4 Defuzzifier

This block consistsofa Multiplier, two Adders and
one Divider.It generates the output crisp values
implementing the consequentpartof the rules. this phase each consequent SingletonXi is
multipliedbyits weightvaluesωi, calculatedby the
Inference Unitin orderto compute the upper part the defuzzification.
Each outputvalue (FUZZY_OUT0, FUZZY_OUT1) deduced from the consequentcrisp values (Xi) using the defuzzification formula:=Xijωij
∑ωij
where:= 0,1 identifies the current output variable numberof theactive ruleson thecurrent output
ωij =weigthof the j-th singleton
Xij= abscissaof the j-th singleton
The two fuzzy outputs are storedin the location9
and 10of the Input Registers (FUZZY_OUT_0,
FUZZY_OUT_1).
i-th OUTPUT
VARIABLE XXi0 Xini0ijin
j-th Singleton
Figure 2.11.
15/99
ST52T301/E301
2.4.5 Input Membership Function
ST52x301 allowsto manage triangular Mbfs.In
orderto definea Mbfitis necessaryto store three
different dataon the memory:
the vertexof the Mbf:V;
the lenghtof the left semi-base: LVD;
the lenghtof the right semi-base:RVD; orderto reduce the dimensionof the memory
area and the computational effort the vertical
dimensionof the vertexis fixedto15(4 bits) using the previous memorization methoditis
possibleto store different kindsof triangular
Memberships Functions.In the following figureis
showna typical exampleof Mbfs that can be
definedin ST52x301
Each Mbfis then defined storing3 bytes.To store
all the information related with the fuzzy project
Mbfs,itis necessaryto use 192 bytesof the
memory(3 bytes*16 Mbfs*4 Inputs= 192 bytes).
LVD RVD
InputMbf
OutputSingleton
OutputVariable
InputVariable
Figure 2.12.Mbfs Parameters Figure 2.13. Exampleof valid Mbfs
The Mbfis memorized by using the following
instruction:
DATAnm lvdv rvd
where identifies the input,m identifies the Mbf among
the16 possibleMbfs, lvd,v, rvd are the parameters
describing the Mbf’s shape.
2.4.6 Output Singleton

ST52x301uses fortheoutput variablesa particular
kindof membership function called Singleton.A
Singleton has nota shape, likea traditional Mbf,
anditis characterizedbya single point identified the couple (X, ω), where theωis calculatedby
the Inference Unitas described before.
Oftena Singletonis simply identified withits Crisp
ValueX.
16/99
ST52T301/E301
2.4.7 Fuzzy Rules.
The rules can have the following structures:AopBop C...........thenZ(AopB)op(CopDop E...) ...........thenZ
whereopis oneof the possiblelinguistic operators
(AND/OR) the first case the rule operators are managed
sequentially;in the second one, the priorityof the
operatoris fixedby the brakets.
Each ruleis codifiedby usingan istruction set, the
inference timefora rule with4 antecedents and1
consequentis about3 microseconds.
The assembler Instruction Set allowingto manage
the fuzzy instructions are reportedin the following
table:
Instruction Description

DATAnmlvdvrvd Storesthe Mbfmofthe inputn withthe shape identifiedby the parameters lvd,v and rvd.
LDPnm Fixesthe alpha valueofthe inputn withthe Mbfm and storesitin the data stack.
LDNnm Calculatesthe negated alpha valueof the inputn withthe Mbfm and store the resultin the data
stack.
FZAND Implementsthe fuzzy operationAND betweenthe last two valuesstoredin thedata stack.
FZOR Implementsthe fuzzy operationOR betweenthe last two values storedinthe data stack.
LDK Storesthe resultofthe last fuzzy operation executedin thedata stack.
SKM Storesthe resultofthe last fuzzy operation executedin thememory registerM.
LDM Copiesthe valueofthe registerMinthe data stack.
CON crisp Multiplies the crisp value withthe lastω weight.
OUT n_out Performsthe defuzzification.
STOP Endsthe fuzzy algorithm. able 2.4. Fuzzy Instructions Set
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Example1: Input1IS NOT Mbf1 AND Input4is Mbf12 OR Input3 IS Mbf8 THEN Crisp1 codifiedby the following instructions
LDN11
calculates the NOTα valueof Input1 with Mbf1 and stores the resultin the data stack
LDP412
fixes theα valueof Input4 withM12 and stores the resultin the data stack
FZAND
adds the NOTα andα values obtained with the operations LDN11 and LDP4 12
LDK
stores the resultof the operation FZANDin the data stack
LDP38
fixes theα valueof Input3 withMbf8 and stores the resultin the data stack
FZOR
implements the operation OR betweenthe results obtained with the operationsLDK
and LDP
CON crisp1
multiplies the resultof the last Ω operation with the crisp value Crisp1
Example2, the priorityof the operatoris fixedby the brakets: (Input3IS Mbf1 AND Input4IS NOT Mbf15) OR (Input1IS Mbf6 OR Input6IS NOT Mbf14) THEN Crisp2
LDP31
fixes theα valueof Input3 withMbf1 and stores the resultin the data stack
LDN415
calculates the NOT α valueof Input4 with Mbf15 and stores the resultin the data
stack
FZAND
adds NOTα andα values obtainedwith the operationsLDP31 and LDN4 15
SKM
stores the resultof the operation FZANDin the memory registerM
LDP16
fixes theα valueof Input1 withMbf6 and stores the resultin the data stack
LDN214
calculates the NOT α valueof Input6 with Mbf14 and stores the resultin the data
stack
FZOR
implements the operation OR betweenthe α and NOTα values obtained with the
twoprevious operations(LDP16 and LDN2 14)
LDK
stores the resultof the operation ORin the data stack
LDM
copies the valueof the memory registerMin the data stack
FZOR
implements the operation OR betweenthe last two values storedin the data stack
(LDK and LDM)
CON crips2
multiplies the resultof the last Ω operation with the crisp value Crip2 the endof the fuzzy rules seta byte,to identify
the output involvedin the rules, and the STOP
istruction mustbe inserted.
When the STOP instructionis performed, the
controlof the algorithm goes backto the CU.
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2.5 ARITHMETIC LOGIC UNIT
The 8-bit Arithmetic Logic Unit (ALU) allowsto
perform arithmetic calcu lations and logic
instructions which can be divided into4 groups:
Load, Arithmetic, Jump and Program Control
instructions (referto the ST52x301 Assembler Set
for further details).
Load Instructions
Menmonic Instruction Bytes Cycles Z S

LDCF LDCF conf, const 2 6 - -
LDRC LDRC reg, const 2 6 - -
LDRI LDRI reg,inp 2 6 - -
LDPR LDPR per,reg 1 6 - -
LDRR LDRR regi,regj 2 6 - -
Arithmetic Instructions
Mnemonic Instruction Bytes Cycles Z S

ADD ADD regi, regj 2 7 I I
AND AND regi, regj 2 7 I -
SUB SUB regi, regj 2 7 I I
SUBO SUBO regi, regj 2 7 I I
Jump Instructions
Mnemonic Instruction Bytes Cycles Z S
JP addr 2 6 - -
JPNS JPNS addr 2 6 - -
JPNZ JPNZ addr 2 6 - -
JPS JPS addr 2 6 - -
JPZ JPZ addr 2 6 - -
SCI Instructions
Mnemonic Instruction Bytes Cycles Z S

SRX SRX regi 2 5 - -
STX STX regi 2 5 - -
Notes: affected not affected able 2.5. Arithmetic& Logic Instructions Set
The computational time required for each
instruction consistsof one clock pulse for each
Cycle plus3 clock pulsesfor the decoding phase.
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Program Control Instructions
Mnemonic Instruction Bytes Cycles Z S

RETI RETI 1 5 I I
RINT RINTint 1 4 - -
STOP STOP 1 4 - -
WAITI WAITI 1 4 - -
UDGI UDGI 1 4 - -
UEGI UEGI 1 4 - -
MDGI MDGI 1 4 - -
MEGI MEGI 1 4 - -
IRQ IRQint label 2 6 - -
IRQM IRQM mask 2 6 - -
IRQP IRQP cost 2 6 - -
Notes: affected not affected able 2.6. Arithmetic& Logic Instructions Set (Continue)
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EPROMThe EPROM memory provides an on-chip
user-programmable non-volatile memory, that
allows fast and reliable storageof user data.
There are 16K bitsof memory space withan 8-bit
internal parallelism (2Kbytes) addressed by an
11-bit bus.The data busisof8 bits.
The memory hasa double supply: VPPis equalto
12V±5%in Programming Phase and 5V±10%
duringWorking Phase.VDDis equalto 5V±10%.
The EPROM memoryof ST52x301is dividedin
three main blocks (see Figure 3.1):
Mbfs Setting with(0 through 191) contains the
coordinatesof the vertexesof every Mbf defined the program.
Interrupt Vectors (192 through 201) contain the
addressesfor the interrupt routines.
Each addressis composedof two bytes.
Program Instruction Set (202 through 2048)
contains the instructionsetof the user program. canbe composedof more Boolean and Fuzzy
Algorithms
The operation that can be performed, during
Programming Phase,on the EPROM are: Writing,
Verify, Writing Inhibit, Standbyand Erasing.
Figure 3.2 sh ows the signalst iming in
Programming Mode.
Mbfs Setting
InterruptVectors
Program
InstructionsSet
Boolean Algorithm
Boolean Algorithm
Fuzzy Algorithm
Fuzzy Algorithm····
INT_EXT
INT_TRIAC
INT_TIMER
INT_SCI
INT_ADC
MbfParameters
Figure 3.1. Memory Map
3.1 EPROM ProgrammingPhase Procedure

Programming modeis selected by applying
12V±5% voltageto the VPP pin and set the control
signalas following:
RESET:0, TEST:0, MODE:1.
CADD, ERES, OE and CE are the control signals
used during the Programming Mode. CADDis
activeon edge,the others are activeon level (OE, are active low, ERESis active high).
3.1.1EPROM Writing

When the memoryis blank,all the bits areat logic
level ”1”. The data are introducedby programming
only the zerosin the desired memory location;
howeverall input data must contain both ”1” and
”0”.
Theonly wayto change”0” into”1”isto erase the
whole memory( by exposureto Ultra Violet light)
and reprogramit.
The memoryisin Writing mode when:= LOW= HIGH
with stable dataon the data bus P(0:7).
The total programming pulse width (CE=0V)is,
typically,50μs (by meansof 5pulsesof10 μs), but
beforeactivating such pulse,itis suggestedto wait
forat least2 μs after VPP risesat 12V. After the
disactivationof the pulseitis suggestedto waitfor
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least2 μs before updating the data and theaddress.
The data updating for the next programmingis
performed, directly by the user,on the data bus
P(0:7) while the addressis incremented through
the pin CADD.
3.1.2 EPROM Verify
Verify modeis availablein orderto verify the
correctnessof the data written.Itis possibleto
activate the Verify mode immediately after the
writingof each byte:= HIGH= LOW
Then,if any errorin writing occured, the user has repeat the EPROMwriting.
The data, during this phase, are avalaibleon the
bus P(0:7)
3.1.3 Writing Inhibit
occurs between the Writing and Verify Mode:= HIGH= HIGH
3.1.4 Standby Mode

The EPROM hasa standby mode which reduces
theactive current from10mA(Programming mode) less than 100 μA. The Memoryis placedin
standby modeby setting CEat HIGH Logic Level
(VPP mightbe equalto5V too). Whenin standby
mode, the outputs arein high impedance state.
3.2 Eprom Erasure

Thanksto the transparent window presentin the
CLCC44-W package,its memory contentsmaybe
erasedby exposureto UV light.
Erasure begins when thedevice isexposedto light
witha wavelengthshorter than 4000Å.It shouldbe
noted that sunlight, as well as some typesof
artificial light, includes wavelengthsin the
3000-4000Årange which,on prolonged exposure,
can cause erasureof memory contents.Itis thus
recommended that EPROM devicesbe fitted with opaque label over the window areain orderto
prevent unintentionalerasure.
The recommended erasure procedure forEPROM
devicesconsistsof exposureto shortwave UV light
havinga wavelengthof 2537Å. The minimum
recommended integrated dose (intensityx
expo-sure time) for complete erasureis
15Wsec/cm2.
Thisis equivalentto an erasure timeof 15-20
minutes usinga UV source havingan intensityof
12mW/cm2ata distanceof 25mm(1 inch) from
the device window.
P(0:7) DATAIN
VPP
12V
Inhibit
min2us
2ustyp.
DATA OUT
RESET
CADD
Writing Verify
ERES
INPUT
PORT
50ustyp.
OUTPUT
PORT3us min.
Figure 3.2. EPROM Programming Timing
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INTERRUPTSThe Control Unit (CU) respondsto peripheral
events and external events through its interrupt
channels.
When suchan event occurs,ifit isnot maskedand
accordingtoa priority order, the current program
execution can be suspendedto allow the CUto
executea specific response routine.
Eachinterrupt isassociated withan interruptvector
that contains the memory addressof the related
interrupt service routine. Each vectoris locatedin
the Program Space (EPROM Memory)ata fixed
address(see Interrupt Vectors table fig.4.2).
4.1 Interrupt Functionment

If,at the endofan arithmeticor logic instruction,
there are pending interrupts, the one with the
highest priorityis passed.To pass an interrupt
meansto storethe arithmeticflags and the currentin the stack and execute the associated
Interrupt routine, whose addressis locatedin one the EPROM memory location between address
192 and 201.
TheInterruptroutineis performedasa normalcode
checking,at the endof eachinstruction,ifa higher
priority interrupt hasto be passed. An Interrupt
request with the higher priority stops the lower
priority Interrupt. The Program Counter and the
arithmetic flags are storedin the stack.
With the instruction RETI (Return from Interrupt)
thearithmetic flags and ProgramCounter (PC)are
restored from the topof the stack.This stack, used
for the Interrupt priority,isa LIFO queue. Interrupt request cannotstop the processingof
the fuzzy rules but thisis passed only after the
definitionof the fuzzyoutputor atthe endofa logic arithmeticinstruction.
4.2 Global Interrupt Request Enabling

When an Interrupt occurs,it generatesa Global
Interrupt Pending(GIP), that canbe hangedupby
software. Aftera GIPa Global Interrupt Request
(GIR) will be generate and Interrupt Service
Routine associatedto the interrupt with higher
priority will start. orderto avoid possible conflicts between
interrupt maskingset inthemain programor inside
macros, the GIPis hangedup through the User
GlobalInterrup Maskor the Macro Global Interrup
Mask (see fig.4.3).
UEGI/UDGI instruction switches on/off the User
GlobalInterrupMaskenabling/disablingtheGIRfor
the main program.
MEGI/MDGI instructions set the Macro Global
InterruptMaskinorderto assurethat the macrowill
notbe broken.
NORMAL
PROGRAM
FLOW
INTERRUPT
SERVICE
ROUTINE
RETI
INSTRUCTION
INTERRUPT
Figure 4.1.Interrupt Flow
InterruptVectorsINT_TIMER
INT_SCI
INT_ADC
INT_TRIAC
INT_EXT
Figure 4.2.Interrupt Vectors Mapping
Global Interrupt
Pending
User Global
InterruptMask
Macro Global
InterruptMask
Global Interrupt
Request
Figure 4.3.Global Interrupt Request generation
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4.3 Interrupt Sources
ST52x301manages interrupt signals generatedby
the internal peripherals (Timer, Triac/PWM
Driver,Analogto Digital Converter and Serial
Communication Port)or coming from the INT pin.
The polarity ofthe ExternalI nterruptis
programmedby the EXTIbitof the REG_CONF14
(see Table 4.1 and fig. 4.4). EXTI=0 means that
INT_EXTis active on rising edge, otherwiseitis
activeon falling edge.
Each peripheral can be programmedin orderto
generate the associate interrupt;further detailsare
describedin the related chapter.
4.4 Interrupt Maskability

The interrupts canbe maskedby configuring the
REG_CONF14.The interruptis enabledwhen the
bit associatedto the mask interruptis ”1”.
Viceversa, when the bitis ”0”, the interruptis
maskedandis kept pendent.
For exampleLDCF 14,6
(CONF_REG14 =00000110) enables interrupts
comingfromthe ADC(INT_ADC) and from the SCI
(INT_SCI).
4.5 Interrupt Priority

Six priority levels are available: level5 has the
lowest priority, level0 has the highest priority.
Level5is associatedto the MainProgram, levels41 are programmableby meansof the priority
register called REG_CONF15 (see fig.4.5);
whereas the higher levelis relatedto the external
interrupt (INT_EXT).
Timer, Triac/PWM Driver, SCI and ADC are
identifiedbya two bits Peripheral Code (see Table
4.2);in orderto set the i-th priority level the user
must write the peripheral labeliin the related INTi
priority level.
Bit Name Value Description MSKE External Interrupt
Masked External Interrupt
Not Masked MSKAD A/D Converter Interrupt
Masked A/D Converter Interrupt
Not Masked MSKSCI SCI Interrupt
Masked SCI Interrupt
Not Masked MSKTM TIMER Interrupt
Masked TIMER Interrupt
Not Masked MSKTC TRIAC/ PWM Interrupt
Masked TRIAC/ PWM Interrupt
Not Masked not used - not used - EXTI Activeon Rising Edge Activeon Falling Edge
Table 4.1. Configuration Register14 Description
Name Description Priority Peripheral
Code Maskable EPROM
Locations

INT_EXT External Interrupt (INT) Ext Highest - yes 200-201
INT_ADC ADC Int Programmable 00 yes 192-193
INT_SCI SCI Int Programmable 01 yes 194-195
INT_TIMER TIMER Int Programmable 10 yes 196-197
INT_TRIAC TRIAC Int Programmable 11 yes 198-199 able 4.2. InterruptsDescription
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D6 D5 D4 D3 D2 D1 D0REG_CONF14
Interrupt
MSKE - External Interrupt Mask
MSKAD- ADC Interrupt Mask
EXTI - External Interrupt Polarity
MSKSCI- SCI Interrupt Mask
MSKTM- TIMER Interrupt Mask
not used
not used
MSKTC- TRIAC Interrupt Mask
Figure 4.4. Interrupt ConfigurationRegister14 D6 D5 D4 D3 D2 D1 D0
REG_CONF15
Interrupt
INT1 - HIGH Level Interrupt
INT2 - MEDIUM-HIGH Level Interrupt
INT3 - MEDIUM-LOW Level Interrupt
INT4 - LOW Level Interrupt
Figure 4.5. Interrupt ConfigurationRegister15
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i.e. LDCF 15, 201 (REG_CONF15=11001001)
define the following priority levels:
Level1: INT_SCI(SCI Code: 01)
Level2: INT_TIMER(TIMER Code: 10)
Level3: INT_ADC(ADC Code: 00)
Level4: INT_TRIAC(TRIAC Code: 11)
Whena source providesan Interrupt request, and
the request processingis also enabled, the CU
changes the normal sequential flowofa program
bytransferingprogramcontrol toa selectedservice
routine.
Whenan interruptoccurs the CU executesa JUMP
instructionto the address loadedin the related
locationof the Interrupt Vector
Whenthe executionreturnsto the originalprogram, begins immediately following the interrupted
instruction.
4.6 Interrupt RESET
eventually pending interrupts canbe reset with
the instruction RINT inti which resets the i-th
interrupt
Bit Name Value Level1 INT1 Peripheral
Code High3 INT2 Peripheral
Code Medium-High5 INT3 Peripheral
Code Medium-Low7 INT4 Peripheral
Code Low
Table 4.3. Configuration Register15 Description
Figure 4.6. Exampleofa Sequenceof Interrupt Requests
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CLOCKST52x301 can work by usinga5, 10or 20 MHz
clock.
The ST52x301ClockGeneratormodule generates
theinternal clockfor theinternal Control Unit,ALU,
Fuzzy Core and on-chip peripherals anditis
designedto requirea minimumof external
components.
Thesystemclock maybe generatedby usingeither qua rtzcr ystal, ora cera mic resonator
(CERALOC);or,at least,by meansofan external
clock.
The different clock generator options connection
methods are shownin Figure 5.1.
When an external clockis used,it must be
connectedon the pin OSCinwhile OSCout mustbe
grounded.
The crystal oscillator start-up timeisa functionof
manyvariables:crystalparameters(especiallyRS),
oscillator load capacitance (CL),IC parameters,
ambient temperature,supplyvoltage. must be observed that the crystalor ceramic
leads and circuit connectionsmustbeas shortas
possible.Typical valuesfor CL1, CL2 are 10pF for20 MHz crystal.
Figure 5.1. Oscillator Connections
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A/D CONVERTERThe A/D Converterof ST52x301is an 8-bit analog digital converter with upto4 analog inputs
offering8bit resolution witha total accuracy of2
LSB anda typical conversion timeof32 μs.
The conversionrangeis0- 2.5V.

The A/D peripheral converts the input voltage with processof successive approximations usinga
fixed clock frequency derived from the oscillator.
The ADC uses5 registers: one Configuration
Register, REG_CONF2, and four Data Registers.
These4 registersare the first4 Input Registers.
The A/D converter drives the analog Multiplexerin
orderto sequentially pickup the externalinputsto putin output and stored automaticallyin4 8-bit
registers.is possibileto configurethe Multiplexerbymeans the register REG_CONF2,in orderto select the
numberof analog inputsto convert.
For example,if thebit3 andbit2of REG_CONF2
are configuredat 10, then the Multiplexer will
sequentially pickup only the inputs 0,1 and2.
Table 6.1 shows the convertion sequences
accordingto the possible valuesof the two bit
REG_CONF2 (3:2).
The A/D Converter,at the endof the conversion,
will senda signal (end-of-conversion)which canbe
used likean interrupt signal. The user can select
the priorityof the A/D interrupt and maskit (see
”Interrupt Routine” chapter)
The conve rsion starts writ ing ”1” on
REG_CONF2(0).The A/Dis resetby writing ”0”in
REG_CONF2(0).
Theconverted dataare automaticallystoredin four
8-bit Input Registers. performingan instruction:
LDRI regj ingi
theanaloginput ”ingi”is loadedintheregister”regj” the Register File.
Figure 6.1. A/D Converter Structure
CONF_REG2 (3:2) INPUT SEQUENCE Ain0 Ain0, Ain1 Ain0, Ain1, Ain2 Ain0, Ain1, Ain2, Ain3
Table 6.1.
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The power consumptionof the device can be
reducedby turningoff the A/Dconverter, oswitchoff the A/D converter theCONF_REG2(0)
bit mustbe resetto ”0”.
The A/D Converter featuresa sample and hold.
The input voltage Ain, which hastobe converted
mustbe constant,for 12.8 μs. internal bandgap referenceis availableon pin
44, BG. By using this signalas reference for the
signaltobe converted, the conversion accuracyis
not strongly related with the variationof the power
supply.
The power supplyof the A/D converter (AVDD and
AVSS)in orderto avoidinterferencesis mantained
separatedfromthe power supplyof thedigitalcore. D6 D5 D4 D3 D2 D1 D0
ADC

Configuration Register
REG_CONF2
Reset ADC
Mustbe1
ADC input selection
Not used
Figure 6.2. ConfigurationRegister REG_CONF2
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7.TIMER
ST52x301 offers one on-chip Timer peripheral.
TheTimerconsistsofan 8-bit counter witha 16-bit
programmable prescaler, thus givinga maximum
count of224, and control logic that allows
configuring the functionment and the typeof
peripheral outputs. Figure 7.2 shows the Timer
block diagram and Figure 7.3 shows the internal
structureof the Timer.
Thecontentof the 8-bit countercanbe read/written
andis incrementedon the RisingEdgeof the16-bit
prescaleroutput(PRESCOUT).Moreover,it canbe
read under program controlat any instantof the
counting phase and loadedina locationof the
RegisterFile.Theprescalercanbe given anyvalue
between0 and FFFFh setting the 4-th (TMLSB)
and 5-th (TMMSB) locationsof the Configuration
Registers Bench.
7.1Timer Functionment

The Timer requiresthree signals:TMRCLK, TRST
and TSTART (see Figure7.3). Eachof them canbe
generatedinternallyor externally,this possibilityis
programmableby the user.
TMRCLK increments the counted valueof the
Prescaler.It can be, by setting CKSL of
REG_CONF6 register, the internal clock signal
(CLKM)or the signal providedon the pin TCLK.
TRSTresets tozerothe contentof the 8bitcounter.is generatedby the TRESor RESET external
signalsor itisforcedbyTMRSTbitof REG_CONF6
register.
TSTART starts/stops the Prescaler counting.It can givenon the pin TCTRLoritis forcedby TMST
bitof REG_CONF6register.
The TSTART signal allowsto workin two different
modes:
LEVEL (Time Counter):
If the TSTART signalis
high the Timer starts thecount.When the TST ART
islow the countis stoppedand the current valueis
storedin the TMR_OUT registerof the Input
registerBench, thenit can betransferredto the j-th
location of the Registers File by using the
instruction:
LDRI reg-j4
EDGE(Period Counter):
After the reset, when the
firstedgeof theTST ARTsignalappears,the Timer
starts the count,at the next TST ART the Timeris
stopped.In this wayitis possibleto measure the
periodofan external signal.
The functionment modalityis set by the TMEL
configurationbitof REG_CONF6 register.
The starting valueof the Counter can be eithera
value containedin the Register Fileor directlya
Fuzzy Output.If INPSL (REG_CONF7(3))is setto
”1”then the value comesfrom oneof the locations the Register File (LDRP 0, reg-i);on the
contraryitis generatedby the Fuzzy Core. The
choice between the two possible fuzzy outputsis
setby the FZSL configurationbitof REG_CONF6
register
FZSL=0/1 means the starting valueis the loaded
from the FUZZY_OUT_0/1.
Level
Edge
start stop start
start
stop
start 033321
Reset
Clock
Counted
Value
Figure 7.1. Timer Functionalities
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Figure 7.2. Timer Peripheral BlockDiagram
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Figure 7.3. Timer Internal Structure
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7.2Timer Interruptis possibleto enable the Timer Interrupt by
softwarecontrol.The Timer canbe programmedto
generatean Interrupt request until the endof the
countor when thereisan external TSTART signal.
The Timer can generate programmable Interruptsto4 different modes:
Interrupt mode1:
Interrupton counter Stop.
Interrupt mode2:
Interrupt on Rising Edgeof
TIMEROUT.
Interrupt mode3:
Interrupt on Falling Edgeof
TIMEROUT.
Interrupt mode4:
Interrupt on both edgesof
TIMEROUT.
InordertoprogramtheinterruptmodeINTSL, INTF
and INTR bitsof the REG_CONF7 must be set
following theindicationsshownin the Table7.1.The
Timer interrupt canbe usedto exit the MCU from
theWAIT mode.
7.3Timer Configuration

The Timer configurationneedsto set4 registersof
the Configuration Register Bench.
CONF_REG4:
TMLSB
contains the less significative bitsof the
Prescaler starting value.
CONF_REG5:
TMMSB
contains the more significative bitsof the
Prescaler starting value
Timer Output
Type1
Type2
Prescout*Counter
Figure 7.4.TIMEROUT Signal Type
INTERRUPT
MODE INTSL INTF INTR
X X 010 001 011
Table 7.1.Timer Interrupt Setting D6 D5 D4 D3 D2 D1 D0
REG_CONF4
Timer
TMLSB- PrescalerInit Value
Less SignificativeBits D6 D5 D4 D3 D2 D1 D0
REG_CONF5
Timer
TMMSB- PrescalerInit Value
More Significative Bits
Figure 7.5. Timer Configuration Register4 and5
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D6 D5 D4 D3 D2 D1 D0REG_CONF6
Timer
TMRST- Internal Timer Reset
TMST- Internal Timer Start
not used
IESL - Internal/External Signals Selector
TMEL- Edge/LevelTimer Abilitation
TMS - Timer Output Shape
POL - Timer Output Polarity
CKSL - Internal/External Clock Select
Figure 7.6. Timer Configuration Register6
Bit Name Value Description TMRST Stop Start TMST Stop Start IESL Internal Signals External Signals TMEL on Edge on Level CKSL Internal Timer Clock External Timer Clock
5TMS Pulse Wave(Type2) Square Wave (Type1) POL Positive Polarity Negative Polarity not
used -
Table 7.2. Configuration Register6 DescriptionCONF_REG6:
TMRST
sets the internalINR signal.
TMST
sets the internalINS signal.
IESL
selects the sourceof the TRES and
TST ART signals.
IESL=”0”signalsare theinternalINR and
INS.
IESL=”1” signals come from the TRES
and TCTRL pins.
TMEL
selects the TSTART signal allowingto
work inLevelModeor inEdge Mode like
previouslydescribed.
TMEL=”0” means Edge Mode
TMEL=”1” means Level Mode.
CKSL
selectsthe sourceof theTMRCLK(work-
ing Timer frequency).
CKSL=”0”, the TMRCLKis the internal
MCLK dividedby the Prescaler starting
value.
CKSL=”1”, the TMRCLKis an external
clockby TCLK pin.
TMS
TIMEROUTisa signal with frequency
equalto the working Timer frequency
dividedby the starting valueof the Pres-
caler (16 bit) and Counter(8 bit). The
Timer outputcanbe eithera squarewave
with duty-cycle 50%ora pulse signal
(withthe pulsedurationequalto thePres-
caler output signal period).
TMS=”1”, TIMEROUTisa square wave
TMS= ”0”, TIMEROUTisa pulse signal.
POL
defines the polarityof the Timer output
signal (TIMEROUT).
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Bit Name Value Description INTSL INT_TMRon Falling Edgeof
Counter Stop INT_TMRon Edgesof
TIMEROUT INTF NO INT_TMRon Falling
Edgeof TIMEROUT INT_TMRon Falling Edgeof
TIMEROUT INTR NO INT_TMRon Rising
Edgeof TIMEROUT INT_TMRon Rising Edgeof
TIMEROUT INPSL Timer Data Input coming
from the Fuzzy Core Timer Data Input coming
froma Register File location FZSL Timer Data Input coming
from FUZZY_OUT_0 Timer Data Input coming
from FUZZY_OUT_1 not used - not used - not used -
Table 7.3. Configuration Register7 Description D6 D5 D4 D3 D2 D1 D0
REG_CONF7
Timer
INTSL- Interrupt GeneratorSelector
INTF - Interrupton TIMEROUTFalling Edge
INTR - Interrupton TIMEROUTRising Edge
INPSL- Input DataSelector
FZSL - Fuzzy InputSelector
notused
notused
notused
Figure 7.7. Timer Configuration Register7
CONF_REG7:
INTSL
It allowsto select the interrupt modefor
the Timer.
INTSL=”0” Interruptis generatedon the
falling edgeof the Counter Stop.
INTSL=”1” the interruptis generatedon
the edgesof TIMEROUT.
INTF
INTR
INPSL
selects the sourceof the valueof the
Counterbetweena locationof theRegis-
ter File and the Fuzzy Core.
INPSL=”0”, Counter value coming from
the FC.
INPSL=”1”, Counter value coming from
the RF.
FZSL
FZSL=”0”, thevalueof theTimerCounter equalto FUZZY_OUT_0
FZSL=”1”, thevalueof theTimerCounter equalto FUZZY_OUT_1
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I/O PORTST52x301is provided with dedicated lines for
input/output.These lines,grouped intoan 8-bit I/O
Port P(0:7),canbe programmedto provide parallel
input/output witha handshake line (READY)to
carry data in/out.
The I/O Portis not ableto perform operationson
the single bit, and the communication cannot be
performedat the same timein input and output.is possibleto program the parallel port direction using the register REG_CONF0in orderto set
which bits arein input and which arein output.
The port has an in ternal register
(PERIPH_REG_2) dedicatedto hold output data
coming from the Register File through an LDPR
instruction.
Inputdata are automaticallystoredin theIN_PORT
register, 6-th locationof the Input Register. pinisa digital output line available directly
connectedto the OUT bitof the REG_CONF1;
thenit canbe setby usinga LDCF instruction.
(see table 8.2 and Figure 8.8)
PERIPH_REG_2(i)
P(0:7)
I/OPIN
TTL
CMOS
IO(i)
INP_PORT(i)
TRISTATE
REG_CO NF0(i)
OUTPUTPINREG_CONF1(0) OUT
Figure 8.1.
Figure 8.2.
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8.1 I/O PORTCONFIGURATION
REG_CONF0 allows dynamic changein I/O Port
configurationduringprogram execution setting the
communication directionof each bit.
IOi
setting equalto ”0” configures the i-thbit the P(0:7) I/O Portin input. Data com-
ing from external digital devices are
storedin the 6-th location(INP_PORT)of
the Input register bench.
IOi=”1” sets the i-th bitof the portin
output.Data storedin thei-th locationof
the RegisterFileis writtenon the portby
using the instruction:
LDPR 2, regi
Bit Name Value Description IO0 Input Pin Output Pin IO1 Input Pin Output Pin IO2 Input Pin Output Pin IO3 Input Pin Output Pin IO4 Input Pin Output Pin IO5 Input Pin Output Pin IO6 Input Pin Output Pin IO7 Input Pin Output Pin
Table 8.1. Configuration Register0 Setting D6 D5 D4 D3 D2 D1 D0
REG_CONF0
I/O Port
IO0 -I/O Communication DirectionBit
IO1 -I/O Communication DirectionBit
IO2 -I/O Communication DirectionBit
IO3 -I/O Communication DirectionBit
IO4 -I/O Communication DirectionBit
IO5 -I/O Communication DirectionBit
IO6 -I/O Communication DirectionBit
IO7 -I/O Communication DirectionBit
Figure 8.3. ConfigurationRegister0
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8.2 INPUT HANDSHAKE
Figure 8.5 illustrates the timing associatedwith the
READY Handshake signal, when the instruction
LDRI reg6is performed.
When the LDRI instructionis executedto read the
port, ST52x301 resets the READY signal to
indicate thatitis not possibleto change the input
data during this phaseof reading. osynchronizethetransmissionwithREADYsignal
will prevent the INP_PORT data from changing
whileST52x301is reading the port.
READ PORT signal representedin figure 8.5isan
ST52x301 internal signal.
Input data on the port are continuously sampled
and are strobed into the port only when READYis
set.
W.A.R.P.3TC
xxxx x0x
REG_CONF1

P(7:0)
IOP
EXTERNAL
PERIPHERAL

DATA
READY
I/O
PORT
Figure 8.4.One Line Input Handshake
PIO(7:0)
READY
DATAIN
READ PORT
CLK
NEWDATAIN
Figure 8.5. One Line Input HandshakeTiming
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8.3 OUTPUT HANDSHAKE
Figure 8.7 illustrates the timing associatedwith the
READY Handshake signal, when the instruction
LDPR2 regis performed.
WhenREADYis resetnosignificantdata areonthe
output port pins, because ST52x301is writing into
the PERIPH_REG_2.
When the datais readyin PERIPH_REG_2,
READY signalis set.
The rising edgeof READYsignal canbe usedasa
latching signal. peripheral acknowledgeis waited for. the signal READYis high,it means that the data
outis still not read.In thiscase, the followingLDPR
instructionis storedina one register peripheral
stack. the READYis maintained high, the following
LDPR instructions store the data coming from the
Registers Fileon the same register stack.
Figure 8.6.One Line Output Handshake
Figure 8.7. One Line Output Handshake Timing
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meansthateach LDPRinstructiondeletesthe oldvalue containedin the parallel port stack register
and rewritea newvalueon the same stackregister.
Only the last LDPR instructionis executedif the
READY signalis maintained high during several
LDRP instructions.
Bit Name Value Description
0P8 - Digital OutputBit
ECKF 5 MHz 10 MHz 20 MHz 20 MHz TXC SCI End Transmission
Interrupt Disabled SCI End Transmission
Interrupt Enabled TDRE
SCI Transmission Data
Register Empty Interrupt
Disabled
SCI Transmission Data
Register Empty Interrupt
Enabled BRK SCI Break Error Interrupt
Disabled SCI Break Error Interrupt
Enabled OVR SCI Overrun Error Interrupt
Disabled SCI Overrun Error Interrupt
Enabled RDRF SCI Received Data Register
Full Interrupt Disabled SCI Received Data Register
FullInterrupt Enabled
Table 8.2 Configuration Register1 Setting
Figure 8.8.
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SERIAL COMMUNICATION INTERFACEThe Serial Communication Interface (SCI)
integrated into the fuzzy processor ST52x301
providesa general purpose shift register
peripheral, that allowsto link several widely
distributed MCUs, through their SCI subsystem.
The SCI givesa serial interface providing
communication with common baud rates, upto
38400Hz, and flexible character format.
The SCIisa full-duplex UART -type asynchronous
system with standard Non Returnto Zero (NRZ)
formatfor the transmitted/received bit. The length the transmittedwordis 10/11 bits(1 start bit, 8/9
data bits,1 stop bit).
The SCIis composedof three modules: Receiver, ransmitter and Baud-Rate Generator anditis
configuredby meansof ConfigurationRegisters3
and1.
9.1 SCI RECEIVERBLOCK

The SCI Rec eiver block ma nagesthe
synchronizationof the serial data stream and
stores the data characters. The SCI Receiveris
mainly formed by two sub-systems: Recovery
Buffer Block and SCDR_RX Block.
The RE configurationbit setto ”1” (Configuration
Register3) enables the SCI Receiver.
The SCI receives data coming from the RxD pin
and drives the Recovery Buffer Block, thatisa
high-speed shift register operatingata clock
frequency (CLOCK_RX)16 times higher than the
fixed baud rate (CLOCK_TX). This sampling rate,
higher than the Baud Rate clock, allowsto detect
Figure 9.1.SCI transmitted word structures
Figure 9.2. SCI Block Diagram
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Bit Name Value Description
0TE Transmission DISABLED Transmission ENABLED
1RE Receiver DISABLED Receiver ENABLED 8,No Parity,1bit stop 8,No Parity,2bit stop 8, Parity,1bit stop 9,No Parity,1bit stop
4T8
Parity Odd,if Parityis
selected(M= 10); otherwise
9th Databit
Parity Even,if Parityis
selected(M= 10); otherwise
9th Databit
BRSL
000 600Hz
001 1200Hz
010 2400Hz
011 4800Hz
100 9600Hz
101 19200Hz
110 38400Hz
111 External Clock
Table 9.1 ConfigurationRegister3 SettingtheSTARTcondition,theNoiseerrorand theFrame
error.
When the SCI Receiverisin IDLE status,itis
waiting for the START condition, thatis obtained
witha logic level0, consecutivetoa logic level1.
Thisconditionis detected,if,with thefixedsampling
time, three logic levels0 are sampled after three
logic levels1.
The recognitionof the STARTbit forces the SCI
Receiver Blockto enterin an data acquisition
sequence, accordingto serial mode.
The2 bits,M,of the ConfigurationRegister3 allow
todefinethe serialmodewith theconventionshown table 9.2.
Thebit,T8,in caseofM = 10 is usedto set the parity
checkto perform,as indicatedin the previoustable
The recognitionof STOP condition allows to
transferthe received data, from Recovery Bufferto
SCDR_RX buffer, adding the eventual ninth data
bit,accordingto themeaningshown inthe previous
table 9.2. After this operation, RXF flagof SCI
Status InputRegister8 (fig.9.3)is setto logic level
1.The Control Unit readsthe data from SCDR_RX
buffer (in read-only mode) with SRX instruction
and providesa resetat logic level0to RDRF flag.a dataof Recovery Bufferis readyto be
transferred into SCDR_RX buffer, but the previous
one was not yet readby the Core,an OVERRUN
Error takes place:the status flag OVERR indicates
the error condition.In this case the information
storedin SCDR_RX bufferis not altered, but the
one that has caused the OVERRUN error canbe
overwrittenbya new data coming from the serial
data line.
Recovery Buffer Block

This blockis structuredasa synchronised finite
state machine on the CLOCK_RX signal falling
edge.
When the Recovery Buffer Blockisin IDLE stateit
waits for the receptionof the correct1 and0
sequence representing the ST ART.
The recognition takes placeby sampling the input
RxD at CLOCK_RX frequency, that hasa
frequency16 times higher than CLOCK_TX. For
this reason, while the external transmitter sendsa
single bit, the Recovery Buffer Block samples16
states(from SAMPLE1to SAMPLE16).
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Bit Name Value Description
0P8 - Digital OutputBit
ECKF 5 MHz 10 MHz 20 MHz 20 MHz TXC SCI End Transmission
Interrupt Disabled SCI End Transmission
Interrupt Enabled TDRE
SCI Transmission Data
Register Empty Interrupt
Disabled
SCI Transmission Data
Register Empty Interrupt
Enabled BRK SCI Break Error Interrupt
Disabled SCI Break Error Interrupt
Enabled OVR SCI Overrun Error Interrupt
Disabled SCI Overrun Error Interrupt
Enabled RDRF SCI Received Data Register
Full Interrupt Disabled SCI Received Data Register
FullInterrupt Enabled
Table 9.2 Configuration Register1 SettingThe analysisof RxD input signalis carried out
looking three samplesfor each bits received.0 these threesamples are notequal,thenthenoise
error flag, NSERR,of Input Register8is setto1
and the received data value will be the one
assumedby the majorityof the samples. meansof the procedure described above,to
avoid SCI becomes IDLE, becauseofa limited
noise due to an erroneous sampling, the
transmissionis recognizedas correctandthenoise
flag erroris set. the endof the cycle relativeto the receptionof bit, Recovery Buffer Block will repeat the same
steps9 times: one stepfor each received bit, plus
one forthestop acquisition(10timesin caseof 9-bit
data, double stopor parity check).
Atthe endof datareception,RecoveryBufferBlock,
will supply informationon eventual frame errorsby
settingto1 FRERR flagbitof Input Register8. frame error can occurif the parity check has not
been successfully achievedorif STOPbit has not
been detected. Recovery Buffer Block receives10 consecutive
bitsat logic level0,a break error occurres, and
interrupt routine request starts.
SCDR_RX block
isa finite state machine synchronized with the
falling edgeof the clock master signal, CKM.
The SCDR_RX block waits the signalof complete
reception, from the Recovery Buffer,to load the
word received. Moreover, the SCDR_RCX block
loads the valuesof FRERR and NSERR flag bits
(Input Register8), and sets the RXF flagto1.
Using SRX instruction the data are transferredto
RegisterFile and RXF flagis resetto0,to indicate
SCDR_RX blockis empty.a new data arrives before the previous one has
been transferredto Register File,an overrun error
occurres and OVERR flag,of Input Register8,is
setto1.
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9.2SCI TRANSMITTER BLOCK
The SCI TransmitterBlock consistsof the following
underblocks: SCDR_TX and SHIFT REGISTER,
synchronized, respectively, with the clock master
signal (CKM) and the CLOCK_TX.
The whole block receives through Configuration
Register3 (M bits) the settings for the following
transmissionmodes (see table 9.1):
8-bit word anda singlestop signal
8-bitwordplusa paritybit anda singlestop signal
8-bit word plusa doublestop signal
9-bit word caseof9 bit frame transmission, the most
significative bit arrives through T8 of the
Configuration Register3. an 8-bit transmission, instead, T8is usedto
configure the SCI, according to information
containedinM (seetable9.1):in particularto chose
thepolarity control(evenor odds) toimplement the
parity check.
Aftera RESET signal, RST, the SCDR_TX blockis IDLE stateuntil itreceivesenablingsignal,TE=1, Configuration Register3. TE=1, using STX instruction the data,to be
transmitted, are transferred from Register Fileto
SCDR_TX block and the flagof Input Register8,
TXEM,is resetto0,to indicate SCDR_TX blockis
full. the core suppliesa new data, this could not be
loadedin the SCDR_TXblockuntil the current data
has not beenunloadedon the Shift Register block.
Thismeans thatonly when TXEMis1,itis possible load datain the SCDR_TX Block.
When the SHIFT REGISTER Blockloads the databe transmittedon an internal buffer, TXENDis
resetto0to indicate the beginningofa new
transmission.At the endof transmission TXENDis
setto1, allowingto loadin the SHIFT REGISTER new data coming from SCDR_TX.is importantto underline that TXEND=1 does
notmeanSCDR_TXis readyto receivea newdata.
For this reason itis bettertoutilisethe TXEM signal synchronize the STX instructionto the SCI
TRANSMITTER block ST52x301core resets TEto0, the transmission interrupted, but the SCI Transmitter block
completes the transmissionin progress beforeto
reset.
9.3 Baud Rate GeneratorBlock

The Baud Rate Generator Block performs the
divisionof the clock master signal (CKM),ina set synchronism frequencies for the serial bit
reception/transmissionon the external line.
Table 9.1. shows the setof frequenciesselectedby
meansof BRSL (Configuration Register3).
Reception frequency (CLOCK_RX)is 16 times
higher than transmission frequency(CLOCK_TX). BRSLis equalto 111, CLOCK_RX and
CLOCK_TX signals coincide with clock master,
CKM.
Figure 9.3. SCI Status Input Register
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10TRIAC/PWMDRIVER
ST52x301 offersa peripheral ableto generatea
signalon pin 24, TRIACOUT,to drivean external
device, likea TRIAC,a IGBTora Power Mos. riac/PWM driver can perform3 different working
modes accordingto REG_CONF10 bits, MODE
(see Table 10.4):
MODE= ”01”:
PWM
MODE= ”10”:
Burst Mode Triac Control
(Thermal Regulations)
Note:in this case CKSLof REG_CONF10 must setto ”1x”.(see Table 10.4)
MODE= ”11”:
Phase Angle Partialization
Triac Control (Motor Control)
The Triac/PWM Driver canbe initializedby usinga
valuefixedbya controlalgorithm, thatcanbe either
the outputofa fuzzy inferenceor the resultof an
arithmetic calculus storedin the Register File. the latter case, by using the LDPR 1,reg-i
instruction, the value, containedin the i-th register Register File,is storedin theT riac Driver/PWM
peripheral register PERIPH_REG_1.
Figure 10.1 shows the internal structure of
Triac/PWM Driver.
PWM Mode

The PWM working modeis obtained by setting
REG_CONF10 bits, MODE,at ”01” value. consistsofa signal,with fixedperiod, whoseduty
cycle canbe modified.
Figure 10.1.TRIAC/PWM Driver Simplified Block Diagram
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D6 D5 D4 D3 D2 D1 D0REG_CONF8
TRIAC/ PWM
TCLSB- Prescalerinit value
Least Significative Bits D6 D5 D4 D3 D2 D1 D0
REG_CONF9
TRIAC/ PWM
TCMSB- Prescalerinit value
Most Significative Bits
Figure 10.2.TRIAC/PWM Configuration Register8 and9
The PWM period canbe generated, internally,by
dividing the masterclockor, externally,by usingan
external clock signal. both cases, the clocksignalis dividedbya 16-bit
Prescaler, managed by REG_CONF8 and
REG_CONF9 (see Figure 10.2).
The dutycycleis fixedbya value,that canbe either
the outputofa fuzzy inferenceor the resultof an
arithmetic calculus.In the first case,it can be
loaded directlyin the registerof the peripheral,
otherwiseit canbe storedin one locationof the
Register File for further manipulations and then
usedfor the controlof the PWM.
Burst Mode
is basedon turningon and off the TRIAC,fora
fixed integer numberof main voltage periods,in
orderto controlthe power transferredto the load.
For this reasona Burst Mode TRIAC control
consistsofa signal, witha period,T, containingan
integer numberof themain voltageperiods, whose
duty cycleis proportionalto the numberof periods whichthe TRIACis ON(Duty Cycle).This kindofriac controlis mainly usedfor thermal regulation.
Thedutycycleis fixedbya valuethatcanbe directly
the outputofa fuzzy inferenceor the resultof an
arithmetic calculus. orderto workin Burst mode,itis necessaryto
detect the pre-post zero-crossingof main voltage, usingan external inserting circuitry.
The user can define the periodT,by meansof the
internal 16-bit prescaler, setting REG_CONF8 and
REG_CONF9 (see Figure 10.2).Tis proportionalto
the main voltage period,itisin the range0to 21.8
sec(if themain frequencyis 50Hz).
The width and the polarityof the pulses can be
programmed accordingto the Triac and the circuit
characteristics.
Phase Angle Partialization Mode

This methodis basedon turningon the TRIAConly
fora part (phase angle)of each main voltage
period. When the phase angleis large the energy
(power)suppliedto the loadis low,viceversa, when
the phase angleis smallthe energysuppliedto the
loadis high.
The phase angle canbe fixedbya fuzzy algorithmbya value storedin the Register File.
The phase angleisan 8-bit value.
The peripheralis programmablein orderto work
witha main voltage frequencyof50or60 Hz.
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10.1 PWM GENERATOR WORKINGMODE
When REG_CONF10 (3:2) bits, MODE, are ”01”,
the peripheralis programmedto workin PWM
Mode. using the 16-bit prescaler,the PWM period can generatedby dividing the internal master clock, an external clock signal applied on the pin
MAIN1,or themain voltagefrequency,byusing the
circuit shownin Figure 10.6.
NOTE: The external clock signal, applied on
MAIN1 pin,must havea frequencyat least three
time smaller than the internal master clock.

The clock source can be selected by using
REG_CONF10(5:4)bits,CKSL(see Table 10.4and
Figure 10.9).If the clock source selectedis not the
main voltagefrequency(CKSL=1x),MAIN2pin can configured as input or output, by using
REG_CONF10(7) bit, IOSL (seeT able 10.4). MAIN2is an output,on this pinitis possibleto
get the prescaler output signal Tck.
The periodof the PWM signalis obtainedby using
the following relation:
T=256*Tck
where Tckis the outputof the 16-bit prescaler
managedby REG_CONF8 and REG_CONF9(see
Figure 10.2).
NOTE.In PWM working mode, the value N,
storedin the 16-bit prescaler, must bein the
range from2to216-1
usinga 20 MHz clock masteritis possibleto
obtaina PWM frequencyin the range 1.2 Hzto
26.04 KHz.
The value Tonis proportionaltoa value,
INIT_VALUE,thatcanbea fuzzy outputora value
Value Description
PWM Driver Burst Mode Control(1) Phase Angle Control
Note:(1) REG_CONF10(5) mustbesetto”1”
Table 10.1.MODE- Triac/PWMWorking Mode
Settings
MCLK
Frequency
1/T
min max
MHz 0.3Hz 6.51 kHz MHz 0.6Hz 13.02 kHz MHz 1.2Hz 26.04 kHz
Table 10.2. PWM Frequencies 256* Tck
Ton= INIT_VALUE* Tck Toff
TRIACOUT
Figure 10.3.PWM Functionament
coming from Register File, according with the
INPSL and FZSL configuration bits of
REG_CONF12 (see Table10.6 and Figure 10.12).
The Tonis equalto:
Ton= INIT_VALUE*Tck. means the Ton can be fixed by the control
algorithm that canbe either the outputofa fuzzy
inferenceor the resultofan arithmetic calculus.In
thesecond case,the data,storedin the i-th location the Register File, canbe loadedby using the
instruction:
LDPR 1, reg-i. the INIT_VALUEis 255 the Toffis equalto Tck.
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10.2 BURST MODE
When REG_CONF10 (3:2) bits, MODE, are ”10”
the peripheralis programmedto workin BURST
MODE.
Notice that when you are workingin Burst mode
CKSL mustbe setto ”1x”
. (see Table 10.4) square wave, Tb,is generated witha duty cycle
proportionalto the power the user intendsto
transferon the load.A pulseis generatedfor each
zero crossingof the main voltage includedin theonof the fixed period. Figure 10.4 shows the
typicalBurstControlworkingmode.The periodTof
thesignalTb (seeFigure 10.4)is equalto 256*Tck.
Thesignal Tckis generatedprogrammingthe16-bit
Prescaler, by REG_CONF8 and REG_CONF9
(see Figure 10.2).Tckis equalto the main voltage
frequency (50or60 Hz) dividedby N+1, whereN
valueis from0to216-1.
The value Tonis proportionaltoa value,
INIT_VALUE,thatcanbea fuzzy outputora value
coming from Register File, according with the NPSL and FZSL config uration bits of
REG_CONF12 (see Table10.6 and Figure 10.12). TRIACOUT pinis generateda sequenceof
pulses, programmed,by using REG_CONF11(0)
bit, POL (see Table 10.5),in ordertobe positiveor
negative,to drive the Triacin different quadrants.
The numberof generated pulses, N_PULSES,is:
N_PULSES=2 [(N+1)*INIT_VALUE-N]
whereNis the value storedin the 16-bit pescaler.
ThenTon= (N_PULSES/ 2)* TPOWERLINE
The first pulseis obtained during the first zero
crossingof the main voltage and the last oneis
generated after INIT_VALUE*Tck clock pulses,
where Tckis the Prescaler output, generatedby
using the mainvoltage frequencyappliedto MAIN1
and MAIN2 pins.
Theperipheralcan beprogrammedin orderto work
with50or60Hz main voltage frequency,by setting
the REG_CONF10(6) bit, PSF (see Table 10.4).
Rangesof the Tb signal period depend on the
powerline frequency (see Table10.3). orderto drivea Triacin Burst Modeitis required generatea sequenceof pulse, that must be
centredon the zero crossingof the power lineas
shownin the Figure 10.7. For this reason, the pre
zero crossing and the post zero crossingof the
powerline mustbe detected. detect the zero-crossing and get also the main
voltage frequency, the user must generate MAIN1
and MAIN2 signals,by using the circuit shownin
Figure 10.6.
MAIN1 and MAIN2 signals are usedin the block
called PULSE GENERA TORof theperipheral (see
Figure 10.1). particular the pulses are generatedby using the
rise edgeof the signal MAIN1 and the falling edge the signal MAIN2.
Figure 10.5 shows the generationof the Triac
pulsesTp.
The first firing pulse for the Triacis generatedon
the zero crossingof the power line, while the next
pulses are centredon the zero crossing.
Power Line
Frequency
min max
Hz 5.12s 335544sHz 4.26s 279620s
Table 10.3. TRIACOUT Signal Period
Ton
Power
Line
TRIACOUT= 256* Tck
Figure 10.4.Burst Working Mode
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Normally the Triac firing pulses start 1/3 Tp before
thezerocrossing and the lengthof thepulsesis Tp,
see Figure 10.5.
The length Tpof the pulsesis programmableby
usingUTP value,thatis a14-bitsnumber,obtained
with REG_CONF12(5:0) bits, UTPMSB, and
REG_CONF13, UTPLSB (see figure 10.12 and
table 10.6):
UTP(13:0)= [UTPMSB(5:0)UTPLSB(7:0)] =TMCLK* UTP
The valueTpisin the range0to 4.9 ms when the
clock masteris20 MHz.
Accordingto REG_CONF11(0) configuration
register bit, POL,itis possibleto set the firing
(1)
(0.5)
Negative
Triac Gate
Current 2/3Tp
1/3Tp
Positive
Triac Gate
Current
Power
LineandIII quadrants andIVquadrants
Figure 10.5.Burst Mode pulse polarity
Figure 10.6 Burst Mode ZeroCrossing Circuit
MAIN1
MAIN2
MainVoltage
TRIACOUT Tp TpTMASK TMASK
Figure 10.7 Burst Mode Zero Crossing
MCLK
Frequency
min max
MHz 0.0012 ms 19.6608ms MHz 0.0006 ms 9.8304 ms MHz 0.0003 ms 4.9152 ms
pulses polarity;in order to obtain positiveor
negative gate Triac currents, allowingto work
respectivelyinI andIV quadrants,orin theII and
III quadrants (seeFigures 10.5 and 10.12). increase the immunityof the peripheralagainst
the electrical noise of the main voltage,a
programmable masking time, by using
REG_CONF11(5:2)bits, TCMSK (see Table 10.5)
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and Figure 10.11),is introduced after each firing
pulse (see Figure 10.7):
Masking time =(2^TCMSK*200 +100) nS. TCMSKis0 then Masking timeis0. fact,to avoid the detectionof electrical noise,
during the masking time no signal, coming from
MAIN1 and MAIN2,is taken into account.
Workingin theII andIII quadrant the peripheral
implements the following procedure: The firing pulseis setto ”1”on the rising edgeof
MAIN1. The firing pulseis resetto ”0” after the timeTp
fixedby program. The firing pulseis resetto ”0”fora timeequalto
the fixed masking time. On the falling edgeof MAIN2the firing pulseis
setto ”1” The firing pulseis resetto ”0” after the timeTp
fixedby program. The firing pulseis resetto ”0”fora timeequalto
the fixed masking time.
Following this approachitis possibleto filter
electrical noise and oscillations on the signal
MAIN1 and MAIN2. ispossibleto generatea programmableInterrupt four different ways: No Interrupt; Interrupton the rising edgeof the signal Tb. Interrupton the falling edgeof the signal Tb. Interrupton both the edgeof the signal Tb.
TheInterruptis programmableby usingthe register
REG_CONF11(7:6),INTSL (see Table 10.5).
(1.5)
(1)
(0.5)
(1.5)
(1)
(0.5)
VA2-A1
180 360
Phase Angle
Current Flow Angle
Load

Figure 10.8.Phase Angle Partialization Mode
10.3 PHASE ANGLE PARTIALIZATION WORK-
ING MODE

When REG_CONF10 (3:2) bits, MODE, are ”11”
the peripheralis programmedto workin PHASE
ANGLE PARTIALIZATION mode. this mode Triacis controlled each periodof the
main voltage. The power transferredto the loadis
proportionalto the CURRENT FLOW ANGLEγ.
Thiskind ofT riaccontrolis suitabletodrivethe Triac
TCMSK MaskingTime

0000 0 μs
0001 0.5 μs
0010 0.9 μs
0011 1.7 μs
0100 3.3 μs
0101 6.5 μs
0110 12.9 μs
0111 25.7 μs
1000 51.3 μs
1001 102.5 μs
1010 204.9 μs
1011 409.7 μs
1100 819.3 μs
1101 1638.9 μs
1110 3276.9 μs
1111 6553.7 μs
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ic,good price


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