ST5092TQFP ,2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-ENDBLOCK DIAGRAMMIC3-MIC PREAMP MIC AMP20dB 0 -> 22.5MIC2- EN+ MUTE 1.5dB STEPMIC1-PREFILTER &DETRANSM ..
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ST5092TQFP
2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
ST50922.7V SUPPLY 14-BIT LINEAR CODEC
WITH HIGH-PERFORMANCE AUDIO FRONT-END
PRELIMINARY DATA
FEATURES:
Complete CODEC and FILTER system including:14 BIT LINEAR ANALOG TO DIGITAL AND
DIGITAL TO ANALOG CONVERTERS. BIT COMPANDED ANALOG TO DIGITAL
AND DIGITAL TO ANALOG CONVERTERS
A-LAW OR μ-LAW.
TRANSMIT AND RECEIVE BAND-PASS FILTERS
ACTIVE ANTIALIAS NOISE FILTER.
Phone Features:THREE SWITCHABLE MICROPHONE AM-
PLIFIER INPUTS. GAIN PROGRAMMABLE:
20 dB PREAMP. (+MUTE), 0 . . 22.5 dB AM-
PLIFIER, 1.5 dB STEPS.
EARPIECE AUDIO OUTPUT. ATTENUATION
PROGRAMMABLE: 0 . . 30 dB, 2 dB STEPS.
EXTERNAL AUDIO OUTPUT. ATTENUATION
PROGRAMMABLE: 0 . . 30 dB, 2 dB STEPS.
TRANSIENT SUPRESSION SIGNAL DURING
POWER ON AND DURING AMPLIFIER
SWITCHING.
INTERNAL PROGRAMMABLE SIDETONE
CIRCUIT. ATTENUATION PROGRAMMABLE:
16 dB RANGE, 1 dB STEP. ROUTING POSSI-
BLE TO BOTH OUTPUTS.
INTERNAL RING OR TONE GENERATOR IN-
CLUDING DTMF TONES, SINEWAVE OR
SQUAREWAVE WAVEFORMS. ATTENU-
ATION PROGRAMMABLE: 27dB RANGE,
3dB STEP. THREE FREQUENCY RANGES:
a) 3.9Hz . . . . 996Hz, 3.9Hz STEP
b) 7.8Hz . . . . 1992Hz, 7.8Hz STEP
c) 15.6Hz . . . . 3984Hz, 15.6Hz STEP
PROGRAMMABLE PULSE WIDTH MODU-
LATED BUZZER DRIVER OUTPUT.
General Features:SINGLE 2.7V to 3.6V SUPPLY
EXTENDED TEMPERATURE RANGE OPERA-
TION (*) -40°C to 85°C.
1.5 μW STANDBY POWER (TYP. AT 3.0V).
15mW OPERATING POWER (TYP. AT 3.0V).
13mW OPERATING POWER (TYP. AT 2.7V).
CMOS COMPATIBLE DIGITAL INTERFACES.
PROGRAMMABLE PCM AND CONTROL IN-
TERFACE MICROWIRE COMPATIBLE.
APPLICATIONS:GSM DIGITAL CELLULAR TELEPHONES.
CT2 DIGITAL CORDLESS TELEPHONES.
DECT DIGITAL CORDLESS TELEPHONES.
BATTERY OPERATED AUDIO FRONT-ENDS
FOR DSPs.
(*) Functionality guaranteed in the range – 40°C to +85°C; Timing and Electrical Specifications are guaranteed in the range
– 30°C to +85°C.
GENERAL DESCRIPTIONST5092 is a high performance low power combined
PCM CODEC/FILTER device tailored to implement
the audio front-end functions required by the next
generation low voltage/low power consumption
digital terminals.
ST5092 offers a number of programmable func-
tions accessed through a serial control channel that
easily interfaces to any classical microcontroller.
The PCM interface supports both non-delayed (nor-
mal and reverse) and delayed frame synchroniza-
tion modes.
ST5092 can be configurated either as a 14-bit lin-
ear or as an 8-bit companded PCM coder.
Additionally to the CODEC/FILTER function,
ST5092 includes a Tone/Ring/DTMF generator, a
sidetone generation, and a buzzer driver output.
ST5092 fulfills and exceeds D3/D4 and CCITT rec-
ommendations and ETSI requirements for digital
handset terminals.
Main applications include digital mobile phones, as
cellular and cordless phones, or any battery pow-
ered equipment that requires audio codecs operat-
ing at low single supply voltages
BLOCK DIAGRAM
PIN CONNECTIONS (Top view)
ST5092
PIN FUNCTIONS (SO28)
ST5092
PIN FUNCTIONS (TQFP44)
ST5092
FUNCTIONAL DESCRIPTIONI DEVICE OPERATION
I.1 Power on initialization:
When power is first applied, power on reset cir-
cuitry initializes ST5092 and puts it into the power
down state. Gain Control Registers for the various
programmable gain amplifiers and programmable
switches are initialized as indicated in the Control
Register description section. All CODEC functions
are disabled.
The desired selection for all programmable func-
tions may be intialized prior to a power up com-
mand using the MICROWIRE control channel.
I.2 Power up/down control:
Following power-on initialization, power up and
power down control may be accomplished by writ-
ing any of the control instructions listed in Table 1
into ST5092 with "P" bit set to 0 for power up or 1
for power down.
Normally, it is recommended that all programma-
ble functions be initially programmed while the
device is powered down. Power state control can
then be included with the last programming in-
struction or in a separate single byte instruction.
Any of the programmable registers may also be
modified while ST5092 is powered up or down by
setting "P" bit as indicated. When power up or
down control is entered as a single byte instruc-
tion, bit 1 must be set to a 0.
When a power up command is given, all de-acti-
vated circuits are activated, but output DX will re-
main in the high impedance state until the second
Fs pulse after power up.
I.3 Power down state:
Following a period of activity, power down state
may be reentered by writing a power down in-
struction.
Control Registers remain in their current state and
can be changed by MICROWIRE control inter-
face.
In addition to the power down instruction, detec-
tion of loss MCLK (no transition detected) auto-
matically enters the device in "reset" power down
state with DX output in the high impedance state.
I.4 Transmit section:
Transmit analog interface is designed in two
stages to enable gains up to 42.5 dB to be real-
ized. Stage 1 is a low noise differential amplifier
providing 20 dB gain. A microphone may be ca-
pacitevely connected to MIC1+, MIC1- inputs,
while the MIC2+ MIC2– and MIC3+ MIC3- inputs
may be used to capacitively connect a second mi-
crophone or a third microphone respectively or an
auxiliary audio circuit. MIC1 or MIC2 or MC3 or
transmit mute is selected with bits 6 and 7 of reg-
ister CR4.
In the mute case, the analog transmit signal is
grounded and the sidetone path is also disabled.
Following the first stage is a programmable gain
amplifier which provides from 0 to 22.5 dB of ad-
ditional gain in 1.5dB step. The total transmit gain
should be adjusted so that, at reference point A,
see Block Diagram description, the internal 0
dBm0 voltage is 0.49 Vrms (overload level is 0.7
Vrms). Second stage amplifier gain can be pro-
grammed with bits 4 to 7 of CR5.
An active RC prefilter then precedes the 8th order
band pass switched capacitor filter. A/D converter
can be either a 14-bit linear (bit CM = 0 in register
CR0) or can have a compressing characteristics
(bit CM = 1 in register CR0) according to CCITT A
or MU255 coding laws. A precision on chip volt-
age reference ensures accurate and highly stable
transmission levels.
Any offset voltage arising in the gain-set amplifier,
the filters or the comparator is cancelled by an in-
ternal autozero circuit.
Each encode cycle begins immediatly at the be-
ginning of the selected Transmit time slot. The to-
tal signal delay referenced to the start of the time
slot is approximatively 195 μs (due to the transmit
filter) plus 125 μs (due to encoding delay), which
totals 320 μs. Voice data is shifted out on DX dur-
ing the selected time slot on the transmit rising
edges of MCLK in delayed or non-delayed normal
mode or on the falling edges of MCLK in non-de-
layed reverse mode.
I.5 Receive section:
Voice Data is shifted into the decoder’s Receive
voice data Register via the DR pin during the se-
lected time slot on the falling edges of MCLK in
delayed or non-delayed normal mode or on the
rising edges of MCLK in non-delayed reverse
mode.
The decoder consists of either a 14-bit linear or
an expanding DAC with A or MU255 law decod-
ing characteristic. Following the Decoder is a
3400 Hz 8th order band-pass switched capacitor
filter with integral Sin X/X correction for the 8 kHz
sample and hold.
0 dBmO voltage at this (B) reference point (see
Block Diagram description) is 0.49 Vrms. A tran-
scient suppressing circuitry ensure interference
noise suppression at power up.
The analog speech signal output can be routed
either to earpiece (VFR+, VFR- outputs) or to an ex-
tra analog output (VLr+, VLr- outputs) by setting
bits OE and SE (1 and 0 of CR4).
Total signal delay is approximatively 190 μs (filter
plus decoding delay) plus 62.5 μs (1/2 frame)
which gives approximatively 252 μs.
Differential outputs VFR+,VFR- are intended to di-
rectly drive an earpiece. Preceding the outputs is
a programmable attenuation amplifier, which must
ST5092
