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ST3DV520EQTR
MUX/DEMUX for 4 differential channel LVDS and DDC
December 2010 Doc ID 18318 Rev 1 1/19
ST3DV520EMUX/DEMUX for 4 differential channel L VDS and DDC
Features Low RON: 4.0 Ω typical VCC operating range: 3.0 to 3.6 V Enhanced ESD protection: > 8 kV (contact) and kV (HBM) Channel on capacitance: 9.5 pF typical Switching time speed: 9 ns Near to zero propagation delay: 250 ps Very low crosstalk: -45 dB at 250 MHz Bit-to-bit skew: 200 ps > 600 MHz -3 dB typical bandwidth (or data
frequency) Support up to 4 differential LVDS channel Support 2 channel for DDC Independent SEL control for LVDS and DDC
channels Package: QFN56
Applications Audio/video switching High bandwidth physical layer signals routing
DescriptionThe ST3DV520E is a 4 differential channel LVDS
multiplexer/demultiplexer low RON bidirectional
switch used to switch between multiple LVDS
sources. It is designed for very low crosstalk, low
bit-to-bit skew and low I/O capacitance, to
maintain high signal integrity.
The differential signal from the LVDS transceiver
is multiplexed into one of two selected outputs
while the unselected switch goes to Hi-Z status.
The device integrates 2 SPDT (single pole dual
throw) switches, for DDC channel.
SEL for LVDS and DDC channel is controlled
independently.
Table 1. Device summary
Contents ST3DV520E2/19 Doc ID 18318 Rev 1
Contents Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ST3DV520E Pin description
Doc ID 18318 Rev 1 3/19
1 Pin description
Figure 1. Pin connection (top through view)
Table 2. Pin description
Pin description ST3DV520E
4/19 Doc ID 18318 Rev 1
Figure 2. Input equivalent circuit
Table 3. LVDS switch function table
Table 4. DDC switch function table
ST3DV520E Maximum rating
Doc ID 18318 Rev 1 5/19
2 Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2.1 Recommended operating conditions
Table 5. Absolute maximum ratings If VIO x IO does not exceed the maximum limit of PD.
Table 6. Recommended operating conditions
Electrical characteristics ST3DV520E
6/19 Doc ID 18318 Rev 1
3 Electrical characteristics
Table 7. DC electrical characteristics Refer to Figure 4: Test circuit for leakage current (IOFF) on page9 Measured by voltage drop between channels at indicated current through the switch. ON resistance is determined by the
lower of the voltages. Flatness is defined as the difference between the RONMAX and RONMIN of ON resistance over the specified range. ΔRON measured at same VCC, temperature and voltage level.
ST3DV520E Electrical characteristics
Doc ID 18318 Rev 1 7/19
Table 8. Capacitance (TA = 25 °C, f = 1 MHz)
Table 9. Power supply characteristics
Table 10. Dynamic electrical characteristics (VCC = 3.3 V ±10%) Refer to Figure 5 on page10 Refer to Figure 6 on page10 Refer to Figure 7 on page11 Refer to Figure 9 on page12 Refer to Figure 10 on page13 Refer to Figure 8 on page11
Electrical characteristics ST3DV520E
8/19 Doc ID 18318 Rev 1
Table 11. Switching characteristics (TA = 25 °C, VCC = 3.3 V ±10%)
Table 12. ESD performance Refer to Figure 3: Diagram for suggested VDD decoupling on page9.
ST3DV520E Electrical characteristics
Doc ID 18318 Rev 1 9/19
Figure 3. Diagram for suggested VDD decoupling Applicable for system level ESD test
Figure 4. Test circuit for leakage current (I OFF)
Electrical characteristics ST3DV520E
10/19 Doc ID 18318 Rev 1
Figure 5. Test circuit for SEL pin input capacitance (CIN)
Figure 6. Test circuit for switch off capacitance (C)
