ST26C32AB ,CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVERST26C32ACMOS QUAD TRI-STATEDIFFERENTIAL LINE RECEIVER■ CMOS DESIGN FOR LOW POWER■ ±0.2V SENSITIVITY ..
ST26C32ABD ,CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVERelectrical characteristics provide conditions for actual device operation.Note 2: Unless otherwise ..
ST26C32ABDR ,CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVERST26C32ACMOS QUAD TRI-STATEDIFFERENTIAL LINE RECEIVER■ CMOS DESIGN FOR LOW POWER■ ±0.2V SENSITIVITY ..
ST26C32ABN ,CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVERAbsolute Maximum Ratings are those values beyond which the safety of the device cannot be guarantee ..
ST26C32ABN ,CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVERPIN CONFIGURATIONPIN DESCRIPTIONPlN N° SYMBOL NAME AND FUNCTIONA INPUT A11IN1A INPUT A22IN2A Channe ..
ST26C32ABN ,CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVERABSOLUTE MAXIMUM RATINGS (Note 1, 2)Symbol Parameter Value UnitV Supply Voltage7VCCV Input Common M ..
STM1061N28WX6F ,Low power voltage detectorAbsolute Maximum Ratings 13Table 4. Operating and AC Measurement Conditions . . . 14Table ..
STM1061N30WX6F ,Low power voltage detectorapplications and is available in space-saving SOT23-3 and SOT323-3 (SC70-3) packages.Figure 2.
STM1061N34WX6F ,Low power voltage detectorSTM1061Low Power Voltage DetectorFigure 1. Packages
STM1061N38WX6F ,Low power voltage detectorBlock Diagram . . . 6Figure 6. STM1061N Active-Low, Open Drain Hardware Hookup . . . . 6Figur ..
STM1810MWX7F ,Low Power Reset Circuitblock diagrams . . . . . 71.2 Pin descriptions . . . . . 71.2.1 Active-low RST output (p ..
STM1815SWX7F ,Low Power Reset CircuitLogic diagram . . . . 5Figure 2. SOT23-3 connections . . . . . . 6Figure 3. Hardware h ..
ST26C32AB
CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVER
1/10December 2002 CMOS DESIGN FOR LOW POWER ±0.2V SENSITIVITY OVER INPUT COMMON
MODE VOLTAGE RANGE TYPICAL PROPAGATION DELAY: 19ns TYPICAL INPUT HYSTERESIS: 60mV INPUT WILL NOT LOAD LINE WHEN
VCC=0V MEETS THE REQUIREMENTS OF EIA
STANDARD RS-422, RS-423 3-STATE OUTPUTS FOR CONNECTION TO
SYSTEM BUSES AVAILABLEIN SURFACE MOUNT
DESCRIPTIONThe ST26C32Aisa quad differential line receiver
designedto meet the RS-422, RS-423 standards
for balanced and unbalanced digital data
transmission, while retaining the low power
characteristicsof CMOS.
The ST26C32A hasan input sensitivityof 200mV
over the common mode input voltage rangeof
±7V. The ST26C32A features internal pull-up and
pull-down resistors which prevent output
oscillation on unused channels. The ST26C32A
providesan enable and disable functiontoall four
receivers and features 3-STATE output with 6mA
source and sink capability.
ORDERING CODES
ST26C32ACMOS QUAD TRI-STATE
DIFFERENTIAL LINE RECEIVER
ST26C32A2/10
PIN CONFIGURATION
PIN DESCRIPTION
TRUTH TABLE= Low Voltage StateH= High Logic StateX= Don’t CareZ= High Impedance
ST26C32A3/10
ABSOLUTE MAXIMUM RATINGS (Note1,2)
Note1: Absolute Maximum Ratingsare those values beyond whichthe safetyofthe device cannotbe guaranteed. Theyarenot meanttoimplythatthe device shouldbe operatedat these limits. The tableof electrical characteristics provide conditionsfor actualdevice operation.
Note2: Unless otherwise specified,all voltageare referencedto ground.
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS(VCC =5V ± 10%, unless otherwise specified, See Note1)
Note1: Unless otherwise specified, min/max limits apply acrossthe recommended operating temperature range.All typicalare givenfor VCC=5VandTa =25°C
ST26C32A4/10
SWITCHING CHARACTERISTICS(VCC =5V ± 10%, See Note1)
Note1: Unless otherwise specified, min/max limits apply acrossthe recommended operating temperature range.All typicalare givenfor VCC=5VandTa= 25°C.
