ST24LC21 Fast Delivery |IC PHOENIX CO.,LIMITED

ST24LC21 ,1Kb (x8) DUAL MODE SERIAL EEPROM for VESA Plug&PlayLogic DiagramDESCRIPTIONThe ST24LC21 is a 1K bit electrically erasableprogrammable memory (EEPROM), ..
ST24LC21B ,1KB (X8) DUAL MODE SERIAL EEPROM FOR VESA PLUG & PLAYLogic DiagramENHANCED ESD/LATCH UPPERFORMANCESERROR RECOVERY MECHANISM(ST24FC21 and ST24FW21) VESA ..
ST24LC21B ,1KB (X8) DUAL MODE SERIAL EEPROM FOR VESA PLUG & PLAYST24LC21B, ST24LW21 ST24FC21, ST24FC21B, ST24FW211 Kbit (x8) Dual Mode Serial EEPROMfor VESA PLUG & ..
ST24LC21BB6 ,1KB (X8) DUAL MODE SERIAL EEPROM FOR VESA PLUG & PLAYST24LC21B, ST24LW21 ST24FC21, ST24FC21B, ST24FW211 Kbit (x8) Dual Mode Serial EEPROMfor VESA PLUG & ..
ST24LC21BM6 ,1KB (X8) DUAL MODE SERIAL EEPROM FOR VESA PLUG & PLAYST24LC21B, ST24LW21 ST24FC21, ST24FC21B, ST24FW211 Kbit (x8) Dual Mode Serial EEPROMfor VESA PLUG & ..
ST24LC21BM6TR ,1KB (X8) DUAL MODE SERIAL EEPROM FOR VESA PLUG & PLAYAbsolute Maximum Ratings Symbol Parameter Value UnitTA Ambient Operating Temperature –40 to 85

ST24LC21
1Kb (x8) DUAL MODE SERIAL EEPROM for VESA Plug&Play
ST24LC21
1Kb (x8) DUAL MODE SERIAL EEPROM
for VESA Plug&Play
NOT FOR NEW DESIGN
June 1997 1/18
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
2.5V to 5.5V SINGLE SUPPLY VOLTAGE
400k Hz COMPATIBILITY OVER the FULL
RANGE of SUPPLY VOLTAGE
TWO WIRE SERIAL INTERFACE I2 C BUS
COMPATIBLE
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ST24LC21 is replaced by the ST24LC21B
DESCRIPTION
The ST24LC21 is a 1K bit electrically erasable
programmable memory (EEPROM), organized by
8 bits.This device can operate in two modes: Trans-
mit Only mode and I2 C bidirectional mode. When
powered, the device is in Transmit Only mode with
EEPROM data clocked out from the rising edge of
the signal applied on VCLK.
The device will switch to the I2 C bidirectional mode
upon the falling edge of the signal applied on SCL
pin. The ST24LC21 cannot switch from the I2C
bidirectional mode to the Transmit Only mode (ex-
cept when the power supply is removed). The
device operates with a power supply value as low
as 2.5V. Both Plastic Dual-in-Line and Plastic Small
Outline packages are available.
Figure 1. Logic Diagram
Table 1. Signal Names
Figure 2A. DIP Pin Connections
Figure 2B. SO Pin Connections
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Table 2. Absolute Maximum Ratings (1)
Note: The MSB b7 is sent first.
X = 0 or 1.
Table 3. Device Select Code
Warning: NC = Not Connected Warning: NC = Not Connected
2/18
ST24LC21
Figure 3. Transmit Only Mode Waveforms
Note: X = VIH or VIL
Table 4. Operating Modes
3/18
ST24LC21
Transmit Only Mode
After a Power-up, the device is in the Transmit Only
mode. A proper initialization sequence must supply
nine clock pulses on the VCLK pin (in order to
internally synchronize the device). During this in-
itialization sequence, the SDA pin is in high imped-
ance. On the rising edge of the tenth pulse applied
on VCLK pin, the device will output the first bit of
byte located at address 00h (most significant bit
first).
A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.
As long as the SCL pin is held high, each byte of
the memory array is transmitted serially on the SDA
pin with an automatic address increment.
When the last byte is transmitted, the address
counter will roll-over to location 00h.2 C Bidirectional Mode
The device can be switched from Transmit Only
mode to I2 C Bidirectional mode by applying a valid
high to low transition on the SCL pin (see Figure 4).
When the device is in the I2C Bidirectional mode,
the VCLK input enables (or inhibits) the execution
of any write instruction: if VCLK = 1, write instruc-
tions are executed; if VCLK = 0, write instructions
are not executed.
The device is compatible with the I2 C standard, two
wire serial interface which uses a bi-directional data
bus and serial clock. The device carries a built-in 4
bit, unique device identification code (1010) corre-
sponding to the I2 C bus definition.
The device behaves as a slave device in the I2C
protocol with all memory operations synchronized
by the serial clock. Read and write operations are
initiated by a START condition generated by the
bus master. The START condition is followed by a
stream of 7 bits (identification code 1010XXX), plus
one read/write bit and terminated by an acknow-
ledge bit.
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
Figure 4. Transition Mode Waveforms
4/18
ST24LC21
Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I2 C Bus
SIGNAL DESCRIPTIONS2 C Serial Clock (SCL). The SCL input pin is used
to synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 5).
Transmit Only Clock (VCLK). The VCLK input pin
is used to synchronize data out when the
ST24LC21 is in Transmit Only mode. The VCLK
input offers also a Write Enable (active high) func-
tion when the ST24LC21 is in I2 C bidirectional
mode.
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 5).
DEVICE OPERATION2 C Bus Background
The ST24LC21 supports the I2 C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24LC21 are always slave de-
vices in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24LC21 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24LC21 and
the bus master. A STOP condition at the end of a
Read command forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
5/18
ST24LC21
Note: 1. Sampled only, not 100% tested.
Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )
Table 6. DC Characteristics
(TA = 0 to 70 °C; VCC = 2.5V to 5.5V)
6/18
ST24LC21
Notes:1. Sampled only, not 100% tested. For a reSTART condition, or following a write cycle.
Table 7. AC Characteristics, I2 C Bidirectional Mode for Clock Frequency = 400kHz
(TA = 0 to 70 °C; VCC = 2.5V to 5.5V)
Data Input. During data input the ST24LC21 sam-
ple the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation
the SDA signal must be stable during the clock low
to high transition and the data must change ONLY
when the SCL line is low.
Memory Addressing. To start communication be-
tween the bus master and the slave ST24LC21, the
master must initiate a START condition. Following
this, the master sends onto the SDA bus line 8 bits
(MSB first) corresponding to the device select code
(7 bits) and a READ or WRITE bit. The 4 most
significant bits of the device select code are the
device type identifier, corresponding to the I2 C bus
definition. For these memories the 4 bits are fixed
as 1010b. The following 3 bits are Don’t Care. The
8th bit sent is the read or write bit (RW), this bit is
set to ’1’ for read and ’0’ for write operations. If a
match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.
Write Operations
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. After receipt of the byte address the de-
vice again responds with an acknowledge.
In I2 C bidirectional mode, any write command with
VCLK = 0 will not modify data and will be acknow-
ledged on data bytes, as shown in Figure 11.
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition.
Page Write. The Page Write mode allows up to 8
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the most significant memory ad-
dress bits are the same. The master sends from
one up to 8 bytes of data, which are each acknow-
ledged by the memory.
7/18
ST24LC21
Notes:1. For a reSTART condition, or following a write cycle. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
Table 8. AC Characteristics, I2 C Bidirectional Mode for Clock Frequency = 100kHz
(TA = 0 to 70 °C; VCC = 2.5V to 5.5V)
Notes:1. Refer to Figure 3. Sampled only, not 100% tested.
Table 9. AC Characteristics, Transmit-only Mode
(TA = 0 to 70 °C; VCC = 2.5V to 5.5V)
8/18
ST24LC21
Figure 6. AC Waveforms
9/18
ST24LC21

Partno	Mfg	Dc	Qty	Available	Descript
ST24LC21	ST	N/a	21	avai	1Kb (x8) DUAL MODE SERIAL EEPROM for VESA Plug&Play