ST20184 Fast Delivery |IC PHOENIX CO.,LIMITED

ST20184 ,ADSL2+ ANALOG FRONT END FOR CPE APPLICATIONSblock diagram of ST20184CTRL/TSTDying Gasp Tuning Circuit I/V ReferenceInterfaceRXP3BypassRXP1LNA1a ..
ST20196 ,ADSL2+ UTOPIA DMT TRANSCEIVER FOR CPE APPLICATIONSFeaturesTone Equalization■ Standard Utopia level1 and 2 ATM interface■ ADSL2+ DMT modem with embedd ..
ST202BD ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSELECTRICAL CHARACTERISTICS (C - C = 0.1μF, V = 5V ± 10%, T = -40 to 85°C, unless otherwise specifie ..
ST202BDR ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSPIN CONFIGURATION PIN DESCRIPTION PlN N° SYMBOL NAME AND FUNCTIONC + Positive Terminal fo ..
ST202BN ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSST2025V POWERED MULTI-CHANNELRS-232 DRIVERS AND RECEIVERS ■ SUPPLY VOLTAGE RANGE: 4.5 TO 5.5V■ SUP ..
ST202BTR ,5V POWERED MULTI-CHANNEL RS-232 DRIVERS AND RECEIVERSAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
STK7563G ,STK7563G
STK7563GII ,2 OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQUIPMENTA Under deve 10pmentMaximum RatingsMA'ii'tirDescription .a & Vin Tc max Tstg . Package(N) 7 " F;max ..
STK7565 ,2 OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQUIPMENTA Under deve 10pmentMaximum RatingsMA'ii'tirDescription .a & Vin Tc max Tstg . Package(N) 7 " F;max ..
STK7573A , OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQIPMENT
STK7573B , OUTPUT TYPE SECONDARY REGULATOR FOR OFFICE AUTOMATION EQIPMENT
STK7575P , Advanced Power MOSFET

ST20184
ADSL2+ ANALOG FRONT END FOR CPE APPLICATIONS
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ST20184
February 2005
1Overview
The ST20184 is an ADSL2+ analog front end chip
designed for CPE applications. It is first released
as part of the ST-20190 Utopia chipset. The
chipset allows equipment manufacturers to devel-
op flexible platforms showing high performance,
fully leveraging the ADSL2+ 24 Mbps wireline
speed. These platforms can quickly adapt to the
rapidly changing requirements of the emerging
ADSL2+ Triple-play market covering data, voice
and video applications. Features Multi-standard support G.992.1 annexA,B,C (SBM/DBM) & I G.992.2 - g.Lite G.992.3 annexA,B,I,J,L (extended reach),M
(double upstream) G.992.4 - g.Lite.bis G.992.5 annexA,B,C,I,J,M ANSI T1.413 Issue2 ETSI TS 101 388 ADSL-over-ISDN Reduced Bill of Materials due to integration of : Line driver Tunable Rx and Tx-fitlers Voltage regulator for 2.5V Dying gasp comparator 13dBm online capable More than 14bit resolution DAC/ADC 70MS/s ADC interface and 8.8MS/s AC 4th order tunable continuous-time receive and
transmit filters Low noise PGA's and 8dB Tx gain tuning Tripple Rx input channel configuration Supply Voltage : 5V and 3.3V Typical power consumption : 750 mW Temperature range : I-range (-40°C to 85°C) Package : TQFP100
Figure 2. ST20184 Block Diagram
ADSL2+ ANALOG FRONT END
FOR CPE APPLICATIONS
Rev. 1
ST20184 General Description
The new ADSL2+ standards will accelerate Broadband applications way beyond always-on data stream-
ing, mainly used for web-browsing and e-mailing. Internet Service Providers are exploring several ways
to increase their revenues by offering new services and applications and enlarging their customer base.
This can be realized using the large number of new features and different annexes of ADSL2+.
Compared to its widely deployed predecessors, MTC20154 and MTC20174, the ST20184 has been de-
signed in a shorter gate-length, state-of-the-art analogue CMOS technology. Due to the transition in semi-
conductor technology and the introduction of advanced design techniques, CAD tools and simulation
software, the performances have been optimized to define the next generation requirements.
The ST20184 contains a integrated Line Driver supplied at 5V. In the receiving path great care has been
taken to lower the noise floor, increase the dynamic range and linearity of the programmable gain ampli-
fiers (LNA's). In both Rx and Tx path tunable, active filters have been integrated to deal with the different
frequency allocations for upstream an downstream bands. The analogue/digital conversions are done by
a more than 14bit resolution ADC and DAC.
For external BOM cost reduction a 2.5V Voltage regulator and dying gasp comparator is integrated and
Digital clock recovery or Time domain interpolation has been implemented only requiring a X-tal to be
hooked-up to the chip. Functional Description
The ST20184 consists of the following functional blocks (see figure 3):
Figure 3. Functional block diagram of ST20184
The analog and digital part have separated 2.5V power supplies. They can be generated internally from
the 3.3V supply. In addition some part of the analog section of the ST20184 has a power supply of 5V.
The digital I/Os work on an additional 3.3V supply.
4.1 THE RECEIVER (RX)
In the RX direction, a LNA (Low Noise Amplifier) provides a first amplification/attenuation stage. Its role is
to make the signal fit in the RX input dynamic range while using the maximum amplification for noise re-
duction. The RX HPF is a 3rd order high pass filter with a switchable cut-off frequency of 140 kHz (Annex
A,C,I,L) or 280 kHz (Annex B,J,M). It removes a part of the echo signal allowing the use of a low order,
external, high pass filter. The second LNA provides a second amplification made possible by the prior fil-
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ST20184
ter. A low pass 2nd order filter is added before the ADC for anti-aliasing purposes. Analog-to-digital con-
version at 70 MS/s and multiplexing to the 35 MHz RX bus take place before the signal is sent to the digital
interface.
Figure 4. Receiver Block diagram
4.2 THE TRANSMITTER (TX)
In the TX direction, the data coming from the digital interface is de-multiplexed and converted to an analog
signal. Next is a 2nd order low-pass filter with a switchable cut-off frequency of 160 kHz (Annex A,C,I,L)
or 320 kHz (Annex B,J,M). Its output is amplified by the TX line driver that also provides a 2nd order But-
terworth lowpass filtering.
Figure 5. Transmitter Block diagram
4.3 FILTER TUNING AND DYING GASP
A filter-tuning module is implemented in order to fine-tune each filter's cut-off frequency (fc) to compensate
process variation.
A dying gasp controller is provided on the chip. It consists of a comparator that compares an external volt-
age coming from a power supply with an internal reference voltage.
4.4 THE DIGITAL INTERFACE
The digital interface block implements all the logic required to provide access in read and write mode to
all the configuration and status registers. It can be divided into two parts: The data interface that converts the multiplexed data from/to the DMT signal processor into valid rep-
resentation for the TX DAC and RX ADC. The control interface that allows the board processor to configure the ST20184 settings (RX/TX
gains, filter band, etc.).
ST20184
4.5 ATU-R BLOCK DIAGRAM
An ATU-R block diagram of the analog front end is presented in the following figure. In addition to the
ST20184, the following blocks are a possible implementation to complete the line interface.
An external RX high pass filter is a third order filter that filters out the echo from the TX path. The ST-
20184's internal high pass filter completes the echo cancelling in the RX path.
The hybrid is using a structure which is cost and space effective and it is characterized by minimum losses.
The hybrid circuit provides also the necessary line impedance matching.
High pass filters at the end of the line interface filter out the POTS or ISDN band signals. DC blocking is
an additional function of these filters.
The ADSL analog front end integrated circuit does not contain any circuitry for the POTS or ISDN service
but guarantees that the POTS or ISDN bandwidth will not be disturbed by spurious signals from the ADSL
spectrum.
Figure 6. ATU-R AFE Block Diagram
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ST20184
4.6 ST20184 RX PATH
4.6.1 Low Noise Amplifier (LNA1)
Figure 7. Low Noise Amplifier 1 a/b or c
The Low Noise Amplifier (LNA1 a/b or c) is used in combination with the attenuator block to fit the input
signal in the 3 volt peak differential output dynamic range.
The gain settings may vary from -9 to 30dB
Table 2. LNA1a/b Characteristics
ST20184
Table 3. LNA1c Characteristics
Table 2. LNA1a/b Characteristics (continued)
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ST20184
4.6.2 RX Integrated High Pass Filter
The RX high pass filter attenuates the echo signal at low frequencies to allow a further amplification of the
receive signal resulting in a better RX sensitivity.
The RX High Pass Filter has a switchable notch frequency at tone 14 for Annex A,C,I,L, or tone 27 for
Annex B,J,M. In addition, it can be bypassed during handshake in Annex C.
The integrated high pass filter has characteristics shown in table 3.
Table 4. RX Band Pass Filter Characteristics
4.6.3 Low Noise Amplifier (LNA2)
This block optimizes the signal amplitude for best use of the ADC input dynamic range. It converts the 3
volts peak differential input dynamic into 1 volt peak differential output dynamic range.
Table 5. LNA2 Specification
Table 3. LNA1c Characteristics (continued)
ST20184
4.6.4 RX Low Pass Filter
This block implements the RX anti-aliasing filtering, attenuates the DMT sidelobe and out of band signals.
It also shifts the common mode voltage of the 5V powered LNA2 to the correct level for the 2.5V powered
ADC. It is designed according to the following characteristics.
Table 6. RX Low Pass Filter Characteristics
4.6.5 A/D Converter
A Sigma-Delta architecture is used for the A/D converter.
Table 7. A/D Converter Specifications
4.7 ST20184 TX PATH
4.7.1 TX Driver
The differential line driver buffers and amplifies the output of the TX filter in the TX signal path and reduces
the out of band noise by means of a second order RC LPF. It is a class AB line driver with fixed gain set-
tings (3 dB). Additionally, The line driver incorporates a digitally controlled bias setting. The distortion of
the line driver is better than -65dB over the ADSL upstream band with a a differential load of 12.5Ω. The
peak differential output swing is 4V.
The line driver characteristics are listed in the following table 8.
To ensure the stability of the line driver, the impedance it sees must be low enough up to high frequencies
(100MHz). As in the application an external LC filter, the leakage inductance of the transformer or even
the PCB tracks are an inductive load with increased impedance at high frequency, a stabilizer is added
close to the TXP/TXN pins. It consists of an RC network as in following figure. At low frequencies (within
US range) the capacitor must be sufficiently small to avoid loading the driver. At high frequencies the im-
pedance of the capacitor becomes negligible so that the Line Driver sees the 6 ohm resistor (12 Ohm dif-
ferential).
Figure 8. TX Driver stabilizer network
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ST20184
Table 8. TX Driver Characteristics
4.7.2 TX Low Pass Filter
This filter performs the TX path out-of-band signal cancellation in order to in order to reduce Downstream
signal degradation signal degradation due to NEXT (Near End Crosstalk). The TX low pass filter is also
acting as a smoothing filter on the D/A converter output to suppress the image spectrum.
The TX Low Pass Filter has a switchable cut-off frequency of 160 kHz for Annex A,C,I,L, or 320kHz for
Annex B,J,M.
It is designed according to the following characteristics.
Table 9. TX Low Pass Filter Specification
ST20184
4.7.3 Digital To Analog Converter (DAC)
A current steering architecture is used. The characteristics are as following
Table 10. DAC Specifications
4.7.4 PLL Based Frequency Multiplier
A simple 17.644 MHz crystal frequency can be used with the ST20184 on-board crystal driver.
A frequency multiplier, build up around an integrated Phase Locked Loop (PLL), is used to multiply the
frequency to 35.328 Mhz (CLKM) and 70.656Mhz (ADC).
4.7.5 Dying Gasp
The dying gasp circuit monitors an external voltage derived from an external power supply voltage. A com-
parator compares this voltage with a reference voltage. A possible loss in power is detected and signaled
to the digital integrated circuit ST20196 which in turn generates an interrupt. Two external resistors (R1,
R2 in the figure below) are used in order to trim the external voltage extracted from the power supply volt-
age to the desired level. Depending on the supply voltage that is used, the time before the regulated sup-
ply drops below the requirements has to be sufficient for the power down to be implemented properly.
Figure 9. The Dying Gasp Circuit
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ST20184
Table 11. Dying Gasp
4.7.6 Voltage regulator
The voltage regulator has the function to provide the analog 2.5V power supply for the C184 chip.
The input power supply VRegIn is the 3.3V. Good HF quality and low ESR (lower than 1 ohm at 10kHz)
capacitors are required for decoupling.
Two reference voltages are generated internally. The reference voltage coming from an internal resistive
divider driven by 5V supply (VRefIn pin 7) is filtered out by an external cap on pin VRefCap (pin 8). The
second reference voltage is based on theVRegIn voltage (pin34).
The reference voltage is defined by means of bit 11 in register &X1101.(Bit LDO_USB). When LDO_USB
is at zero, which is the default condition, the reference voltage is based on VRefIn pin. When LDO_USB
is forced to one, the reference voltage is based on VRegIn pin.
Table 12.
4.7.7 Power-On-Reset circuit
A double Power-On-Reset circuit (POR) is used in order to generate an internal reset in case of power
supply lower than the PorL threshold and will be released when above PorH threshold. That internal reset
signal complementary to the hard reset (applied on reset input pin) guarantees that the C184 chip is work-
ing under normal condition and places the driver in a self-protected mode.
A POR circuit is placed on each power supply (AVDD5 and AVSS25) and has the threshold levels depict-
ed in following table. Both POR outputs are monitored separately by the modem chip via the ctrl interface.
Their values can be read as POR25 and POR5 in register &X1011. These signals are set when a high
level or rising edge is generated by the internal POR5 and POR25 circuit. The value of these bits are reset
when they have been read through the control interface.
POR5 monitors the voltage of VREFIN pin (pin 7) and POR25 monitors the voltage of DVDD25PLL
(pin82).
Table 13.
ST20184
4.7.8 HYBRID SWITCHES
C184 has two low impedant switches on board. They are used to stabilize the input impedance of LNA1.
The switches can be controlled by means of HYBRID_CTRL<1:0> in register &X1111. The switch be-
tween terminal SW1P (pin 37) and SW1N (pin 38) is closed when HYBRID_CTRL<1> is forced to one,
and opened when HYBRID_CTRL<1> is forced to zero. The switch between terminal SW2P (pin 39) and
SW2N (pin 40) is closed when HYBRID_CTRL<0> is forced to one, and opened when HYBRID_CTRL<0>
is forced to zero.
Table 14.
4.8 Digital Interface
4.8.1 Digital Interface Blocks
The ST20184's digital interface is composed of a bidirectional serial control interface (CTRLIN-CTRLOUT
pins), one transmit data 4-bit wide parallel interface (TXn pins) and one receive data 10-bit wide parallel
interface (RXn pins). The interfaces are used as follows: The control interface is dedicated to send and read commands towards the ST20184. The interface is
synchronized over the word clock (CLKWD pin). The TXn interface is used to send digital words (16 bits) over the TX path DAC. The words are
multiplexed over the 4 bit wide bus using the word clock as "start word" time reference. The bus is
synchronized over the master clock @ 35.328MHz (CLKM pin). The RXn interface does not behave like the TX bus. It is dedicated to the PDM stream generated by
the ADC. Two samples of each 5 bits will be multiplexed to a 10 bit bus running at 35.328MHz (CLKM).
4.8.2 Master and Word Clock
The system's master clock has a nominal frequency of 35.328 MHz. Based on this clock, a word clock is
generated. It is used to synchronise the data multiplexed on the RX and TX buses of the ST20184. The
CTRLIN/OUT serial interface will be also totally synchronised on this clock. The word clock is a square
pulse having a high level duration (width) equal to one master clock period and a period equal to four mas-
ter clock periods. The figure here below depicts the signal characteristics.
Figure 10. Word clock generation
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ST20184
4.8.3 Control interface (CTRLIN/OUT pins)
The control interface is bi-directional, allowing the modem chip to send commands towards the analog
chip, and also to read the values of its internal registers. A 16-bit control message can be exchanged with
the analog ASIC. It is composed of 12 control data bits (CtrlD), and 4 control command bits (CtrlC). The
format is detailed in the table below. Note that it differs from the one introduced for the ST20174.
4.8.4 Write access to the ST20184
The bit sequence that is transferred is composed of 5 parts: a leading start bit, four bits representing an
address (CtrlC), a logic zero to indicate it is a write access, 12 bits of data (CtrlD), and 1 stop bit. This bit
sequence is transmitted on the serial interface at a rate defined by CLWD
Figure 11. Serial control interface for write accesses to 20184.
4.8.5 Read access to the ST20184
For this type of accesses, the CTRLIN pin is used, in addition to the already existing CTRLOUT.
The exchange of data takes place in the following order: The Modem chip transmits a leading start bit, four
bits representing an address (CtrlC), and a logic one to indicate it is a read access. With the following
CLWD pulse, the analog ASIC provides the 12 bits corresponding to the data addressed (CtrlD), and re-
turns to logic zero.
Figure 12. Serial control interface for read accesses to 20184.
ST20184
4.8.6 Control interface timing
The control interface bits are considered valid on each positive edge of the word clock. They will be sam-
pled at this moment. The stop bit will trigger the internal data validation.
Figure 13. Control interface chronodiagram
Table 15. Control interface timing requirements
4.8.7 Control interface bit mapping
The following table depicts all the available control command op-codes and their corresponding data.
Table 16. CTRL interface op-codes and corresponding data
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ST20184
Table 16. CTRL interface op-codes and corresponding data (continued)
ST20184
Table 16. CTRL interface op-codes and corresponding data (continued)

Partno	Mfg	Dc	Qty	Available	Descript
ST20184	ST	N/a	24	avai	ADSL2+ ANALOG FRONT END FOR CPE APPLICATIONS