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ST1G3234BJRSTN/a256094avai1-BIT DUAL SUPPLY BUS BUFFER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR
ST1G3234BJRSTMN/a6200avai1-BIT DUAL SUPPLY BUS BUFFER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR


ST1G3234BJR ,1-BIT DUAL SUPPLY BUS BUFFER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTORLogic Diagram LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD ..
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ST1G3234BJR
1-BIT DUAL SUPPLY BUS BUFFER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR
1/11February 2005 HIGH SPEED: tPD = 4.4ns (MAX.) at TA =85°C CCB = 1.65V; V CCA = 3.0V LOW POWER DISSIPATION: CCA = I CCB = 5µA(MAX.) at TA =85°C SYMMETRICAL OUTPUT IMPEDANCE: OHA | = I OLA = 10mA MIN at
VCCA = 2.75V; VCCB = 1.4V to 3.6V OHA | = I OLA = 6mA MIN at CCA = 2.3V; V CCB = 1.4 to 3.6V) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS 26Ω SERIES RESISTOR ON A SIDE OUTPUTS OPERATING VOLTAGE RANGE:
VCCA(OPR) = 1.4V to 3.6V (1.2V Data Retent)
VCCB(OPR) = 1.4V to 3.6V (1.2V Data Retent) LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17) ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V ROHS Compliant for FLIPCHIP Package
DESCRIPTION

The ST1G3234 is a dual supply low voltage
CMOS 1-BIT BUS BUFFER level translator
fabricated with sub-micron silicon gate and
five-layer metal wiring C2 MOS technology.
Designed for use as an interface between a 3.3V
bus and a 2.5V or 1.8V bus in a mixed 3.3V/1.8V,
3.3V/2.5V, 1.8V/1.4V and 2.5V/1.8V supply
systems, it achieves high speed operation while
maintaining the CMOS low power dissipation.
This IC is intended for one-way asynchronous
communication between data buses. The input
and output power down protections disable the
device when both power supply are down, so that
the buses are effectively isolated.
The input tolerant buffers allow to translate V CCBcompatible signals and greater signals than VCCB
up/down to VCCA.
All inputs are equipped with protection circuits
against static discharge, giving them ESD immuni-
ty and transient excess voltage.
ST1G3234

1-BIT DUAL SUPPLY BUS BUFFER LEVEL TRANSLATOR
WITH A SIDE SERIES RESISTOR
Table 1: Order Codes
PRODUCT PREVIEW
Figure 1: Logic Diagram

Rev. 3
ST1G3234
2/11
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
Figure 3: Pin Connection (Top through view)
Table 3: Truth Table
ST1G3234
3/11
Table 4: Absolute Maximum Ratings

Absolute Maximum Ratings are those value beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions

1) VI from 0.8V to 2.0V at VCC = 3.0V
ST1G3234
4/11
Table 6: DC Specification

(*) VCC range = 3.3±0.3; 2.5±0.2V; 1.8±0.15V
ST1G3234
5/11
Table 7: AC Electrical Characteristics
Table 8: Capacitance Characteristics

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per circuit)
ST1G3234
6/11
Figure 4: Test Circuit

CL = 10/30pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Table 9: Waveform Symbol Value
Figure 5: Waveform - Propagation Delay (f=1MHz; 50% duty cycle)
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