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ST1284-01A8-ST1284-02A8
PARALLEL PORT SINGLE TERMINATION NETWORK WITH +/-15KV ESD PROTECTION
ST1284-xxA8/T8July 2002 - Ed: 1B One devicefor parallel port termination Compliant with IEEE1284 standard EMI/ RFI noise filtering Highly integrated solutionin28 pin QSOP and
TSSOP packages One single device provides the proper termina-
tionfor8 datalines,1 strobe line,4 control lines
and4 statuts lines In system ESD protectionof ±15kV (air dis-
charge)as per IEC61000-4-2 level4
FEATURES
SCHEMATIC DIAGRAMPARALLEL PORT SINGLE TERMINATION
NETWORK WITH ±15kV ESD PROTECTIONA.S.D.TM
ECP/EPP Parallel Port termination on: Desktops Notebooks Workstations Servers PC Peripherals Set Top Box
MAIN APPLICATIONSThe ST1284-xxA8/T8isa highly integrated termi-
nationfor enhanced high speed parallel ports. The
integrated termination compliesto the IEEE1284
Standard recommendations and government
EMC compatibility requirements.Itis built around
two basic cells. The first one (Cell1) provides line
termination, EMI filtering and ESD protection for
the Strobe and Datalines while the second one
(Cell2) provides EMI filtering and ESD protection
for the Control and Status lines. In addition,
ST1284-xxA8 provides extra protection against
ESD. When tested accordingto IEC61000-4-2,
they withstand ±8kV contact discharges and
±15kV air-discharges, thereby providingto the
system the necessary robustnessto meet upto
level4of IEC61000-4-2, without the needfor addi-
tional ESD protection components. Cells1 and2
are describedin more detailin figures1 and2.
DESCRIPTION IEC61000-4-2 ±15kV (air discharge) 8kV (contact discharge) MIL STD 883E- Method 3015-7: Class3
(human body model).
COMPLIES WITH THE FOLLOWING ESD
STANDARDS:
ST1284-xxA8/T8
ABSOLUTE MAXIMUM RATINGS (Tamb 25°C)
ELECTRICAL CHARACTERISTICS (Tamb = 25°C)The ST1284-xxA8/T8is built around the two basic cells described below which integrate the recom-
mended IEEE1284 network and the ESD protection compatible with IEC61000-4-2 level4
BASIC CELL CONFIGURATIONSVcc
Gnd
Fig. 1:Cell1 for line termination, EMI filtering and
ESD protection for the Datalines and Strobe sig-
nals. There are9 of these cells inside the
ST1284-xxA8/T8
Vcc
Gnd
Fig.2: Cell2 for EMI filtering and ESD protection the Control and Status signals. There are8of
these cells inside the ST1284-xxA8/T8
ST1284-xxA8/T8The functional diagram here above presentsa IEEE1284-A connector pinout and show howto connect
the ST1284-xxA8/T8in orderto correctly terminate and filter the17 signal lines. The IEEE1284-A con-
nectoris the PC standardfor the host connection.
Control and status lines (from10to 17) only requirea pull-up resistor (Rp) anda filter capacitor (C).
The data lines (from2to9) and the STROBE (pin1) also requirea termination series resistor (Rs) additionto the pull-up resistor anda filter capacitor. The Vccis connectedto pin 20 and the
groundto pin 22.
The ST1284-xxA8/T8 canbe used withall3 typesof connectors definedin the IEEE1284 standard: IEEE1284-Aisa 25DB connector whichis the PC standard for the host connection. IEEE1284-Bisa36 pin, 0.085 inch centerline connector usedon the peripheral device. IEEE1284-Cisa new36 pin, 0.050 inch centerline connector which canbe usedfor both host and peripher-
als.
APPLICATION INFORMATION
ST1284-xxA8/T8
FREQUENCY BEHAVIOR OF DATA AND STROBE SIGNALS
TECHNICAL INFORMATION
Fig. A1: Measurement conditions
Fig. A2: Typical frequency response curvefor data
and strobe signals. additionto the requirementsof termination and EMC compatibility, computing devices are requiredtobe
testedfor ESD susceptibility. This testis describedin the IEC61000-4-2 andis alreadyin placein Europe.
This test requires thata device tolerates ESD events and remain operational without user intervention.
The ST1284-xxA8/T8is particularly optimizedto perform ESD protection. ESD protectionis basedon the
useof device which clampsat:
Vouput V RIBR dPP=+ .
This protection functionis splittedin2 stages.As shownin figure A3, the ESD strikes are clampedby the
first stage S1 and thenits remaining overvoltageis appliedto the second stage through the resistorR.
Sucha configuration makes the voltage very lowat the output.
ESD PROTECTION
Fig. A3: ST1284 ESD clamping behavior
ST1284-xxA8/T8 havea good approximationof the remaining voltagesat both Vin and Vout stages, we give the typical
dynamical resistance value Rd. By taking into account these following hypothesis: Rt>Rd, Rg>Rd and
Rload>Rd,it gives these formulas:
Vinput RV RV
gBR d PP= + ..
Voutput RV R Vinput
tBR d= + ..
The resultsof the calculation done for VPP=8kV, Rg=330Ω (IEC61000-4-2 standard), VBR=7V (typ.)
and Rd= 1Ω (typ.) give:
Vinput= 31.2V
Voutput= 7.95V
This confirms the very low remaining voltage across the devicetobe protected.Itis also importantto note
thatin this approximation the parasitic inductance effect was not taken into account. This couldbe few
tenthsof volts during fewnsat the input side. This parasitic effectis not presentat the output side due the
low current involved after the resistanceR.
The measurements done here after show very clearly (Fig. A5) the high efficiencyof the ESD protection:no influenceof the parasitic inductanceson Vout stage Voutput clamping voltage very closeto VBR (positive strike) and -VF (negative strike)
Fig. A4: Measurement conditions
Fig. A5: Remaining voltageat the input and output of the device duringa ±16kV ESD surge
(IEC61000-4-2).
ST1284-xxA8/T8
PACKAGE MECHANICAL DATAQSOP28 (Plastic)
PACKAGE MECHANICAL DATATSSOP28 (Plastic)
