ST10R167-Q3 ,16-BIT MCUST10C16716-BIT MCU WITH 32K BYTE ROM■ HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE– 80ns ..
ST10R167-Q6 ,16-BIT MCUABSOLUTE MAXIMUM RATINGS ..... 3820.2 PARAMETER INTERPRETATION ..... 3820.3 DC CHARACTERISTICS . 38 ..
ST10R167-Q6-TR ,16-BIT MCUST10R16716-BIT ROMLESS MCU■ HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE– 80ns INSTRUCTI ..
ST10R172LT1 ,16-BIT LOW VOLTAGE ROMLESS MCUTable of Contents15.3 AC CHARACTERISTICS . 3615.3.1 Cpu Clock Generation Mechanisms . . ..
ST10R172LT6 ,16-BIT LOW VOLTAGE ROMLESS MCUST10R172L16-BIT LOW VOLTAGE ROMLESS MCUDATASHEET■ High Performance 16-bit CPU● CPU Frequency: 0 to ..
ST10R272LT1 ,16-BIT LOW VOLTAGE ROMLESS MCU WITH MACTable of Contents16.3 AC CHARACTERISTICS . 4516.3.1 CPU Clock Generation Mechanisms . . . ..
STK4913 ,Thick Film Hybid Circuit 2-Channel 50W Min AF Power Amp
STK4913 ,Thick Film Hybid Circuit 2-Channel 50W Min AF Power Amp
STK5314 ,Thick Film Hybrid Integrated Circuit VOLTAGE REGULATORNo. 1146STK5314Thick Film Hybrid Integrated Ci rcuitVOLTAGE REGULATOR
STK5325 , 2-CHANNEL 10 TO 50W MIN AF POWER AMP.(DUAL-SUPPLY)
STK5325 , 2-CHANNEL 10 TO 50W MIN AF POWER AMP.(DUAL-SUPPLY)
STK5451 ,3-Output Series Regulator for VTR UseNo.1663STK5451Thiekimm Hybrid IC3-Output Series Regulator for VTR is,
ST10R167-Q3-ST10R167-Q6
16-BIT MCU
1/66January 2002 HIGH PERFORMANCE CPU
– 16-BIT CPU WITH 4-STAGE PIPELINE
– 80ns INSTRUCTION CYCLE TIME @ 25MHz CLK
– 400ns 16 X 16-BIT MULTIPLICATION
– 800ns 32 / 16-BIT DIVISION
– ENHANCED BOOLEAN BIT MANIPULATION
FACILITIES
– ADDITIONAL INSTRUCTIONS TO SUPPORT HLL
AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING
SUPPORT� MEMORY ORGANIZATION
– 32K BYTE ON-CHIP ROM MEMORY
– UP TO 16M BYTE LINEAR ADDRESS SPACE FOR
CODE AND DATA (5M BYTE WITH CAN)
– 2K BYTE ON-CHIP INTERNAL RAM (IRAM)
– 2K BYTE ON-CHIP EXTENSION RAM (XRAM)� FAST AND FLEXIBLE BUS
– PROGRAMMABLE EXTERNAL BUS
CHARACTERISTICS FOR DIFFERENT ADDRESS
RANGES
– 8-BIT OR 16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTERNAL
ADDRESS/DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD-ACKNOWLEDGE BUS ARBITRATION
SUPPORT� INTERRUPT
– 8-CHANNEL PERIPHERAL EVENT CONTROLLER
FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA
TRANSFER
– 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH
56 SOURCES, SAMPLE-RATE DOWN TO 40ns TIMERS
– TWO MULTI-FUNCTIONAL GENERAL PURPOSE
TIMER UNITS WITH 5 TIMERS
– TWO 16-CHANNEL CAPTURE/COMPARE UNITS A/D CONVERTER
– 16-CHANNEL 10-BIT
– 7.76μs CONVERSION TIME� FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG� ON-CHIP CAN 2.0B INTERFACE� ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT UP TO 111 GENERAL PURPOSE I/O LINES
– INDIVIDUALLY PROGRAMMABLE AS INPUT,
OUTPUT OR SPECIAL FUNCTION
– PROGRAMMABLE DRIVE STRENGTH
– PROGRAMMABLE THRESHOLD (HYSTERESIS)� IDLE AND POWER DOWN MODES
– IDLE CURRENT <95mA
– POWER-DOWN SUPPLY CURRENT <400μA� 4-CHANNEL PWM UNIT� SERIAL CHANNELS
– SYNCHRONOUS/ASYNC SERIAL CHANNEL
– HIGH-SPEED SYNCHRONOUS CHANNEL DEVELOPMENT SUPPORT
– C-COMPILERS, MACRO-ASSEMBLER PACKAG-
ES, EMULATORS, EVAL BOARDS, HLL-DEBUG-
GERS, SIMULATORS, LOGIC ANALYZER
DISASSEMBLERS, PROGRAMMING BOARDS� 144-PIN PQFP PACKAGE
ST10C16716-BIT MCU WITH 32K BYTE ROM
ST10C1672/66
TABLE OF CONTENTS Page INTRODUCTION ......................................................................................................... 4 PIN DATA .................................................................................................................. 5 FUNCTIONAL DESCRIPTION.................................................................................... 10 MEMORY ORGANIZATION........................................................................................ 11 CENTRAL PROCESSING UNIT (CPU)...................................................................... 12
6 EXTERNAL BUS CONTROLLER............................................................................... 13
7 INTERRUPT SYSTEM ................................................................................................ 14 CAPTURE/COMPARE (CAPCOM) UNIT ................................................................... 17 GENERAL PURPOSE TIMER UNIT........................................................................... 189.1 GPT1 .......................................................................................................................... 18
9.2 GPT2 .......................................................................................................................... 19
10 PWM MODULE ........................................................................................................... 21
11 PARALLEL PORTS.................................................................................................... 22
12 A/D CONVERTER....................................................................................................... 23
13 SERIAL CHANNELS .................................................................................................. 24
14 CAN MODULE ............................................................................................................ 26
15 WATCHDOG TIMER................................................................................................... 26
16 INSTRUCTION SET SUMMARY ................................................................................ 27
17 SYSTEM RESET ......................................................................................................... 29
18 POWER REDUCTION MODES .................................................................................. 30
19 SPECIAL FUNCTION REGISTER OVERVIEW.......................................................... 3119.1 IDENTIFICATION REGISTERS ................................................................................. 37
20 ELECTRICAL CHARACTERISTICS .......................................................................... 3820.1 ABSOLUTE MAXIMUM RATINGS ............................................................................. 38
20.2 PARAMETER INTERPRETATION ............................................................................. 38
20.3 DC CHARACTERISTICS ........................................................................................... 38
20.3.1 A/D converter characteristics ...................................................................................... 40
20.4 AC CHARACTERISTICS ............................................................................................ 41
20.4.1 Definition of internal timing ......................................................................................... 42
20.4.2 Clock generation modes ............................................................................................. 42
ST10C1673/66
20.4.3 Prescaler operation .................................................................................................... 43
20.4.4 Direct drive ................................................................................................................. 43
20.4.5 Oscillator watchdog (OWD) ........................................................................................ 43
20.4.6 Phase locked loop ...................................................................................................... 43
20.4.7 Memory cycle variables .............................................................................................. 44
20.4.8 External clock drive XTAL1 ........................................................................................ 45
20.4.9 Multiplexed bus ........................................................................................................... 46
20.4.10 Demultiplexed bus ......................................................................................................52
20.4.11 CLKOUT and READY ................................................................................................. 58
20.4.12 External bus arbitration ...............................................................................................60
20.4.13 High-speed synchronous serial interface (SSC) timing .............................................. 61
21 PACKAGE MECHANICAL DATA ........................................................................... 64
22 ORDERING INFORMATION....................................................................................... 65
ST10C1674/66
1 - INTRODUCTIONThe ST10C167 is a derivative of the
STMicroelectronics ST10 family of 16-bit
single-chip CMOS microcontrollers. It combines
high CPU performance (up to 12.5 million
instructions per second) with high peripheral
functionality and enhanced I/O capabilities.
It also provides on-chip high-speed RAM and
clock generation via PLL.
Figure 1 : Logic Symbol
ST10C1675/66
2 - PIN DATA
Figure 2 : Pin Configuration (top view)
ST10C1676/66
Table 1 : Pin list
ST10C1677/66
Table 1 : Pin list (continued)
ST10C1678/66
Table 1 : Pin list (continued)
ST10C1679/66
Table 1 : Pin list (continued)
ST10C16710/66
3 - FUNCTIONAL DESCRIPTIONThe architecture of the ST10C167 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The
block diagram gives an overview of the different
on-chip components and the high bandwidth inter-
nal bus structure of the ST10C167.
Figure 3 : Block diagram
ST10C16711/66
4 - MEMORY ORGANIZATIONThe memory space of the ST10C167 is
configured in a Von-Neumann architecture. Code
memory, data memory , registers and I/O ports are
organized within the same linear address space of
16M Byte.
The entire memory space can be accessed Byte-
wise or Wordwise. Particular portions of the
on-chip memory have additionally been made
directly bit addressable.
ROM : 32K Byte of on-chip ROM.
RAM : 2K Byte of on-chip internal RAM
(dual-port) is provided as a storage for data, sys-
tem stack, general purpose register banks and
code. The register bank can consist of up to 16
wordwide (R0 to R15) and/or Bytewide (RL0,
RH0, …, RL7, RH7) general purpose registers.
XRAM : 2K Byte of on-chip extension RAM (sin-
gle port XRAM) is provided as a storage for data,
user stack and code.
The XRAM is connected to the internal XBUS and
is accessed like an external memory in 16-bit
demultiplexed bus-mode without waitstate or
read/write delay (80ns access at 25MHz CPU
clock). Byte and Word access is allowed.
The XRAM address range is 00’E000h -
00’E7FFh if the XRAM is enabled (XPEN bit 2 of
SYSCON register). As the XRAM appears like
external memory, it cannot be used for the
ST10C167’s system stack or register banks. The
XRAM is not provided for single bit storage and
therefore is not bit addressable. If bit XRAMEN is
cleared, then any access in the address range
00’E000h - 00’E7FFh will be directed to external
memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx
register.
SFR/ESFR : 1024 Byte (2 * 512 Byte) of addressspace is reserved for the special function register
areas. SFRs are wordwide registers which are
used for controlling and monitoring functions of
the different on-chip units.
CAN : Address range 00’EF00h - 00’EFFFh is
reserved for the CAN Module access. The CAN is
enabled by setting XPEN bit 2 of the SYSCON
register. Accesses to the CAN Module use demul-
tiplexed addresses and a 16-bit data bus (Byte
accesses are possible). Two wait states give an
access time of 160ns at 25MHz CPU clock. No
tristate waitstate is used.
Note If the CAN module is used, Port 4 can not
be programmed to output all 8 segment
address lines. Thus, only 4 segment
address lines can be used, reducing the
external memory space to 5M Byte (1M
Byte per CS line).
In order to meet the needs of designs where more
memory is required than is provided on chip, up to
16M Byte of external RAM and/or ROM can be
connected to the microcontroller.
ST10C16712/66
5 - CENTRAL PROCESSING UNIT (CPU)The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi-
cated SFRs. Additional hardware has been added
for a separate multiply and divide unit, a bit-mask
generator and a barrel shifter.
Most of the ST10C167’s instructions can be exe-
cuted in one instruction cycle which requires 80ns
at 25MHz CPU clock. For example, shift and
rotate instructions are processed in one instruc-
tion cycle independent of the number of bits to be
shifted. Multiple-cycle instructions have been opti-
mized: branches are carried out in 2 cycles, 16 x
16 bit multiplication in 5 cycles and a 32/16 bit
division in 10 cycles.The jump cache reduces the
execution time of repeatedly performed jumps in a
loop, from 2 cycles to 1 cycle.
The CPU uses an actual register context
consisting of up to 16 Word wide GPRs physically
allocated within the on-chip RAM area. A Context
Pointer (CP) register determines the base
address of the active register bank to be accessed
by the CPU. The number of register banks is only
restricted by the available internal RAM space.
For easy parameter passing, a register bank may
overlap others.
A system stack of up to 1024 Byte is provided as a
storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and
STKUN, are implicitly compared against the stack
pointer value upon each stack access for the
detection of a stack overflow or underflow.
Figure 4 : CPU Block Diagram
ST10C16713/66
6 - EXTERNAL BUS CONTROLLERAll of the external memory accesses are per-
formed by the on-chip external bus controller. The
EBC can be programmed to single chip mode
when no external memory is required, or to one of
four different external memory access modes:
– 16-/18-/20-/24-bit addresses and 16-bit data,
demultiplexed.
– 16-/18-/20-/24-bit addresses and 16-bit data,
multiplexed.
– 16-/18-/20-/24-bit addresses and 8-bit data,
multiplexed.
– 16-/18-/20-/24-bit addresses and 8-bit data, de-
multiplexed.
In demultiplexed bus modes addresses are output
on Port1 and data is input/output on Port0 or P0L,
respectively. In the multiplexed bus modes both
addresses and data use Port0 for input/output.
Timing characteristics of the external bus inter-
face (memory cycle time, memory tri-state time,
length of ALE and read/write delay) are program-
mable giving the choice of a wide range of memo-
ries and external peripherals. Up to 4 independent
address windows may be defined (using register
pairs ADDRSELx / BUSCONx) to access different
resources and bus characteristics. These address
windows are arranged hierarchically where
BUSCON4 overrides BUSCON3 and BUSCON2
overrides BUSCON1. All accesses to locations
not covered by these 4 address windows are con-
trolled by BUSCON0. Up to 5 external CS signals windows plus default) can be generated in
order to save external glue logic. Access to very
slow memories is supported by a ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbi-
tration which shares external resources with other
bus masters. The bus arbitration is enabled by
setting bit HLDEN in register SYSCON. After set-
ting HLDEN once, pins P6.7...P6.5 (BREQ,
HLDA, HOLD) are automatically controlled by the
EBC. In master mode (default after reset) the
HLDA pin is an output. By setting bit DP6.7 to’1’
the slave mode is selected where pin HLDA is
switched to input. This directly connects the slave
controller to another master controller without
glue logic.
For applications which require less external mem-
ory space, the address space can be restricted to
1M Byte, 256K Byte or to 64K Byte. Port 4 outputs
all 8 address lines if an address space of
16M Byte is used, otherwise four, two or no
address lines.
Chip select timing can be made programmable.
By default (after reset), the CSx lines change half
a CPU clock cycle after the rising edge of ALE.
With the CSCFG bit set in the SYSCON register
the CSx lines change with the rising edge of ALE.
The active level of the READY pin can be set by
bit RDYPOL in the BUSCONx registers. When the
READY function is enabled for a specific address
window, each bus cycle within the window must
be terminated with the active level defined by bit
RDYPOL in the associated BUSCON register.
ST10C16714/66
7 - INTERRUPT SYSTEMThe interrupt response time for internal program
execution is from 200ns to 480ns.
The ST10C167 architecture supports several
mechanisms for fast and flexible response to ser-
vice requests that can be generated from various
sources internal or external to the microcontroller.
Any of these interrupt requests can be serviced by
the Interrupt Controller or by the Peripheral Event
Controller (PEC).
In contrast to a standard interrupt service where
the current program execution is suspended and
a branch to the interrupt vector table is performed,
just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service
implies a single Byte or Word data transfer
between any two memory locations with an addi-
tional increment of either the PEC source or the
destination pointer. An individual PEC transfer
counter is implicitly decremented for each PEC
service except when performing in the continuous
transfer mode. When this counter reaches zero, a
standard interrupt is performed to the correspond-
ing source related vector location. PEC services
are very well suited, for example, for supporting
the transmission or reception of blocks of data.
The ST10C167 has 8 PEC channels each of
which offers such fast interrupt-driven data trans-
fer capabilities.
A interrupt control register which contains an
interrupt request flag, an interrupt enable flag and
an interrupt priority bitfield is dedicated to each
existing interrupt source. Thanks to its related
register, each source can be programmed to one
of sixteen interrupt priority levels. Once starting to
be processed by the CPU, an interrupt service
can only be interrupted by a higher prioritized
service request. For the standard interrupt
processing, each of the possible interrupt sources
has a dedicated vector location.
Fast external interrupt inputs are provided to ser-
vice external interrupts with high precision
requirements. These fast interrupt inputs feature
programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the
‘TRAP’ instruction in combination with an individ-
ual trap (interrupt) number.
Table 2 shows all the available ST10C167 inter-
rupt sources and the corresponding hard-
ware-related interrupt flags, vectors, vector
locations and trap (interrupt) numbers :
Table 2 : Interrupt sources
ST10C16715/66
Table 2 : Interrupt sources (continued)
ST10C16716/66
Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable system reaction similar to a stan-
dard interrupt service (branching to a dedicated
vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag regis-
ter (TFR). Except when another higher prioritized
trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn,
hardware trap services can normally not be inter-
rupted by standard or PEC interrupts.
Table 3 shows all of the possible exceptions or
error conditions that can arise during run-time:
Table 3 : Exceptions or error conditions that can arise during run time
ST10C16717/66
8 - CAPTURE/COMPARE (CAPCOM) UNITThe ST10C167 has two 16 channel CAPCOM
units. They support generation and control of
timing sequences on up to 32 channels with a
maximum resolution of 320ns at 25MHz CPU
clock. The CAPCOM units are typically used to
handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion,
software timing, or time recording relative to
external events.
Four 16-bit timers (T0/T1, T7/T8) with reload
registers provide two independent time bases for
the capture/compare register array.
The input clock for the timers is programmable to
several prescaled values of the internal system
clock, or may be derived from an overflow/
underflow of timer T6 in module GPT2. This
provides a wide range of variation for the timer
period and resolution and allows precise
adjustments to application specific requirements.
In addition, external count inputs for CAPCOM
timers T0 and T7 allow event scheduling for the
capture/compare registers relative to external
events.
Each of the two capture/compare register arrays
contain 16 dual purpose capture/compare
registers, each of which may be individually
allocated to either CAPCOM timer T0 or T1 (T7 or
T8, respectively), and programmed for capture or
compare functions. Each register has one
associated port pin which serves as an input pin
for triggering the capture function, or as an output
pin (except for CC24...CC27) to indicate the
occurrence of a compare event.
When a capture/compare register has been
selected for capture mode, the current contents of
the allocated timer will be latched (captured) into
the capture/compare register in response to an
external event at the port pin which is associated
with this register. In addition, a specific interrupt
request for this capture/compare register is
generated. Either a positive, a negative, or both a
positive and a negative external signal transition
at the pin can be selected as the triggering event.
The contents of all registers which have been
selected for one of the five compare modes are
continuously compared with the contents of the
allocated timers. When a match occurs between
the timer value and the value in a capture/
compare register, specific actions will be taken
based on the selected compare mode (see
Table4).
The input frequencies fTx for Tx are determined as
a function of the CPU clocks. The formulas are
detailed in the user manual. The timer input fre-
quencies, resolution and periods which result
from the selected pre-scaler option in TxI when
using a 25MHz CPU clock are listed in the table
below. The numbers for the timer periods are
based on a reload value of 0000H . Note that some
numbers may be rounded to 3 significant figures
(see T able 5).
Table 4 : Compare modes
Table 5 : CAPCOM timer input frequencies, resolution and periods
ST10C16718/66
9 - GENERAL PURPOSE TIMER UNITThe GPT unit is a flexible multifunctional timer/
counter structure which is used for time related
tasks such as event timing and counting, pulse
width and duty cycle measurements, pulse
generation, or pulse multiplication. The GPT unit
contains five 16-bit timers organized into two
separate modules GPT1 and GPT2. Each timer in
each module may operate independently in
several different modes, or may be concatenated
with another timer of the same module.
9.1 - GPT1Each of the three timers T2, T3, T4 of the GPT1
module can be configured individually for one of
four basic modes of operation:
timer, gated
timer, counter mode and incremental interface
mode. In timer mode, the input clock for a timer isderived from the CPU clock, divided by a pro-
grammable prescaler. In counter mode, the timer
is clocked in reference to external events. Pulse
width or duty cycle measurement is supported in
gated timer mode where the operation of a timer is
controlled by the ‘gate’ level on an external input
pin. For these purposes, each timer has one asso-
ciated port pin (TxIN) which is the gate or the
clock input.
The table below lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 25MHz CPU clock. This also applies to the
Gated Timer Mode of T3 and to the auxiliary
timers T2 and T4 in Timer and Gated Timer Mode
(see T able6).
The count direction (up/down) for each timer is
programmable by software or may additionally be
altered dynamically by an external signal on a port
pin (TxEUD).
In Incremental Interface Mode, the GPT1 timers
(T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B by
their respective inputs TxIN and TxEUD. Direction
and count signals are internally derived from
these two input signals so that the contents of the
respective timer Tx corresponds to the sensor
position. The third position sensor signal TOP0
can be connected to an interrupt input.
Timer T3 has output toggle latches (TxOTL) which
changes state on each timer over-flow/underflow.
The state of this latch may be output on port pins
(TxOUT) e. g. for time out monitoring of external
hardware components, or may be used internally
to clock timers T2 and T4 for high resolution mea-
surement of long time periods.
In addition to their basic operating modes, timers
T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or
reload registers, timers T2 and T4 are stopped.
The contents of timer T3 is captured into T2 or T4
in response to a signal at their associated input
pins (TxIN). Timer T3 is reloaded with the
contents of T2 or T4 triggered either by an
external signal or by a selectable state transition
of its toggle latch T3OTL. When both T2 and T4
are configured to alternately reload T3 on
opposite state transitions of T3OTL with the low
and high times of a PWM signal, this signal
canbe constantly generated without software
intervention.
Table 6 : GPT1 timer input frequencies, resolution and periods
ST10C16719/66
9.2 - GPT2The GPT2 module provides precise event control
and time measurement. It includes two timers (T5,
T6) and a capture/reload register (CAPREL). Both
timers can be clocked with an input clock which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction (up/down) for each timer is programma-
ble by software or may additionally be altered
dynamically by an external signal on a port pin
(TxEUD). Concatenation of the timers is sup-
ported via the output toggle latch (T6OTL) of timer
T6 which changes its state on each timer over-
flow/underflow.
The state of this latch may be used to clock timer
T5, or it may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register.
The CAPREL register may capture the contents of
timer T5 based on an external signal transition on
the corresponding port pin (CAPIN), and timer T5
may optionally be cleared after the capture proce-
dure. This allows absolute time differences to be
measured or pulse multiplication to be performed
without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3 inputs T3IN and/or T3EUD. This is advanta-
geous when T3 operates in Incremental Interface
Mode.
Table 7 lists the timer input frequencies, resolution
and periods for each pre-scaler option at 25MHz
CPU clock.
This also applies to the Gated Timer Mode of T6
and to the auxiliary timer T5 in Timer and Gated
Timer Mode.
Figure 5 : Block diagram of GPT1
ST10C16720/66
Table 7 : GPT2 timer input frequencies, resolution and periods
Figure 6 : Block diagram of GPT2
ST10C16721/66
10 - PWM MODULEThe pulse width modulation module can generate
up to four PWM output signals using edge-aligned
or centre-aligned PWM. In addition, the PWM
module can generate PWM burst signals and sin-
gle shot outputs. T able 8 shows the PWM fre-
quencies for different resolutions. The level of the
output signals is selectable and the PWM module
can generate interrupt requests.
Table 8 : PWM unit frequencies and resolution at 25MHz clock
Figure 7 : Block diagram of PWM module
ST10C16722/66
11 - PARALLEL PORTSThe ST10C167 provides up to 111 I/O lines orga-
nized into eight input/output ports and one input
port.
All port lines are bit-addressable, and all input/out-
put lines are individually (bit-wise) programmable
as input or output via direction registers. The I/O
ports are true bidirectional ports which are
switched to high impedance state when config-
ured as inputs.
The output drivers of five I/O ports can be config-
ured (pin by pin) for push/pull operation or
open-drain operation via control registers. During
the internal reset, all port pins are configured as
inputs.
The input threshold of Port 2, Port 3, Port 7 and
Port 8 is selectable (TTL-or CMOS-like), where
the special CMOS-like input threshold reduces
noise sensitivity due to the input hysteresis.
The input thresholds are selected with bit of
PICON register dedicated to blocks of 8 input pins
(2-bit for port2, 2-bit for port3, 1-bit for port7, 1-bit
for port8).
All pins of I/O ports also support an alternate pro-
grammable function:
– Port0 and Port1 may be used as address and
data lines when accessing external memory.
– Port 2, Port 7 and Port 8 are associated with the
capture inputs or with the compare outputs of
the CAPCOM units and/or with the outputs of
the PWM module.
– Port 3 includes the alternate functions of timers,
serial interfaces, the optional bus control signal
BHE and the system clock output (CLKOUT).
– Port 4 outputs the additional segment address
bits A16 to A23 in systems where segmentation
is enabled to access more than 64K Byte of
memory.
– Port 5 is used as analog input channels of the
A/D converter or as timer control signals.
– Port 6 provides optional bus arbitration signals
(BREQ, HLDA, HOLD) and chip select signals.
All port lines that are not used for alternate func-
tions may be used as general purpose I/O lines.
ST10C16723/66
12 - A/D CONVERTERA10-bit A/D converter with 16 multiplexed input
channels and a sample and hold circuit is inte-
grated on-chip. The sample time (for loading the
capacitors) and the conversion time is program-
mable and can be adjusted to the external circuitry.
Overrun error detection/protection is controlled by
the ADDAT register. Either an interrupt request is
generated when the result of a previous conver-
sion has not been read from the result register at
the time the next conversion is complete, or the
next conversion is suspended until the previous
result has been read. For applications which
require less than 16 analog input channels, the
remaining channel inputs can be used as digital
input port pins. The AD converter of the
ST10F168 supports different conversion modes :
– Single channel single conversion : the analog
level of the selected channel is sampled once
and converted. The result of the conversion is
stored in the ADDAT register.
– Single channel continuous
conversion : the
analog level of the selected channel is repeatedly
sampled and converted. The result of the conver-
sion is stored in the ADDAT register.
– Auto scan single conversion : the analog level
of the selected channels are sampled once and
converted. After each conversion the result is
stored in the ADDAT register. The data can be
transfered to the RAM by interrupt software
management or using the powerfull Peripheral
Event Controller data transfert.
– Auto scan continuous conversion : the ana-
log level of the selected channels are repeatedly
sampled and converted. The result of the con-
version is stored in the ADDAT register. The
data can be transfered to the RAM by interrupt
software management or using the powerfull
Peripheral Event Controller data transfert.
– Wait for ADDAT read mode : when using con-
tinuous modes, in order to avoid to overwrite
the result of the current conversion by the next
one, the ADWR bit of ADCON control register
must be activated. Then, until the ADDAT regis-
ter is read, the new result is stored in a tempo-
rary buffer and the conversion is on hold.
– Channel injection mode : when using
continuous modes, a selected channel can be
converted in between without changing the
current operating mode. The 10 bit data of the
conversion are stored in ADRES field of
ADDAT2. The current continuous mode remains
active after the single conversion is completed.
The T able : 9 ADC sample clock and conversion
time shows the ADC unit conversion clock, sample
clock.
A complete conversion will take 14tCC + 2 tSC + TCL. This time includes the conversion it-self,
the sampling time and the time required to trans-
fer the digital value to the result register. For
example, at 25MHz of CPU clock, minimum com-
plete conversion time is 7.76μs.
The A/D converter provides automatic offset and
linearity self calibration. The calibration operation
is performed in two ways:
– A full calibration sequence is performed after a
reset and lasts 1.6ms minimum (at 25MHz CPU
clock). During this time, the ADBSY flag is set to
indicate the operation. Normal conversion can
be performed during this time. The duration of
the calibration sequence is then extended by the
time consumed by the conversions.
Note : After a power-on reset, the total
unadjusted error (TUE) of the ADC might be
worse than ±2LSB (max. ±4LSB). During the full
calibration sequence, the TUE is constantly
improved until at the end of the cycle, TUE is
within the specified limits of ±2LSB.
– One calibration cycle is performed after each
conversion : each calibration cycle takes 4 ADC
clock cycles. These operation cycles ensure
constant updating of the ADC accuracy, com-
pensating changing operating conditions.
Note 1. See Section 20.4.4 - Direct drive on page43.
2. tCC = TCL x 24.
Table 9 : ADC sample clock and conversion time
ST10C16724/66
13 - SERIAL CHANNELSSerial communication with other microcontrollers,
processors, terminals or external peripheral com-
ponents is provided by two serial interfaces: the
asynchronous/synchronous serial channel
(ASC0) and the high-speed synchronous serial
channel (SSC).
Two dedicated Baud rate generators set up all
standard Baud rates without the requirement of
oscillator tuning.
For transmission, reception and erroneous recep-
tion, 3 separate interrupt vectors are provided for
each serial channel.
ASCOASCO supports full-duplex asynchronous
communication up to 781.25K Baud and
half-duplex synchronous communication up to Baud at 25MHz system clock. For
asynchronous operation, the Baud rate generator
provides a clock with 16 times the rate of the
established Baud rate.
The table below lists various commonly used
Baud rates together with the required reload val-
ues and the deviation errors compared to the
intended Baud rate (see Table 10).
For synchronous operation, the Baud rate genera-
tor provides a clock with 4 times the rate of the
established Baud rate.
Note The deviation errors given in the table above are rounded. Using a Baud rate crystal will provide correct Baud rates without deviation
errors.
Table 10 : Commonly used Baud rates by reload value and deviation errors
ST10C16725/66
High Speed Synchronous Serial Channel (SSC)The High-Speed Synchronous Serial Interface
SSC provides flexible high-speed serial
communication between the ST10C167 and other
microcontrollers, microprocessors or external
peripherals.
The SSC supports full-duplex and half-duplex
synchronous communication; The serial clock
signal can be generated by the SSC itself (master
mode) or be received from an external master
(slave mode). Data width, shift direction, clock
polarity and phase are programmable. This allows
communication with SPI-compatible devices.
Transmission and reception of data is
double-buffered. A 16-bit Baud rate generator
provides the SSC with a separate serial clock
signal. The serial channel SSC has its own
dedicated 16-bit Baud rate generator with 16-bit
reload capability, allowing Baud rate generation
independent from the timers.
SSCBR is the dual-function Baud Rate Generator/
Reload register. Table 11 lists some possible
Baud rates against the required reload values and
the resulting bit times for a 25MHz CPU clock.
Table 11 : Synchronous Baud rate and reload values
ST10C16726/66
14 - CAN MODULEThe integrated CAN module handles the com-
pletely autonomous transmission and reception of
CAN frames in accordance with the CAN specifi-
cation V2.0 part B (active) i.e. the on-chip CAN
module can receive and transmit standard frames
with 11-bit identifiers as well as extended frames
with 29-bit identifiers.
The CAN module provides full CAN functionality
on up to 15 message objects. Message object 15
can be configured for basic CAN functionality.
Both modes provide separate masks for accep-
tance filtering, allowing a number of identifiers in
full CAN mode to be accepted and disregarding a
number of identifiers in basic CAN mode.
All message objects can be updated independent
from other objects and are equipped for the maxi-
mum message length of 8 Byte.
The bit timing is derived from the XCLK and is pro-
grammable up to a data rate of 1M Baud. The
CAN module uses two pins to interface to a bus
transceiver.
15 - WATCHDOG TIMERThe Watchdog Timer is a fail-safe mechanism
which prevents the microcontroller from malfunc-
tioning for long periods of time. The Watchdog
Timer is always enabled after a reset of the chip
and can only be disabled in the time interval until
the EINIT (end of initialization) instruction has
been executed. Therefore, the chip start-up pro-
cedure is always monitored. The software must
be designed to service the watchdog timer before
it overflows. If, due to hardware or software
related failures, the software fails to do so, the
watchdog timer overflows and generates an inter-
nal hardware reset. It pulls the RSTOUT pin low in
order to allow external hardware components to
be reset.
The Watchdog Timer is 16-bit, clocked with the
system clock divided by 2 or 128. The high Byte of
the watchdog timer register can be set to a
pre-specified reload value (stored in WDTREL).
Each time it is serviced by the application soft-
ware, the high Byte of the watchdog timer is
reloaded. For security, rewrite WDTCON each
time before the watchdog timer is serviced
Table 12 : Watchdog time range for 25MHz CPU clock
ST10C16727/66
16 - INSTRUCTION SET SUMMARYThe table below lists the instructions of the
ST10C167. The various addressing modes,
instruction operation, parameters for conditional
execution of instructions, opcodes and a detailed
description of each instruction can be found in the
“ST10 Family Programming Manual”.
Table 13 : Instruction set summary
ST10C16728/66
Table 13 : Instruction set summary (continued)
ST10C16729/66
17 - SYSTEM RESETThe internal system reset function is invoked
either by asserting a hardware reset signal on pin
RSTIN (Hardware Reset Input), by the execution
of the SRST instruction (Software Reset) or by an
overflow of the watchdog timer. Whenever one of
these conditions occurs, the microcontroller is
reset into its predefined default state. The
following type of reset are implemented on the
ST10C167:
Asynchronous hardware resetAsynchronous reset does not require a stabilized
clock signal on XT AL1, as it is not internally resyn-
chronized. It immediately resets the microcontrol-
ler into its default reset state.
This asynchronous reset is required upon
power-up of the chip and may be used during cat-
astrophic situations. The rising edge of the RSTIN
pin is internally resynchronized before exiting the
reset condition. Therefore, only the entry of this
hardware reset is asynchronous.
Synchronous hardware reset (warm reset)A warm synchronous hardware reset is triggered
when the reset input signal RSTIN is latched low
and RPD (Pin 84) is high. The I/Os are
immediately (asynchronously) set in high
impedance, RSTOUT is driven low. After negation
of RSTIN is detected, a short transition period
elapses, during which pending internal hold states
are cancelled and any current internal access
cycles are completed, external bus cycles are
aborted.
Then, the internal reset sequence starts for 1024
TCL (512 CPU clock cycles). During this reset
sequence, if bit BDRSTEN was previously set by
software (bit 5 in SYSCON register), RSTIN pin is
driven low and internal reset signal is asserted to
reset the microcontroller in its default state. Note
that after all reset sequences, bit BDRSTEN is
cleared.
After the reset sequence has been completed, the
RSTIN input is sampled. If the reset input signal is
active at that time the internal reset condition is
prolonged until RSTIN becomes inactive.
Software resetThe reset sequence can be triggered at any time
by the protected instruction SRST (software
reset). This instruction can be executed
deliberately within a program, e.g. to leave
bootstrap loader mode, or on a hardware trap that
reveals a system failure. As for a synchronous
hardware reset, the reset sequence lasts 1024
TCL (512 CPU clock cycles), and drives the
RSTIN pin low.
Watchdog timer resetWhen the watchdog timer is not disabled during
the initialization or serviced regularly during
program execution it will overflow and trigger the
reset sequence.
Unlike hardware and software resets, the watch-
dog reset completes a running external bus cycle
if this bus cycle either does not use READY , or if
READY is sampled active (low) after the pro-
grammed waitstates.
When READY is sampled inactive (high) after the
programmed waitstates the running external bus
cycle is aborted. The internal reset sequence is
then started. The watchdog reset cannot occur
while the ST10C167 is in bootstrap loader mode.
Bidirectional resetThis feature is enabled by bit 3 of the SYSCON
register. The bidirectional reset makes the watch-
dog timer reset and software reset externally visi-
ble. It is active for the duration of an internal reset
sequences caused by a watchdog timer reset and
software reset.
This means that the bidirectional reset transforms
an internal watchdog timer reset or software reset
into an external hardware reset with a minimum
duration of 1024 TCL. The consequence is that
during a watchdog timer reset or software reset,
the behavior of the ST10C167 is equal to an
external hardware reset.
ST10C16730/66
18 - POWER REDUCTION MODESTwo different power reduction modes with differ-
ent levels of power reduction can be entered
under software control.
In
Idle mode the CPU is stopped, while the
peripherals continue their operation. Idle mode
can be terminated by any reset or interrupt
request.
In
Power Down mode both the CPU and the
peripherals are stopped. Power Down mode can
be configured by software in order to be termi-
nated only by a hardware reset or by an external
interrupt source on fast external interrupt pins.
There are two different operating Power Down
modes:
– Protected power down mode: selected by set-
ting bit PWDCFG in the SYSCON register to ‘0’.
This mode can be used in conjunction with an
external power failure signal which pulls the NMI
pin low when a power failure is imminent. The
microcontroller enters the NMI trap routine and
saves the internal state into RAM. The trap rou-
tine then sets a flag or writes a bit pattern into
specific RAM locations, and executes the
PWRDN instruction. If the NMI pin is still low at
this time, Power Down mode will be entered, if
not program execution continues. During power
down the voltage at the VCC pins can be lowered
to 2.5 V and the contents of the internal RAM will
still be preserved.
– Interruptible
power down mode: this
modeis selected by setting bit PWDCFG in the
SYSCON register. The CPU and peripheral
clocks are frozen, and the oscillator and PLL are
stopped. To exit power down mode with an ex-
ternal interrupt, an EXxIN (x = 7...0) pin has to
be asserted for at least 40ns. This signal ena-
bles the internal oscillator and PLL circuitry, and
turns on the weak pull-down. If the Interrupt was
enabled before entering power down mode, the
device executes the interrupt service routine,
and then resumes execution after the PWRDN
instruction. If the interrupt was disabled, the de-
vice executes the instruction following PWRDN
instruction, and the Interrupt Request Flag re-
mains set until it is cleared by software.
All external bus actions are completed before Idle
or Power Down mode is entered. However, Idle or
Power Down mode is not entered if READY is
enabled, but has not been activated during the
last bus access.
ST10C16731/66
19 - SPECIAL FUNCTION REGISTER OVERVIEWTable 14 lists all SFRs which are implemented the ST10C167in alphabetical order.
Bit-addressable SFRs are marked with the letter
“b” in column “Name”. SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter
“E” in column “Physical Address”.
An SFR can be specified by its individual
mnemonic name. Depending on the selected
addressing mode, an SFR can be accessed via its
physical address (using the Data Page Pointers),
or via its short 8-bit address (without using the
Data Page Pointers).
Table 14 : Special function registers listed by name
ST10C16732/66
Table 14 : Special function registers listed by name (continued)
ST10C16733/66
Table 14 : Special function registers listed by name (continued)
