IC Phoenix
 
Home ›  SS94 > ST10F280-Q3TR,16-BIT MCU WITH MAC UNIT
ST10F280-Q3TR Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
ST10F280-Q3TR |ST10F280Q3TRSTN/a350avai16-BIT MCU WITH MAC UNIT
ST10F280-Q3TR |ST10F280Q3TRSTMicroelectronicsN/a7300avai16-BIT MCU WITH MAC UNIT


ST10F280-Q3TR ,16-BIT MCU WITH MAC UNITFeatures 406.1.1.1 - Enhanced Addressing Capabilities...... 406.1.1.2 - Multiply-Accumulate Unit . ..
ST10F280-Q3TR ,16-BIT MCU WITH MAC UNITST10F28016-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAMPRODUCT PREVIEW■ HIGH PERF ..
ST10R167-Q3 ,16-BIT MCUST10C16716-BIT MCU WITH 32K BYTE ROM■ HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE– 80ns ..
ST10R167-Q6 ,16-BIT MCUABSOLUTE MAXIMUM RATINGS ..... 3820.2 PARAMETER INTERPRETATION ..... 3820.3 DC CHARACTERISTICS . 38 ..
ST10R167-Q6-TR ,16-BIT MCUST10R16716-BIT ROMLESS MCU■ HIGH PERFORMANCE CPU – 16-BIT CPU WITH 4-STAGE PIPELINE– 80ns INSTRUCTI ..
ST10R172LT1 ,16-BIT LOW VOLTAGE ROMLESS MCUTable of Contents15.3 AC CHARACTERISTICS . 3615.3.1 Cpu Clock Generation Mechanisms . . ..
STK4913 ,Thick Film Hybid Circuit 2-Channel 50W Min AF Power Amp
STK4913 ,Thick Film Hybid Circuit 2-Channel 50W Min AF Power Amp
STK5314 ,Thick Film Hybrid Integrated Circuit VOLTAGE REGULATORNo. 1146STK5314Thick Film Hybrid Integrated Ci rcuitVOLTAGE REGULATOR
STK5325 , 2-CHANNEL 10 TO 50W MIN AF POWER AMP.(DUAL-SUPPLY)
STK5325 , 2-CHANNEL 10 TO 50W MIN AF POWER AMP.(DUAL-SUPPLY)
STK5451 ,3-Output Series Regulator for VTR UseNo.1663STK5451Thiekimm Hybrid IC3-Output Series Regulator for VTR is,


ST10F280-Q3TR
16-BIT MCU WITH MAC UNIT
1/186
ST10F280

March 2003 HIGH PERFORMANCE CPU WITH DSP FUNCTIONS
- 16-BIT CPU WITH 4-STAGE PIPELINE.
- 50ns INSTRUCTION CYCLE TIME AT 40MHz CPU
CLOCK.
- MULTIPLY/ACCUMULATE UNIT (MAC) 16 X 16-BIT
MULTIPLICATION, 40-BIT ACCUMULATOR
- REPEAT UNIT.
- ENHANCED BOOLEAN BIT MANIPULATION FACILITIES.
- ADDITIONAL INSTRUCTIONS TO SUPPORT HLL
AND OPERATING SYSTEMS.
- SINGLE-CYCLE CONTEXT SWITCHING SUPPORT.� MEMORY ORGANIZATION
- 512K BYTE ON-CHIP FLASH MEMORY SINGLE
VOLTAGE WITH ERASE/PROGRAM CONTROLLER.
- 100K ERASING/PROGRAMMING CYCLES.
- 20 YEAR DATA RETENTION TIME
- UP TO 16M BYTE LINEAR ADDRESS SPACE FOR
CODE AND DATA (5M BYTE WITH CAN).
- 2K BYTE ON-CHIP INTERNAL RAM (IRAM).
- 16K BYTE EXTENSION RAM (XRAM). FAST AND FLEXIBLE BUS
- PROGRAMMABLE EXTERNAL BUS CHARACTERIS-
TICS FOR DIFFERENT ADDRESS RANGES.
- 8-BIT OR 16-BIT EXTERNAL DATA BUS.
- MULTIPLEXED OR DEMULTIPLEXED EXTERNAL
ADDRESS/DATA BUSES.
- FIVE PROGRAMMABLE CHIP-SELECT SIGNALS.
- HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT.� INTERRUPT
- 8-CHANNEL PERIPHERAL EVENT CONTROLLER
FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA
TRANSFER.
- 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH 56
SOURCES, SAMPLE-RATE DOWN TO 25ns. TWO MULTI-FUNCTIONAL GENERAL PURPOSE
TIMER UNITS WITH 5 TIMERS.� TWO 16-CHANNEL CAPTURE/COMPARE UNITS A/D CONVERTER
- 2X16-CHANNEL 10-BIT.
- 4.85μS CONVERSION TIME
- ONE TIMER FOR ADC CHANNEL INJECTION� 8-CHANNEL PWM UNIT SERIAL CHANNELS
- SYNCHRONOUS/ASYNC SERIAL CHANNEL
- HIGH-SPEED SYNCHRONOUS CHANNEL.� FAIL-SAFE PROTECTION
- PROGRAMMABLE WATCHDOG TIMER.
- OSCILLATOR WATCHDOG. TWO CAN 2.0b INTERFACES OPERATING ON ONE
OR TWO CAN BUSSES (30 OR 2X15 MESSAGE
OBJECTS) ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION
- ON-CHIP PLL.
- DIRECT OR PRESCALED CLOCK INPUT. UP TO 143 GENERAL PURPOSE I/O LINES
- INDIVIDUALLY PROGRAMMABLE AS INPUT, OUT-
PUT OR SPECIAL FUNCTION.
- PROGRAMMABLE THRESHOLD (HYSTERESIS). IDLE AND POWER DOWN MODES MAXIMUM CPU FREQUENCY 40MHz PACKAGE PBGA 208 BALLS (23mm x 23mm x
1.96 mm - PITCH 1.27mm). SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED
REGULATOR FOR 3.3 V CORE SUPPLY). TEMPERATURE RANGE: -40 +125°C
16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM
PRODUCT PREVIEW
ST10F280
2/186
TABLE OF CONTENTS
1 - INTRODUCTION ........................................................................................................ 6
2 - BALL DATA ............................................................................................................... 7
3 - FUNCTIONAL DESCRIPTION ................................................................................... 17
4 - MEMORY ORGANIZATION ....................................................................................... 18
5 - INTERNAL FLASH MEMORY ................................................................................... 21

5.1 - OVERVIEW ................................................................................................................ 21
5.2 - OPERATIONAL OVERVIEW ...................................................................................... 21
5.3 - ARCHITECTURAL DESCRIPTION ............................................................................ 23
5.3.1 - Read Mode ................................................................................................................. 23
5.3.2 - Command Mode ......................................................................................................... 23
5.3.3 - Flash Status Register ................................................................................................. 23
5.3.4 - Flash Protection Register ........................................................................................... 25
5.3.5 - Instructions Description .............................................................................................. 25
5.3.6 - Reset Processing and Initial State .............................................................................. 29
5.4 - FLASH MEMORY CONFIGURATION ........................................................................ 29
5.5 - APPLICATION EXAMPLES ....................................................................................... 29
5.5.1 - Handling of Flash Addresses ...................................................................................... 29
5.5.2 - Basic Flash Access Control ........................................................................................ 30
5.5.3 - Programming Examples ............................................................................................. 31
5.6 - BOOTSTRAP LOADER ............................................................................................ 34
5.6.1 - Entering the Bootstrap Loader .................................................................................... 34
5.6.2 - Memory Configuration After Reset ............................................................................. 35
5.6.3 - Loading the Startup Code ........................................................................................... 36
5.6.4 - Exiting Bootstrap Loader Mode .................................................................................. 36
5.6.5 - Choosing the Baud Rate for the BSL ......................................................................... 37
6 - CENTRAL PROCESSING UNIT (CPU) ..................................................................... 38

6.1 - MULTIPLIER-ACCUMULATOR UNIT (MAC) ............................................................. 39
6.1.1 - Features ..................................................................................................................... 40
6.1.1.1 - Enhanced Addressing Capabilities .............................................................................. 40
6.1.1.2 - Multiply-Accumulate Unit ............................................................................................. 40
6.1.1.3 - Program Control .......................................................................................................... 40
6.2 - INSTRUCTION SET SUMMARY ................................................................................ 41
6.3 - MAC COPROCESSOR SPECIFIC INSTRUCTIONS ................................................. 42
7 - EXTERNAL BUS CONTROLLER .............................................................................. 46

7.1 - PROGRAMMABLE CHIP SELECT TIMING CONTROL ............................................ 46
7.2 - READY PROGRAMMABLE POLARITY ..................................................................... 47
8 - INTERRUPT SYSTEM ............................................................................................... 49

8.1 - EXTERNAL INTERRUPTS ......................................................................................... 49
ST10F280
3/186
8.2 - INTERRUPT REGISTERS AND VECTORS LOCATION LIST .................................. 50
8.3 - INTERRUPT CONTROL REGISTERS ....................................................................... 52
8.4 - EXCEPTION AND ERROR TRAPS LIST ................................................................... 53
9 - CAPTURE/COMPARE (CAPCOM) UNITS ................................................................ 54
10 - GENERAL PURPOSE TIMER UNIT .......................................................................... 57

10.1 - GPT1 .................................................................................................................... ...... 57
10.2 - GPT2 .......................................................................................................................... 58
11 - PWM MODULE .......................................................................................................... 60

11.1 - STANDARD PWM MODULE ...................................................................................... 60
11.2 - NEW PWM MODULE : XPWM ................................................................................... 61
11.2.1 - Operating Modes ........................................................................................................62
11.2.1.1 - Mode 0: Standard PWM Generation (Edge Aligned PWM)......................................... 62
11.2.1.2 - Mode 1: Symmetrical PWM Generation (Center Aligned PWM) ................................. 63
11.2.1.3 - Burst Mode ................................................................................................................ 64
11.2.1.4 - Single Shot Mode ...................................................................................................... 65
11.2.2 - XPWM Module Registers ........................................................................................... 66
11.2.3 - Interrupt Request Generation ..................................................................................... 68
11.2.4 - XPWM Output Signals ................................................................................................ 68
11.2.5 - XPOLAR Register (polarity of the XPWM channel) .................................................... 69
12 - PARALLEL PORTS ................................................................................................... 70

12.1 - INTRODUCTION ........................................................................................................ 72
12.1.1 - Open Drain Mode ....................................................................................................... 72
12.1.2 - Input Threshold Control ............................................................................................ 73
12.1.3 - Output Driver Control ................................................................................................73
12.1.4 - Alternate Port Functions ............................................................................................. 75
12.2 - PORT0 ........................................................................................................................ 76
12.2.1 - Alternate Functions of PORT0 .................................................................................... 77
12.3 - PORT1 ........................................................................................................................ 79
12.3.1 - Alternate Functions of PORT1 .................................................................................... 79
12.4 - PORT 2 ....................................................................................................................... 80
12.4.1 - Alternate Functions of Port 2 ..................................................................................... 81
12.5 - PORT 3 ....................................................................................................................... 84
12.5.1 - Alternate Functions of Port 3 ...................................................................................... 85
12.6 - PORT 4 ....................................................................................................................... 87
12.6.1 - Alternate Functions of Port 4 ...................................................................................... 88
12.7 - PORT 5 ....................................................................................................................... 92
12.7.1 - Port 5 Schmitt Trigger Analog Inputs .......................................................................... 93
12.8 - PORT 6 ....................................................................................................................... 93
12.8.1 - Alternate Functions of Port 6 ...................................................................................... 94
12.9 - PORT 7 ....................................................................................................................... 95
12.9.1 - Alternate Functions of Port 7 ...................................................................................... 96
ST10F280
4/186
12.10 - PORT 8 ....................................................................................................................... 99
12.10.1 - Alternate Functions of Port 8 ...................................................................................... 99
12.11 - XPORT 9 .................................................................................................................... 101
12.12 - XPORT 10 .................................................................................................................. 103
12.12.1 - Alternate Functions of XPort 10 .................................................................................. 103
12.12.2 - New Disturb Protection on Analog Inputs ................................................................... 104
13 - A/D CONVERTER ...................................................................................................... 105

13.1 - A/D CONVERTER MODULE ...................................................................................... 105
13.2 - MULTIPLEXAGE OF TWO BLOCKS OF 16 ANALOG INPUTS ................................ 106
13.3 - XTIMER PERIPHERAL (TRIGGER FOR ADC CHANNEL INJECTION) ................... 107
13.3.1 - Main Features ............................................................................................................. 107
13.3.2 - Register Description ...................................................................................................108
13.3.2.1 - TCR : Timer Control Register ...................................................................................... 108
13.3.2.2 - XTSVR :Timer Start Value Register ............................................................................ 109
13.3.2.3 - XTEVR : Timer End Value Register ............................................................................ 109
13.3.2.4 - XTCVR : Timer Current Value Register....................................................................... 109
13.3.2.5 - Registers Mapping....................................................................................................... 109
13.3.3 - Block Diagram ........................................................................................................... 110
13.3.3.1 - Clocks.......................................................................................................................... 110
13.3.3.2 - Registers ..................................................................................................................... 110
13.3.3.3 - Timer output (XADCINJ).............................................................................................. 111
14 - SERIAL CHANNELS ................................................................................................. 112

14.1 - ASYNCHRONOUS / SYNCHRONOUS SERIAL INTERFACE (ASCO) .................... 112
14.1.1 - ASCO in Asynchronous Mode .................................................................................... 112
14.1.2 - ASCO in Synchronous Mode ...................................................................................... 114
14.2 - HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) ..................................... 116
15 - CAN MODULES ......................................................................................................... 118

15.1 - MEMORY MAPPING .................................................................................................. 118
15.1.1 - CAN1 .......................................................................................................................... 118
15.1.2 - CAN2 .......................................................................................................................... 118
15.2 - CAN BUS CONFIGURATIONS .................................................................................. 118
15.3 - REGISTER AND MESSAGE OBJECT ORGANIZATION .......................................... 119
15.4 - CAN INTERRUPT HANDLING ................................................................................. 121
15.5 - THE MESSAGE OBJECT .......................................................................................... 124
15.6 - ARBITRATION REGISTERS ...................................................................................... 126
16 - WATCHDOG TIMER .................................................................................................. 127
17 - SYSTEM RESET ........................................................................................................ 129

17.1 - ASYNCHRONOUS RESET (LONG HARDWARE RESET) ....................................... 129
17.2 - SYNCHRONOUS RESET (WARM RESET) .............................................................. 130
ST10F280
5/186
17.3 - SOFTWARE RESET .................................................................................................. 131
17.4 - WATCHDOG TIMER RESET ..................................................................................... 131
17.5 - RSTOUT PIN AND BIDIRECTIONAL RESET ............................................................ 131
17.6 - RESET CIRCUITRY ................................................................................................... 132
18 - POWER REDUCTION MODES ................................................................................. 135

18.1 - IDLE MODE ................................................................................................................135
18.2 - POWER DOWN MODE .............................................................................................. 135
18.2.1 - Protected Power Down Mode ..................................................................................... 136
18.2.2 - Interruptable Power Down Mode ................................................................................ 136
19 - SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... 139

19.1 - IDENTIFICATION REGISTERS ................................................................................. 148
19.2 - SYSTEM CONFIGURATION REGISTERS ................................................................ 149
20 - ELECTRICAL CHARACTERISTICS ......................................................................... 155

20.1 - ABSOLUTE MAXIMUM RATINGS ............................................................................. 155
20.2 - PARAMETER INTERPRETATION ............................................................................. 155
20.3 - DC CHARACTERISTICS ........................................................................................... 155
20.3.1 - A/D Converter Characteristics .................................................................................... 158
20.3.2 - Conversion Timing Control ....................................................................................... 159
20.4 - AC CHARACTERISTICS ............................................................................................ 160
20.4.1 - Test Waveforms .......................................................................................................160
20.4.2 - Definition of Internal Timing ........................................................................................ 160
20.4.3 - Clock Generation Modes ............................................................................................ 161
20.4.4 - Prescaler Operation ....................................................................................................162
20.4.5 - Direct Drive ................................................................................................................. 162
20.4.6 - Oscillator Watchdog (OWD) ....................................................................................... 162
20.4.7 - Phase Locked Loop .................................................................................................... 162
20.4.8 - External Clock Drive XTAL1 ....................................................................................... 163
20.4.9 - Memory Cycle Variables ............................................................................................. 164
20.4.10 - Multiplexed Bus .......................................................................................................... 165
20.4.11 - Demultiplexed Bus ...................................................................................................... 171
20.4.12 - CLKOUT and READY ................................................................................................. 177
20.4.13 - External Bus Arbitration ..............................................................................................179
20.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing ........................................... 181
20.4.14.1 Master Mode................................................................................................................ 181
20.4.14.2 Slave mode.................................................................................................................. 182
21 - PACKAGE MECHANICAL DATA ........................................................................... 183
22 - ORDERING INFORMATION ...................................................................................... 184
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED